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riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation
Add the actual support code for SPL_ZERO_MEM_BEFORE_USE and remove existing Starfive JH7110's L2 LIM clean code, since existing code has following issues: 1. Each hart (in the middle of a function call) overwriting its own stack and other harts' stacks. (data-race and data-corruption) 2. Lottery winner hart can be doing "board_init_f_init_reserve", while other harts are in the middle of zeroing L2 LIM. (data-race) Signed-off-by: Bo Gan <ganboing@gmail.com> Signed-off-by: Shengyu Qu <wiagn233@outlook.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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3 changed files with 15 additions and 25 deletions
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@ -13,7 +13,6 @@
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#include <init.h>
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#include <init.h>
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#define CSR_U74_FEATURE_DISABLE 0x7c1
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#define CSR_U74_FEATURE_DISABLE 0x7c1
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#define L2_LIM_MEM_END 0x81FFFFFUL
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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@ -59,9 +58,6 @@ int spl_soc_init(void)
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void harts_early_init(void)
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void harts_early_init(void)
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{
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{
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ulong *ptr;
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u8 *tmp;
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ulong len, remain;
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/*
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/*
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* Feature Disable CSR
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* Feature Disable CSR
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*
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*
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@ -70,25 +66,4 @@ void harts_early_init(void)
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*/
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*/
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if (CONFIG_IS_ENABLED(RISCV_MMODE))
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if (CONFIG_IS_ENABLED(RISCV_MMODE))
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csr_write(CSR_U74_FEATURE_DISABLE, 0);
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csr_write(CSR_U74_FEATURE_DISABLE, 0);
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/* clear L2 LIM memory
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* set __bss_end to 0x81FFFFF region to zero
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* The L2 Cache Controller supports ECC. ECC is applied to SRAM.
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* If it is not cleared, the ECC part is invalid, and an ECC error
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* will be reported when reading data.
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*/
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ptr = (ulong *)&__bss_end;
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len = L2_LIM_MEM_END - (ulong)&__bss_end;
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remain = len % sizeof(ulong);
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len /= sizeof(ulong);
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while (len--)
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*ptr++ = 0;
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/* clear the remain bytes */
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if (remain) {
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tmp = (u8 *)ptr;
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while (remain--)
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*tmp++ = 0;
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}
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}
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}
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@ -111,6 +111,18 @@ call_board_init_f:
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* It's essential before any function call, otherwise, we get data-race.
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* It's essential before any function call, otherwise, we get data-race.
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*/
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*/
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/* clear stack if necessary */
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#if CONFIG_IS_ENABLED(ZERO_MEM_BEFORE_USE)
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clear_stack:
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li t1, 1
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slli t1, t1, CONFIG_STACK_SIZE_SHIFT
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sub t1, sp, t1
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clear_stack_loop:
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SREG zero, 0(t1) /* t1 is always 16 byte aligned */
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addi t1, t1, REGBYTES
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blt t1, sp, clear_stack_loop
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#endif
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call_board_init_f_0:
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call_board_init_f_0:
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/* find top of reserve space */
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/* find top of reserve space */
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#if CONFIG_IS_ENABLED(SMP)
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#if CONFIG_IS_ENABLED(SMP)
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@ -162,6 +162,9 @@ void board_init_f_init_reserve(ulong base)
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#if CONFIG_VAL(SYS_MALLOC_F_LEN)
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#if CONFIG_VAL(SYS_MALLOC_F_LEN)
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/* go down one 'early malloc arena' */
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/* go down one 'early malloc arena' */
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gd->malloc_base = base;
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gd->malloc_base = base;
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#if CONFIG_IS_ENABLED(ZERO_MEM_BEFORE_USE)
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memset((void *)base, '\0', CONFIG_VAL(SYS_MALLOC_F_LEN));
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#endif
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#endif
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#endif
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if (CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE))
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if (CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE))
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