mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
dnet: driver for Dave DNET ethernet controller
Driver for Dave DNET ethernet controller (used on Dave/DENX QongEVB-LITE board). Signed-off-by: Ilya Yanok <yanok@emcraft.com> Acked-by: Ben Warren <biggerbadderben@gmail.com>
This commit is contained in:
Ilya Yanok
Jean-Christophe PLAGNIOL-VILLARD
parent
54dc517328
commit
62cbc408f5
4 changed files with 564 additions and 0 deletions
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@ -33,6 +33,7 @@ COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o
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COBJS-$(CONFIG_DRIVER_CS8900) += cs8900.o
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COBJS-$(CONFIG_TULIP) += dc2114x.o
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COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o
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COBJS-$(CONFIG_DNET) += dnet.o
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COBJS-$(CONFIG_E1000) += e1000.o
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COBJS-$(CONFIG_EEPRO100) += eepro100.o
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COBJS-$(CONFIG_ENC28J60) += enc28j60.o
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396
drivers/net/dnet.c
Normal file
396
drivers/net/dnet.c
Normal file
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@ -0,0 +1,396 @@
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/*
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* Dave Ethernet Controller driver
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*
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* Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <common.h>
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#ifndef CONFIG_DNET_AUTONEG_TIMEOUT
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#define CONFIG_DNET_AUTONEG_TIMEOUT 5000000 /* default value */
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#endif
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#include <net.h>
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#include <malloc.h>
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#include <linux/mii.h>
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#include <miiphy.h>
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#include <asm/io.h>
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#include "dnet.h"
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struct dnet_device {
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struct dnet_registers *regs;
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const struct device *dev;
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struct eth_device netdev;
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unsigned short phy_addr;
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};
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/* get struct dnet_device from given struct netdev */
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#define to_dnet(_nd) container_of(_nd, struct dnet_device, netdev)
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/* function for reading internal MAC register */
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u16 dnet_readw_mac(struct dnet_device *dnet, u16 reg)
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{
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u16 data_read;
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/* issue a read */
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writel(reg, &dnet->regs->MACREG_ADDR);
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/* since a read/write op to the MAC is very slow,
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* we must wait before reading the data */
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udelay(1);
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/* read data read from the MAC register */
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data_read = readl(&dnet->regs->MACREG_DATA);
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/* all done */
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return data_read;
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}
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/* function for writing internal MAC register */
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void dnet_writew_mac(struct dnet_device *dnet, u16 reg, u16 val)
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{
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/* load data to write */
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writel(val, &dnet->regs->MACREG_DATA);
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/* issue a write */
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writel(reg | DNET_INTERNAL_WRITE, &dnet->regs->MACREG_ADDR);
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/* since a read/write op to the MAC is very slow,
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* we must wait before exiting */
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udelay(1);
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}
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static void dnet_mdio_write(struct dnet_device *dnet, u8 reg, u16 value)
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{
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u16 tmp;
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debug(DRIVERNAME "dnet_mdio_write %02x:%02x <- %04x\n",
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dnet->phy_addr, reg, value);
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while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
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DNET_INTERNAL_GMII_MNG_CMD_FIN))
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;
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/* prepare for a write operation */
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tmp = (1 << 13);
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/* only 5 bits allowed for register offset */
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reg &= 0x1f;
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/* prepare reg_value for a write */
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tmp |= (dnet->phy_addr << 8);
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tmp |= reg;
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/* write data to write first */
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dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_DAT_REG, value);
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/* write control word */
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dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG, tmp);
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while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
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DNET_INTERNAL_GMII_MNG_CMD_FIN))
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;
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}
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static u16 dnet_mdio_read(struct dnet_device *dnet, u8 reg)
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{
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u16 value;
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while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
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DNET_INTERNAL_GMII_MNG_CMD_FIN))
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;
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/* only 5 bits allowed for register offset*/
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reg &= 0x1f;
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/* prepare reg_value for a read */
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value = (dnet->phy_addr << 8);
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value |= reg;
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/* write control word */
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dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG, value);
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/* wait for end of transfer */
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while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) &
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DNET_INTERNAL_GMII_MNG_CMD_FIN))
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;
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value = dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_DAT_REG);
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debug(DRIVERNAME "dnet_mdio_read %02x:%02x <- %04x\n",
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dnet->phy_addr, reg, value);
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return value;
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}
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static int dnet_send(struct eth_device *netdev, volatile void *packet,
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int length)
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{
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struct dnet_device *dnet = to_dnet(netdev);
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int i, len, wrsz;
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unsigned int *bufp;
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unsigned int tx_cmd;
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debug(DRIVERNAME "[%s] Sending %u bytes\n", __func__, length);
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/* frame size (words) */
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len = (length + 3) >> 2;
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bufp = (unsigned int *) (((u32)packet) & 0xFFFFFFFC);
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wrsz = (u32)length + 3;
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wrsz += ((u32)packet) & 0x3;
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wrsz >>= 2;
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tx_cmd = ((((unsigned int)(packet)) & 0x03) << 16) | (u32)length;
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/* check if there is enough room for the current frame */
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if (wrsz < (DNET_FIFO_SIZE - readl(&dnet->regs->TX_FIFO_WCNT))) {
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for (i = 0; i < wrsz; i++)
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writel(*bufp++, &dnet->regs->TX_DATA_FIFO);
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/*
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* inform MAC that a packet's written and ready
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* to be shipped out
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*/
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writel(tx_cmd, &dnet->regs->TX_LEN_FIFO);
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} else {
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printf(DRIVERNAME "No free space (actual %d, required %d "
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"(words))\n", DNET_FIFO_SIZE -
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readl(&dnet->regs->TX_FIFO_WCNT), wrsz);
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}
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/* No one cares anyway */
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return 0;
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}
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static int dnet_recv(struct eth_device *netdev)
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{
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struct dnet_device *dnet = to_dnet(netdev);
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unsigned int *data_ptr;
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int pkt_len, poll, i;
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u32 cmd_word;
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debug("Waiting for pkt (polling)\n");
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poll = 50;
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while ((readl(&dnet->regs->RX_FIFO_WCNT) >> 16) == 0) {
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udelay(10); /* wait 10 usec */
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if (--poll == 0)
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return 0; /* no pkt available */
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}
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cmd_word = readl(&dnet->regs->RX_LEN_FIFO);
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pkt_len = cmd_word & 0xFFFF;
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debug("Got pkt with size %d bytes\n", pkt_len);
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if (cmd_word & 0xDF180000)
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printf("%s packet receive error %x\n", __func__, cmd_word);
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data_ptr = (unsigned int *) NetRxPackets[0];
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for (i = 0; i < (pkt_len + 3) >> 2; i++)
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*data_ptr++ = readl(&dnet->regs->RX_DATA_FIFO);
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NetReceive(NetRxPackets[0], pkt_len + 5); /* ok + 5 ?? */
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return 0;
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}
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static void dnet_set_hwaddr(struct eth_device *netdev)
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{
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struct dnet_device *dnet = to_dnet(netdev);
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u16 tmp;
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tmp = cpu_to_be16(*((u16 *)netdev->enetaddr));
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dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_0_REG, tmp);
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tmp = cpu_to_be16(*((u16 *)(netdev->enetaddr + 2)));
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dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_1_REG, tmp);
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tmp = cpu_to_be16(*((u16 *)(netdev->enetaddr + 4)));
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dnet_writew_mac(dnet, DNET_INTERNAL_MAC_ADDR_2_REG, tmp);
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}
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static void dnet_phy_reset(struct dnet_device *dnet)
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{
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struct eth_device *netdev = &dnet->netdev;
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int i;
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u16 status, adv;
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adv = ADVERTISE_CSMA | ADVERTISE_ALL;
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dnet_mdio_write(dnet, MII_ADVERTISE, adv);
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printf("%s: Starting autonegotiation...\n", netdev->name);
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dnet_mdio_write(dnet, MII_BMCR, (BMCR_ANENABLE
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| BMCR_ANRESTART));
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for (i = 0; i < CONFIG_DNET_AUTONEG_TIMEOUT / 100; i++) {
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status = dnet_mdio_read(dnet, MII_BMSR);
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if (status & BMSR_ANEGCOMPLETE)
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break;
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udelay(100);
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}
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if (status & BMSR_ANEGCOMPLETE)
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printf("%s: Autonegotiation complete\n", netdev->name);
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else
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printf("%s: Autonegotiation timed out (status=0x%04x)\n",
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netdev->name, status);
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}
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static int dnet_phy_init(struct dnet_device *dnet)
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{
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struct eth_device *netdev = &dnet->netdev;
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u16 phy_id, status, adv, lpa;
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int media, speed, duplex;
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int i;
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u32 ctl_reg;
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/* Find a PHY */
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for (i = 0; i < 32; i++) {
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dnet->phy_addr = i;
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phy_id = dnet_mdio_read(dnet, MII_PHYSID1);
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if (phy_id != 0xffff) {
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/* ok we found it */
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printf("Found PHY at address %d PHYID (%04x:%04x)\n",
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i, phy_id,
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dnet_mdio_read(dnet, MII_PHYSID2));
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break;
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}
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}
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/* Check if the PHY is up to snuff... */
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phy_id = dnet_mdio_read(dnet, MII_PHYSID1);
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if (phy_id == 0xffff) {
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printf("%s: No PHY present\n", netdev->name);
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return -1;
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}
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status = dnet_mdio_read(dnet, MII_BMSR);
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if (!(status & BMSR_LSTATUS)) {
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/* Try to re-negotiate if we don't have link already. */
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dnet_phy_reset(dnet);
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for (i = 0; i < CONFIG_DNET_AUTONEG_TIMEOUT / 100; i++) {
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status = dnet_mdio_read(dnet, MII_BMSR);
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if (status & BMSR_LSTATUS)
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break;
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udelay(100);
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}
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}
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if (!(status & BMSR_LSTATUS)) {
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printf("%s: link down (status: 0x%04x)\n",
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netdev->name, status);
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return -1;
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} else {
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adv = dnet_mdio_read(dnet, MII_ADVERTISE);
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lpa = dnet_mdio_read(dnet, MII_LPA);
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media = mii_nway_result(lpa & adv);
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speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
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? 1 : 0);
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duplex = (media & ADVERTISE_FULL) ? 1 : 0;
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/* 1000BaseT ethernet is not supported */
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printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
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netdev->name,
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speed ? "100" : "10",
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duplex ? "full" : "half",
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lpa);
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ctl_reg = dnet_readw_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG);
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if (duplex)
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ctl_reg &= ~(DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP);
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else
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ctl_reg |= DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP;
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dnet_writew_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg);
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return 0;
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}
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}
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static int dnet_init(struct eth_device *netdev, bd_t *bd)
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{
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struct dnet_device *dnet = to_dnet(netdev);
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u32 config;
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/*
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* dnet_halt should have been called at some point before now,
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* so we'll assume the controller is idle.
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*/
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/* set hardware address */
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dnet_set_hwaddr(netdev);
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if (dnet_phy_init(dnet) < 0)
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return -1;
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/* flush rx/tx fifos */
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writel(DNET_SYS_CTL_RXFIFOFLUSH | DNET_SYS_CTL_TXFIFOFLUSH,
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&dnet->regs->SYS_CTL);
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udelay(1000);
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writel(0, &dnet->regs->SYS_CTL);
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config = dnet_readw_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG);
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config |= DNET_INTERNAL_RXTX_CONTROL_RXPAUSE |
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DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST |
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DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL |
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DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS;
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dnet_writew_mac(dnet, DNET_INTERNAL_RXTX_CONTROL_REG, config);
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/* Enable TX and RX */
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dnet_writew_mac(dnet, DNET_INTERNAL_MODE_REG,
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DNET_INTERNAL_MODE_RXEN | DNET_INTERNAL_MODE_TXEN);
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return 0;
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}
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static void dnet_halt(struct eth_device *netdev)
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{
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struct dnet_device *dnet = to_dnet(netdev);
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/* Disable TX and RX */
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dnet_writew_mac(dnet, DNET_INTERNAL_MODE_REG, 0);
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}
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int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr)
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{
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struct dnet_device *dnet;
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struct eth_device *netdev;
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unsigned int dev_capa;
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dnet = malloc(sizeof(struct dnet_device));
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if (!dnet) {
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printf("Error: Failed to allocate memory for DNET%d\n", id);
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return -1;
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}
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memset(dnet, 0, sizeof(struct dnet_device));
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netdev = &dnet->netdev;
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dnet->regs = (struct dnet_registers *)regs;
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dnet->phy_addr = phy_addr;
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sprintf(netdev->name, "dnet%d", id);
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netdev->init = dnet_init;
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netdev->halt = dnet_halt;
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netdev->send = dnet_send;
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netdev->recv = dnet_recv;
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dev_capa = readl(&dnet->regs->VERCAPS) & 0xFFFF;
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debug("%s: has %smdio, %sirq, %sgigabit, %sdma \n", netdev->name,
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(dev_capa & DNET_HAS_MDIO) ? "" : "no ",
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(dev_capa & DNET_HAS_IRQ) ? "" : "no ",
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(dev_capa & DNET_HAS_GIGABIT) ? "" : "no ",
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(dev_capa & DNET_HAS_DMA) ? "" : "no ");
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eth_register(netdev);
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return 0;
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}
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166
drivers/net/dnet.h
Normal file
166
drivers/net/dnet.h
Normal file
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@ -0,0 +1,166 @@
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/*
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* Dave Ethernet Controller driver
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*
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* Copyright (C) 2008 Dave S.r.l. <www.dave.eu>
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __DRIVERS_DNET_H__
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#define __DRIVERS_DNET_H__
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#define DRIVERNAME "dnet"
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struct dnet_registers {
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/* ALL DNET FIFO REGISTERS */
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u32 RX_LEN_FIFO;
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u32 RX_DATA_FIFO;
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u32 TX_LEN_FIFO;
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u32 TX_DATA_FIFO;
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u32 pad1[0x3c];
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/* ALL DNET CONTROL/STATUS REGISTERS */
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u32 VERCAPS;
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u32 INTR_SRC;
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u32 INTR_ENB;
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u32 RX_STATUS;
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u32 TX_STATUS;
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u32 RX_FRAMES_CNT;
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u32 TX_FRAMES_CNT;
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u32 RX_FIFO_TH;
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u32 TX_FIFO_TH;
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u32 SYS_CTL;
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u32 PAUSE_TMR;
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u32 RX_FIFO_WCNT;
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u32 TX_FIFO_WCNT;
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u32 pad2[0x33];
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/* ALL DNET MAC REGISTERS */
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u32 MACREG_DATA; /* Mac-Reg Data */
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u32 MACREG_ADDR; /* Mac-Reg Addr */
|
||||
u32 pad3[0x3e];
|
||||
/* ALL DNET RX STATISTICS COUNTERS */
|
||||
u32 RX_PKT_IGNR_CNT;
|
||||
u32 RX_LEN_CHK_ERR_CNT;
|
||||
u32 RX_LNG_FRM_CNT;
|
||||
u32 RX_SHRT_FRM_CNT;
|
||||
u32 RX_IPG_VIOL_CNT;
|
||||
u32 RX_CRC_ERR_CNT;
|
||||
u32 RX_OK_PKT_CNT;
|
||||
u32 RX_CTL_FRM_CNT;
|
||||
u32 RX_PAUSE_FRM_CNT;
|
||||
u32 RX_MULTICAST_CNT;
|
||||
u32 RX_BROADCAST_CNT;
|
||||
u32 RX_VLAN_TAG_CNT;
|
||||
u32 RX_PRE_SHRINK_CNT;
|
||||
u32 RX_DRIB_NIB_CNT;
|
||||
u32 RX_UNSUP_OPCD_CNT;
|
||||
u32 RX_BYTE_CNT;
|
||||
u32 pad4[0x30];
|
||||
/* DNET TX STATISTICS COUNTERS */
|
||||
u32 TX_UNICAST_CNT;
|
||||
u32 TX_PAUSE_FRM_CNT;
|
||||
u32 TX_MULTICAST_CNT;
|
||||
u32 TX_BRDCAST_CNT;
|
||||
u32 TX_VLAN_TAG_CNT;
|
||||
u32 TX_BAD_FCS_CNT;
|
||||
u32 TX_JUMBO_CNT;
|
||||
u32 TX_BYTE_CNT;
|
||||
};
|
||||
|
||||
/* SOME INTERNAL MAC-CORE REGISTER */
|
||||
#define DNET_INTERNAL_MODE_REG 0x0
|
||||
#define DNET_INTERNAL_RXTX_CONTROL_REG 0x2
|
||||
#define DNET_INTERNAL_MAX_PKT_SIZE_REG 0x4
|
||||
#define DNET_INTERNAL_IGP_REG 0x8
|
||||
#define DNET_INTERNAL_MAC_ADDR_0_REG 0xa
|
||||
#define DNET_INTERNAL_MAC_ADDR_1_REG 0xc
|
||||
#define DNET_INTERNAL_MAC_ADDR_2_REG 0xe
|
||||
#define DNET_INTERNAL_TX_RX_STS_REG 0x12
|
||||
#define DNET_INTERNAL_GMII_MNG_CTL_REG 0x14
|
||||
#define DNET_INTERNAL_GMII_MNG_DAT_REG 0x16
|
||||
|
||||
#define DNET_INTERNAL_GMII_MNG_CMD_FIN (1 << 14)
|
||||
|
||||
#define DNET_INTERNAL_WRITE (1 << 31)
|
||||
|
||||
/* MAC-CORE REGISTER FIELDS */
|
||||
|
||||
/* MAC-CORE MODE REGISTER FIELDS */
|
||||
#define DNET_INTERNAL_MODE_GBITEN (1 << 0)
|
||||
#define DNET_INTERNAL_MODE_FCEN (1 << 1)
|
||||
#define DNET_INTERNAL_MODE_RXEN (1 << 2)
|
||||
#define DNET_INTERNAL_MODE_TXEN (1 << 3)
|
||||
|
||||
/* MAC-CORE RXTX CONTROL REGISTER FIELDS */
|
||||
#define DNET_INTERNAL_RXTX_CONTROL_RXSHORTFRAME (1 << 8)
|
||||
#define DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST (1 << 7)
|
||||
#define DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST (1 << 4)
|
||||
#define DNET_INTERNAL_RXTX_CONTROL_RXPAUSE (1 << 3)
|
||||
#define DNET_INTERNAL_RXTX_CONTROL_DISTXFCS (1 << 2)
|
||||
#define DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS (1 << 1)
|
||||
#define DNET_INTERNAL_RXTX_CONTROL_ENPROMISC (1 << 0)
|
||||
#define DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL (1 << 6)
|
||||
#define DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP (1 << 5)
|
||||
|
||||
/* SYSTEM CONTROL REGISTER FIELDS */
|
||||
#define DNET_SYS_CTL_IGNORENEXTPKT (1 << 0)
|
||||
#define DNET_SYS_CTL_SENDPAUSE (1 << 2)
|
||||
#define DNET_SYS_CTL_RXFIFOFLUSH (1 << 3)
|
||||
#define DNET_SYS_CTL_TXFIFOFLUSH (1 << 4)
|
||||
|
||||
/* TX STATUS REGISTER FIELDS */
|
||||
#define DNET_TX_STATUS_FIFO_ALMOST_EMPTY (1 << 2)
|
||||
#define DNET_TX_STATUS_FIFO_ALMOST_FULL (1 << 1)
|
||||
|
||||
/* INTERRUPT SOURCE REGISTER FIELDS */
|
||||
#define DNET_INTR_SRC_TX_PKTSENT (1 << 0)
|
||||
#define DNET_INTR_SRC_TX_FIFOAF (1 << 1)
|
||||
#define DNET_INTR_SRC_TX_FIFOAE (1 << 2)
|
||||
#define DNET_INTR_SRC_TX_DISCFRM (1 << 3)
|
||||
#define DNET_INTR_SRC_TX_FIFOFULL (1 << 4)
|
||||
#define DNET_INTR_SRC_RX_CMDFIFOAF (1 << 8)
|
||||
#define DNET_INTR_SRC_RX_CMDFIFOFF (1 << 9)
|
||||
#define DNET_INTR_SRC_RX_DATAFIFOFF (1 << 10)
|
||||
#define DNET_INTR_SRC_TX_SUMMARY (1 << 16)
|
||||
#define DNET_INTR_SRC_RX_SUMMARY (1 << 17)
|
||||
#define DNET_INTR_SRC_PHY (1 << 19)
|
||||
|
||||
/* INTERRUPT ENABLE REGISTER FIELDS */
|
||||
#define DNET_INTR_ENB_TX_PKTSENT (1 << 0)
|
||||
#define DNET_INTR_ENB_TX_FIFOAF (1 << 1)
|
||||
#define DNET_INTR_ENB_TX_FIFOAE (1 << 2)
|
||||
#define DNET_INTR_ENB_TX_DISCFRM (1 << 3)
|
||||
#define DNET_INTR_ENB_TX_FIFOFULL (1 << 4)
|
||||
#define DNET_INTR_ENB_RX_PKTRDY (1 << 8)
|
||||
#define DNET_INTR_ENB_RX_FIFOAF (1 << 9)
|
||||
#define DNET_INTR_ENB_RX_FIFOERR (1 << 10)
|
||||
#define DNET_INTR_ENB_RX_ERROR (1 << 11)
|
||||
#define DNET_INTR_ENB_RX_FIFOFULL (1 << 12)
|
||||
#define DNET_INTR_ENB_RX_FIFOAE (1 << 13)
|
||||
#define DNET_INTR_ENB_TX_SUMMARY (1 << 16)
|
||||
#define DNET_INTR_ENB_RX_SUMMARY (1 << 17)
|
||||
#define DNET_INTR_ENB_GLOBAL_ENABLE (1 << 18)
|
||||
|
||||
/*
|
||||
* Capabilities. Used by the driver to know the capabilities that
|
||||
* the ethernet controller inside the FPGA have.
|
||||
*/
|
||||
|
||||
#define DNET_HAS_MDIO (1 << 0)
|
||||
#define DNET_HAS_IRQ (1 << 1)
|
||||
#define DNET_HAS_GIGABIT (1 << 2)
|
||||
#define DNET_HAS_DMA (1 << 3)
|
||||
|
||||
#define DNET_HAS_MII (1 << 4) /* or GMII */
|
||||
#define DNET_HAS_RMII (1 << 5) /* or RGMII */
|
||||
|
||||
#define DNET_CAPS_MASK 0xFFFF
|
||||
|
||||
#define DNET_FIFO_SIZE 2048 /* 2K x 32 bit */
|
||||
#define DNET_FIFO_TX_DATA_AF_TH (DNET_FIFO_SIZE - 384) /* 384 = 1536 / 4 */
|
||||
#define DNET_FIFO_TX_DATA_AE_TH (384)
|
||||
|
||||
#define DNET_FIFO_RX_CMD_AF_TH (1 << 16) /* just one frame inside the FIFO */
|
||||
|
||||
#endif
|
||||
|
|
@ -44,6 +44,7 @@ int cpu_eth_init(bd_t *bis);
|
|||
int au1x00_enet_initialize(bd_t*);
|
||||
int bfin_EMAC_initialize(bd_t *bis);
|
||||
int dc21x4x_initialize(bd_t *bis);
|
||||
int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
|
||||
int e1000_initialize(bd_t *bis);
|
||||
int eepro100_initialize(bd_t *bis);
|
||||
int eth_3com_initialize (bd_t * bis);
|
||||
|
|
|
|||
Loading…
Reference in a new issue