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riscv: implement the invalidate_icache_* functions

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Implement the functions invalidate_icache_range() and
invalidate_icache_all().

RISC-V does not have instructions for explicit cache-control. The
functions in this patch are implemented with the memory ordering
instruction for synchronizing the instruction and data streams. This may
be implemented as a cache flush or invalidate on simple processors,
others may only invalidate the relevant cache lines.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
This commit is contained in:
Lukas Auer 2018-11-22 11:26:23 +01:00 committed by Andes
parent c93a1c8185
commit 62a09ad53b
1 changed files with 10 additions and 0 deletions
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10
arch/riscv/lib/cache.c
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@ -12,6 +12,16 @@ void flush_dcache_range(unsigned long start, unsigned long end)
void invalidate_icache_range(unsigned long start, unsigned long end)
{
/*
* RISC-V does not have an instruction for invalidating parts of the
* instruction cache. Invalidate all of it instead.
*/
invalidate_icache_all();
}
void invalidate_icache_all(void)
{
asm volatile ("fence.i" ::: "memory");
}
void invalidate_dcache_range(unsigned long start, unsigned long end)