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https://github.com/AsahiLinux/u-boot
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AT91: Update otc570 board to new SoC access
* convert otc570 board to use c stucture SoC access * change gpio access to at91_gpio syntax Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
This commit is contained in:
Daniel Gorsulowski
Tom Rix
parent
7cedb29872
commit
6258b04e9a
2 changed files with 105 additions and 96 deletions
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@ -28,13 +28,13 @@
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#include <common.h>
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#include <asm/arch/at91sam9263.h>
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#include <asm/arch/at91sam9_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/at91_matrix.h>
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#include <asm/arch/at91_pio.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/io.h>
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#include <atmel_lcdc.h>
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@ -58,10 +58,10 @@ int get_hw_rev(void)
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if (hw_rev >= 0)
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return hw_rev;
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hw_rev = at91_get_gpio_value(AT91_PIN_PB19);
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hw_rev |= at91_get_gpio_value(AT91_PIN_PB20) << 1;
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hw_rev |= at91_get_gpio_value(AT91_PIN_PB21) << 2;
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hw_rev |= at91_get_gpio_value(AT91_PIN_PB22) << 3;
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hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
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hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
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hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
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hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
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if (hw_rev == 15)
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hw_rev = 0;
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@ -73,40 +73,44 @@ int get_hw_rev(void)
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static void otc570_nand_hw_init(void)
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{
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unsigned long csa;
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at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE;
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at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
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/* Enable CS3 */
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csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
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at91_sys_write(AT91_MATRIX_EBI0CSA,
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csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
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csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
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writel(csa, &matrix->csa[0]);
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/* Configure SMC CS3 for NAND/SmartMedia */
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at91_sys_write(AT91_SMC_SETUP(3),
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AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
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at91_sys_write(AT91_SMC_PULSE(3),
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AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
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AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
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at91_sys_write(AT91_SMC_CYCLE(3),
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AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
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at91_sys_write(AT91_SMC_MODE(3),
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_EXNWMODE_DISABLE |
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AT91_SMC_DBW_8 |
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AT91_SMC_TDF_(2));
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
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&smc->cs[3].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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AT91_SMC_MODE_DBW_8 |
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AT91_SMC_MODE_TDF_CYCLE(2),
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&smc->cs[3].mode);
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/* Configure RDY/BSY */
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at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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/* Enable NandFlash */
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at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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}
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#endif /* CONFIG_CMD_NAND */
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#ifdef CONFIG_MACB
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static void otc570_macb_hw_init(void)
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{
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
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writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
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at91_macb_hw_init();
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}
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#endif
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@ -119,26 +123,27 @@ static void otc570_macb_hw_init(void)
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*/
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static void otc570_ethercat_hw_init(void)
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{
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at91_smc_t *smc1 = (at91_smc_t *) AT91_SMC1_BASE;
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/* Configure SMC EBI1_CS0 for EtherCAT */
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at91_sys_write(AT91_SMC1_SETUP(0),
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AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
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at91_sys_write(AT91_SMC1_PULSE(0),
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AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) |
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AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(9));
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at91_sys_write(AT91_SMC1_CYCLE(0),
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AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(6));
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writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
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&smc1->cs[0].setup);
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writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
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AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
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&smc1->cs[0].pulse);
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writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
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&smc1->cs[0].cycle);
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/*
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* Configure behavior at external wait signal, byte-select mode, 16 bit
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* data bus width, none data float wait states and TDF optimization
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*/
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at91_sys_write(AT91_SMC1_MODE(0),
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AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY |
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AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) |
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AT91_SMC_TDFMODE);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
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AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
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AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
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/* Configure RDY/BSY */
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at91_set_B_periph(AT91_PIN_PE20, 0); /* EBI1_NWAIT */
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at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */
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}
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#ifdef CONFIG_LCD
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@ -164,43 +169,44 @@ vidinfo_t panel_info = {
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void lcd_enable(void)
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{
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at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */
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at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power up */
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}
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void lcd_disable(void)
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{
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at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */
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at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power down */
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}
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static void otc570_lcd_hw_init(void)
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{
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at91_set_A_periph(AT91_PIN_PC0, 0); /* LCDVSYNC */
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at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
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at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
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at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
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at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
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at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
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at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
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at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
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at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
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at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
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at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
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at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
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at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
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at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
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at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
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at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
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at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
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at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
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at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
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at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
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at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
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at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
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at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
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at91_set_gpio_output(AT91_PIN_PA30, 1); /* PCI */
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
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at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
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at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
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at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
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at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
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at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
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at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
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at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
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at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
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at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
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at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
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at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
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at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
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at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
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at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
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at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
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at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
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at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
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at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
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at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
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at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
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at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
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at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
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at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
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at91_set_pio_output(AT91_PIO_PORTA, 30, 1); /* PCI */
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writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer);
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gd->fb_base = CONFIG_OTC570_LCD_BASE;
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}
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@ -242,7 +248,7 @@ int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_MACB
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rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
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rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x00);
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#endif
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return rc;
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}
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@ -290,32 +296,33 @@ u32 get_board_rev(void)
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#ifdef CONFIG_MISC_INIT_R
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int misc_init_r(void)
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{
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char str[64];
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char str[64];
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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at91_set_gpio_output(AT91_PIN_PA29, 1);
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at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
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at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0);
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at91_set_pio_output(AT91_PIO_PORTA, 29, 1);
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at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */
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at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* RXD0 */
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writel(1 << AT91SAM9263_ID_US0, &pmc->pcer);
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/* Set USART_MODE = 1 (RS485) */
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at91_sys_write((0xFFF8C004 - AT91_BASE_SYS), 1);
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writel(1, 0xFFF8C004);
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printf("USART0: ");
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if (getenv_r("usart0", str, sizeof(str)) == -1) {
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printf("No entry - assuming 1-wire\n");
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/* CTS pin, works as mode select pin (0 = 1-wire; 1 = RS485) */
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at91_set_gpio_output(AT91_PIN_PA29, 0);
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at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
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} else {
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if (strcmp(str, "1-wire") == 0) {
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printf("%s\n", str);
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at91_set_gpio_output(AT91_PIN_PA29, 0);
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at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
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} else if (strcmp(str, "rs485") == 0) {
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printf("%s\n", str);
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at91_set_gpio_output(AT91_PIN_PA29, 1);
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at91_set_pio_output(AT91_PIO_PORTA, 29, 1);
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} else {
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printf("Wrong entry - assuming 1-wire ");
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printf("(valid values are '1-wire' or 'rs485')\n");
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at91_set_gpio_output(AT91_PIN_PA29, 0);
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at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
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}
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}
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printf("Display memory address: 0x%08lX\n", gd->fb_base);
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@ -326,14 +333,17 @@ int misc_init_r(void)
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int board_init(void)
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{
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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/* Peripheral Clock Enable Register */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
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1 << AT91SAM9263_ID_PIOB |
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1 << AT91SAM9263_ID_PIOCDE |
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1 << AT91SAM9263_ID_TWI |
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1 << AT91SAM9263_ID_SPI0 |
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1 << AT91SAM9263_ID_LCDC |
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1 << AT91SAM9263_ID_UHP);
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writel( 1 << AT91SAM9263_ID_PIOA |
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1 << AT91SAM9263_ID_PIOB |
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1 << AT91SAM9263_ID_PIOCDE |
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1 << AT91SAM9263_ID_TWI |
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1 << AT91SAM9263_ID_SPI0 |
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1 << AT91SAM9263_ID_LCDC |
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1 << AT91SAM9263_ID_UHP,
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&pmc->pcer);
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/* arch number of OTC570-Board */
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gd->bd->bi_arch_number = MACH_TYPE_OTC570;
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@ -55,6 +55,7 @@
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/*
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* Hardware drivers
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*/
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#define CONFIG_AT91_GPIO 1
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/* Console output */
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#define CONFIG_ATMEL_USART 1
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@ -96,24 +97,22 @@
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#ifdef CONFIG_SOFT_I2C
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#define CONFIG_I2C_CMD_TREE 1
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#define CONFIG_I2C_MULTI_BUS 1
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/* Enable peripheral clock and configure data and clock pins for pio */
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/* Configure data and clock pins for pio */
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#define I2C_INIT { \
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOB | \
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1 << AT91SAM9263_ID_PIOCDE); \
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at91_set_gpio_output(AT91_PIN_PB4, 0); \
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at91_set_gpio_output(AT91_PIN_PB5, 0); \
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at91_set_pio_output(AT91_PIO_PORTB, 4, 0); \
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at91_set_pio_output(AT91_PIO_PORTB, 5, 0); \
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}
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/* Configure data pin as output */
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#define I2C_ACTIVE at91_set_gpio_output(AT91_PIN_PB4, 0)
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#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTB, 4, 0)
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/* Configure data pin as input */
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#define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PB4, 0)
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#define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTB, 4, 0)
|
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/* Read data pin */
|
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#define I2C_READ at91_get_gpio_value(AT91_PIN_PB4)
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#define I2C_READ at91_get_pio_value(AT91_PIO_PORTB, 4)
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/* Set data pin */
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#define I2C_SDA(bit) at91_set_gpio_value(AT91_PIN_PB4, bit)
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#define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTB, 4, bit)
|
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/* Set clock pin */
|
||||
#define I2C_SCL(bit) at91_set_gpio_value(AT91_PIN_PB5, bit)
|
||||
#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
|
||||
#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTB, 5, bit)
|
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#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
|
||||
#endif /* CONFIG_SOFT_I2C */
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
|
|
@ -173,8 +172,8 @@
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
|
||||
/* our CLE is AD22 */
|
||||
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
|
||||
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
|
||||
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
|
||||
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15
|
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#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 22
|
||||
#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
|
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#endif
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||||
|
||||
|
|
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Reference in a new issue