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arm: socfpga: stratix10: Enable SMMU access

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Enable TCU access through the Stratix10 CCU so that the
SMMU can access the SDRAM.

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
This commit is contained in:
Thor Thayer 2019-12-06 13:47:31 -06:00 committed by Marek Vasut
parent cb068cae0d
commit 62079b2211
2 changed files with 21 additions and 0 deletions
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7
arch/arm/mach-socfpga/include/mach/firewall.h
View file

@ -95,6 +95,13 @@ struct socfpga_firwall_l4_sys {
#define CCU_IOM_MPRT_ADMASK_MEM_RAM0 0x18628 #define CCU_IOM_MPRT_ADMASK_MEM_RAM0 0x18628
#define CCU_TCU_MPRT_ADBASE_MEMSPACE0 0x2c520
#define CCU_TCU_MPRT_ADBASE_MEMSPACE1A 0x2c540
#define CCU_TCU_MPRT_ADBASE_MEMSPACE1B 0x2c560
#define CCU_TCU_MPRT_ADBASE_MEMSPACE1C 0x2c580
#define CCU_TCU_MPRT_ADBASE_MEMSPACE1D 0x2c5a0
#define CCU_TCU_MPRT_ADBASE_MEMSPACE1E 0x2c5c0
#define CCU_ADMASK_P_MASK BIT(0) #define CCU_ADMASK_P_MASK BIT(0)
#define CCU_ADMASK_NS_MASK BIT(1) #define CCU_ADMASK_NS_MASK BIT(1)

14
drivers/ddr/altera/sdram_s10.c
View file

@ -105,6 +105,20 @@ int sdram_mmr_init_full(struct udevice *dev)
clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E), clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E),
CCU_ADBASE_DI_MASK); CCU_ADBASE_DI_MASK);
/* Enable access to DDR from TCU */
clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE0),
CCU_ADBASE_DI_MASK);
clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1A),
CCU_ADBASE_DI_MASK);
clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1B),
CCU_ADBASE_DI_MASK);
clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1C),
CCU_ADBASE_DI_MASK);
clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1D),
CCU_ADBASE_DI_MASK);
clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1E),
CCU_ADBASE_DI_MASK);
/* this enables nonsecure access to DDR */ /* this enables nonsecure access to DDR */
/* mpuregion0addr_limit */ /* mpuregion0addr_limit */
FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT); FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);