mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 07:04:28 +00:00
Convert CONFIG_FEC_MXC to Kconfig
This converts the following to Kconfig: CONFIG_FEC_MXC Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
parent
bca1bce92a
commit
61e1972e73
47 changed files with 30 additions and 18 deletions
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@ -80,6 +80,7 @@ CONFIG_SPI_FLASH_SST=y
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_POWER_LEGACY=y
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CONFIG_DM_REGULATOR=y
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@ -93,6 +93,7 @@ CONFIG_SPI_FLASH_MTD=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_DM_ETH=y
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_DM_PMIC=y
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CONFIG_DM_REGULATOR=y
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@ -48,6 +48,7 @@ CONFIG_FSL_USDHC=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_DM_ETH=y
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CONFIG_FEC_MXC=y
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CONFIG_PHY=y
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CONFIG_PHY_IMX8MQ_USB=y
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CONFIG_PINCTRL=y
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@ -52,6 +52,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y
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CONFIG_SUPPORT_EMMC_BOOT=y
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CONFIG_FSL_USDHC=y
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CONFIG_DM_ETH=y
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CONFIG_FEC_MXC=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX8M=y
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CONFIG_SPL_POWER_LEGACY=y
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@ -50,6 +50,7 @@ CONFIG_MTD=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_SMSC=y
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CONFIG_DM_ETH=y
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX6=y
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@ -90,6 +90,7 @@ CONFIG_PHY_MICREL_KSZ8XXX=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_DM_ETH_PHY=y
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CONFIG_FEC_MXC=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX5=y
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CONFIG_DM_REGULATOR=y
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@ -63,6 +63,7 @@ CONFIG_SPI_FLASH_SST=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ90X1=y
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX6=y
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@ -48,6 +48,7 @@ CONFIG_SF_DEFAULT_SPEED=40000000
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX6=y
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@ -50,6 +50,7 @@ CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_PCI=y
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CONFIG_PINCTRL=y
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@ -66,6 +66,7 @@ CONFIG_SPI_FLASH_SST=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ90X1=y
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_MXC_UART=y
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CONFIG_SPI=y
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@ -66,6 +66,7 @@ CONFIG_SPI_FLASH_SST=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ90X1=y
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_MXC_UART=y
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CONFIG_SPI=y
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@ -68,6 +68,7 @@ CONFIG_SPI_FLASH_SST=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ90X1=y
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_MXC_UART=y
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CONFIG_SPI=y
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@ -68,6 +68,7 @@ CONFIG_SPI_FLASH_SST=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ90X1=y
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_MXC_UART=y
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CONFIG_SPI=y
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@ -66,6 +66,7 @@ CONFIG_SPI_FLASH_SST=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ90X1=y
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_MXC_UART=y
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CONFIG_SPI=y
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@ -66,6 +66,7 @@ CONFIG_SPI_FLASH_SST=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ90X1=y
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_MXC_UART=y
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CONFIG_SPI=y
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@ -54,6 +54,7 @@ CONFIG_SYS_I2C_MXC=y
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CONFIG_FSL_USDHC=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_MICREL=y
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX6=y
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@ -57,6 +57,7 @@ CONFIG_FSL_USDHC=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ8XXX=y
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX6=y
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@ -69,6 +69,7 @@ CONFIG_FSL_USDHC=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_DM_ETH=y
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CONFIG_FEC_MXC=y
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CONFIG_RGMII=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX6=y
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@ -61,6 +61,7 @@ CONFIG_PHYLIB=y
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ8XXX=y
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CONFIG_DM_ETH=y
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX6=y
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@ -50,6 +50,7 @@ CONFIG_SPL_SYS_I2C_LEGACY=y
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CONFIG_SUPPORT_EMMC_BOOT=y
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CONFIG_FSL_USDHC=y
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CONFIG_DM_ETH=y
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CONFIG_FEC_MXC=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX8M=y
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CONFIG_SPL_POWER_LEGACY=y
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@ -57,6 +57,7 @@ CONFIG_FSL_USDHC=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ8XXX=y
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX6=y
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@ -42,6 +42,7 @@ CONFIG_FSL_USDHC=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ8XXX=y
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX6=y
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@ -44,6 +44,7 @@ CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_WINBOND=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX6=y
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@ -48,6 +48,7 @@ CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_WINBOND=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX6=y
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@ -44,6 +44,7 @@ CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_WINBOND=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX6=y
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@ -48,6 +48,7 @@ CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_WINBOND=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX6=y
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@ -44,6 +44,7 @@ CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_WINBOND=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX6=y
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@ -48,6 +48,7 @@ CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_WINBOND=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX6=y
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@ -51,6 +51,7 @@ CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ8XXX=y
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_DM_SERIAL=y
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CONFIG_FSL_LPUART=y
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@ -51,6 +51,7 @@ CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ8XXX=y
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_DM_SERIAL=y
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CONFIG_FSL_LPUART=y
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@ -13,7 +13,6 @@
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#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
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/* Network */
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#define CONFIG_FEC_MXC
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC_PHYADDR 0
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@ -147,7 +147,6 @@
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#endif
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/* Ethernet */
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#define CONFIG_FEC_MXC
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#define CONFIG_FEC_MXC_PHYADDR 0
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define IMX_FEC_BASE ENET_BASE_ADDR
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@ -91,7 +91,6 @@
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/*
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* Ethernet
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*/
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#define CONFIG_FEC_MXC
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#define CONFIG_FEC_MXC_PHYADDR 0x1f
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/*
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@ -54,7 +54,6 @@
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#define CONFIG_MII
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_FEC_MXC_PHYADDR 0
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#define FEC_QUIRK_ENET_MAC
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@ -48,7 +48,6 @@
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#define CONFIG_MII
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_FEC_MXC_PHYADDR 0
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#define FEC_QUIRK_ENET_MAC
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@ -126,7 +126,6 @@
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#endif
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#ifdef CONFIG_CMD_NET
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#define CONFIG_FEC_MXC
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#define CONFIG_FEC_ENET_DEV 0
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#define IMX_FEC_BASE ENET_BASE_ADDR
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@ -73,7 +73,6 @@
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* Ethernet on SOC (FEC)
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*/
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#ifdef CONFIG_CMD_NET
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#define CONFIG_FEC_MXC
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#define IMX_FEC_BASE FEC_BASE_ADDR
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#define CONFIG_FEC_MXC_PHYADDR 0x0
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#define CONFIG_MII
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@ -111,8 +111,6 @@
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/* Network */
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#define CONFIG_FEC_MXC
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#define IMX_FEC_BASE ENET2_BASE_ADDR
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#define CONFIG_FEC_MXC_PHYADDR 0x0
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#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
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/* Network */
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#define CONFIG_FEC_MXC
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#define IMX_FEC_BASE ENET_BASE_ADDR
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#define CONFIG_FEC_MXC_PHYADDR 0x1
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@ -32,7 +32,6 @@
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#define CONFIG_LBA48
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#endif
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#define CONFIG_FEC_MXC
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#define IMX_FEC_BASE ENET_BASE_ADDR
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_ETHPRIME "FEC"
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@ -130,7 +130,6 @@
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#define CONFIG_BOARD_SIZE_LIMIT 715776
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/* Ethernet Configuration */
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#define CONFIG_FEC_MXC
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#define CONFIG_MII
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#define IMX_FEC_BASE ENET_BASE_ADDR
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#define CONFIG_FEC_XCV_TYPE RGMII
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@ -28,7 +28,6 @@
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/* Network support */
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#define CONFIG_FEC_MXC
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#define IMX_FEC_BASE ENET2_BASE_ADDR
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#define CONFIG_FEC_MXC_PHYADDR 0x1
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#define CONFIG_FEC_XCV_TYPE RMII
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#define CONFIG_MII
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_FEC_MXC_PHYADDR 1
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#define FEC_QUIRK_ENET_MAC
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#endif
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#ifdef CONFIG_CMD_NET
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#define CONFIG_FEC_MXC
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#define IMX_FEC_BASE ENET_BASE_ADDR
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#define CONFIG_FEC_MXC_PHYADDR 0x1
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#define CONFIG_FEC_XCV_TYPE RMII
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
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#define CONFIG_FEC_MXC
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#define IMX_FEC_BASE ENET_BASE_ADDR
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#define CONFIG_ARP_TIMEOUT 200UL
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define CONFIG_SYS_FSL_ESDHC_NUM 1
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#define CONFIG_FEC_MXC
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#define IMX_FEC_BASE ENET_BASE_ADDR
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#define CONFIG_FEC_XCV_TYPE RMII
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#define CONFIG_FEC_MXC_PHYADDR 0
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#define CONFIG_MXC_USB_FLAGS 0
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#define CONFIG_FEC_MXC
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#define CONFIG_FEC_ENET_DEV 0
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#define IMX_FEC_BASE ENET_BASE_ADDR
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#define CONFIG_FEC_MXC_PHYADDR 0x0
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