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https://github.com/AsahiLinux/u-boot
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keystone2: clock: add K2L clock definitions and commands
This patch adds clock definitions and commands to support Keystone II K2L SOC. Acked-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
This commit is contained in:
Hao Zhang
Tom Rini
parent
c4995a8282
commit
61d122583f
4 changed files with 232 additions and 0 deletions
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@ -10,6 +10,7 @@ obj-y += psc.o
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obj-y += clock.o
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obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
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obj-$(CONFIG_SOC_K2E) += clock-k2e.o
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obj-$(CONFIG_SOC_K2L) += clock-k2l.o
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obj-y += cmd_clock.o
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obj-y += cmd_mon.o
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obj-y += msmc.o
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138
arch/arm/cpu/armv7/keystone/clock-k2l.c
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138
arch/arm/cpu/armv7/keystone/clock-k2l.c
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@ -0,0 +1,138 @@
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/*
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* Keystone2: get clk rate for K2L
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/clock_defs.h>
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const struct keystone_pll_regs keystone_pll_regs[] = {
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[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
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[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
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[TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
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[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
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};
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int dev_speeds[] = {
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SPD800,
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SPD1000,
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SPD1200,
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SPD800,
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SPD800,
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SPD800,
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SPD800,
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SPD800,
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SPD1200,
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SPD1000,
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SPD800,
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SPD800,
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SPD800,
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};
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int arm_speeds[] = {
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SPD800,
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SPD1000,
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SPD1200,
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SPD1350,
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SPD1400,
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SPD800,
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SPD1400,
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SPD1350,
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SPD1200,
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SPD1000,
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SPD800,
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SPD800,
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SPD800,
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};
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/**
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* pll_freq_get - get pll frequency
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* Fout = Fref * NF(mult) / NR(prediv) / OD
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* @pll: pll identifier
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*/
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static unsigned long pll_freq_get(int pll)
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{
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unsigned long mult = 1, prediv = 1, output_div = 2;
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unsigned long ret;
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u32 tmp, reg;
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if (pll == CORE_PLL) {
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ret = external_clk[sys_clk];
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if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
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/* PLL mode */
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tmp = __raw_readl(KS2_MAINPLLCTL0);
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prediv = (tmp & PLL_DIV_MASK) + 1;
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mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
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(pllctl_reg_read(pll, mult) &
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PLLM_MULT_LO_MASK)) + 1;
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output_div = ((pllctl_reg_read(pll, secctl) >>
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PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
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ret = ret / prediv / output_div * mult;
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}
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} else {
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switch (pll) {
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case PASS_PLL:
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ret = external_clk[pa_clk];
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reg = KS2_PASSPLLCTL0;
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break;
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case TETRIS_PLL:
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ret = external_clk[tetris_clk];
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reg = KS2_ARMPLLCTL0;
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break;
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case DDR3_PLL:
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ret = external_clk[ddr3_clk];
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reg = KS2_DDR3APLLCTL0;
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break;
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default:
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return 0;
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}
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tmp = __raw_readl(reg);
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if (!(tmp & PLLCTL_BYPASS)) {
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/* Bypass disabled */
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prediv = (tmp & PLL_DIV_MASK) + 1;
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mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
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output_div = ((tmp >> PLL_CLKOD_SHIFT) &
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PLL_CLKOD_MASK) + 1;
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ret = ((ret / prediv) * mult) / output_div;
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}
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}
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return ret;
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}
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unsigned long clk_get_rate(unsigned int clk)
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{
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switch (clk) {
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case core_pll_clk: return pll_freq_get(CORE_PLL);
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case pass_pll_clk: return pll_freq_get(PASS_PLL);
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case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
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case ddr3_pll_clk: return pll_freq_get(DDR3_PLL);
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case sys_clk0_1_clk:
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case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
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case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
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case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
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case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
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case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
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case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
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case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
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case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
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case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
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case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
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case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
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case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
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case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
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case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
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case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
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default:
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break;
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}
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return 0;
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}
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89
arch/arm/include/asm/arch-keystone/clock-k2l.h
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89
arch/arm/include/asm/arch-keystone/clock-k2l.h
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@ -0,0 +1,89 @@
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/*
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* K2L: Clock management APIs
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_CLOCK_K2L_H
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#define __ASM_ARCH_CLOCK_K2L_H
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enum ext_clk_e {
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sys_clk,
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alt_core_clk,
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pa_clk,
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tetris_clk,
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ddr3_clk,
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pcie_clk,
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sgmii_clk,
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usb_clk,
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rp1_clk,
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ext_clk_count /* number of external clocks */
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};
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extern unsigned int external_clk[ext_clk_count];
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#define CLK_LIST(CLK)\
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CLK(0, core_pll_clk)\
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CLK(1, pass_pll_clk)\
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CLK(2, tetris_pll_clk)\
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CLK(3, ddr3_pll_clk)\
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CLK(4, sys_clk0_clk)\
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CLK(5, sys_clk0_1_clk)\
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CLK(6, sys_clk0_2_clk)\
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CLK(7, sys_clk0_3_clk)\
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CLK(8, sys_clk0_4_clk)\
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CLK(9, sys_clk0_6_clk)\
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CLK(10, sys_clk0_8_clk)\
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CLK(11, sys_clk0_12_clk)\
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CLK(12, sys_clk0_24_clk)\
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CLK(13, sys_clk1_clk)\
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CLK(14, sys_clk1_3_clk)\
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CLK(15, sys_clk1_4_clk)\
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CLK(16, sys_clk1_6_clk)\
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CLK(17, sys_clk1_12_clk)\
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CLK(18, sys_clk2_clk)\
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CLK(19, sys_clk3_clk)\
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#define PLLSET_CMD_LIST "<pa|arm|ddr3>"
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#define KS2_CLK1_6 sys_clk0_6_clk
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/* PLL identifiers */
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enum pll_type_e {
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CORE_PLL,
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PASS_PLL,
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TETRIS_PLL,
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DDR3_PLL,
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};
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enum {
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SPD800,
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SPD1000,
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SPD1200,
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SPD1350,
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SPD1400,
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SPD_RSV
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};
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#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
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#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
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#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2}
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#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2}
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#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2}
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#define PASS_PLL_983 {PASS_PLL, 16, 1, 2}
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#define PASS_PLL_1050 {PASS_PLL, 205, 12, 2}
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#define TETRIS_PLL_491 {TETRIS_PLL, 8, 1, 2}
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#define TETRIS_PLL_737 {TETRIS_PLL, 12, 1, 2}
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#define TETRIS_PLL_799 {TETRIS_PLL, 13, 1, 2}
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#define TETRIS_PLL_983 {TETRIS_PLL, 16, 1, 2}
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#define TETRIS_PLL_1167 {TETRIS_PLL, 19, 1, 2}
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#define TETRIS_PLL_1228 {TETRIS_PLL, 20, 1, 2}
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#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2}
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#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4}
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#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
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#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6}
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#endif
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@ -20,6 +20,10 @@
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#include <asm/arch/clock-k2e.h>
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#endif
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#ifdef CONFIG_SOC_K2L
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#include <asm/arch/clock-k2l.h>
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#endif
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#define MAIN_PLL CORE_PLL
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#include <asm/types.h>
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