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Tom Rini 2021-07-05 11:20:30 -04:00
commit 6194b45a83
481 changed files with 30825 additions and 4213 deletions
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4
MAINTAINERS
View file

@ -1020,8 +1020,8 @@ M: Sean Anderson <seanga2@gmail.com>
S: Maintained
F: doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt
F: doc/device-tree-bindings/pinctrl/kendryte,k210-fpioa.txt
F: drivers/clk/kendryte/
F: drivers/pinctrl/kendryte/
F: drivers/clk/clk_kendryte.c
F: drivers/pinctrl/pinctrl-kendryte.c
F: include/kendryte/
RNG

6
arch/arm/dts/Makefile
View file

@ -146,6 +146,9 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-rockpro64.dtb \
rk3399pro-rock-pi-n10.dtb
dtb-$(CONFIG_ROCKCHIP_RK3568) += \
rk3568-evb.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
rv1108-elgin-r1.dtb \
rv1108-evb.dtb
@ -904,7 +907,8 @@ dtb-$(CONFIG_RCAR_GEN3) += \
r8a77970-eagle-u-boot.dtb \
r8a77980-condor-u-boot.dtb \
r8a77990-ebisu-u-boot.dtb \
r8a77995-draak-u-boot.dtb
r8a77995-draak-u-boot.dtb \
r8a779a0-falcon-u-boot.dtb
ifdef CONFIG_RCAR_GEN3
DTC_FLAGS += -R 4 -p 0x1000

5
arch/arm/dts/am335x-bone-common.dtsi
View file

@ -398,3 +398,8 @@
&sham {
status = "okay";
};
&rtc {
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};

5
arch/arm/dts/am335x-evm.dts
View file

@ -762,3 +762,8 @@
pinctrl-names = "default";
pinctrl-0 = <&dcan1_pins_default>;
};
&rtc {
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};

5
arch/arm/dts/am335x-evmsk.dts
View file

@ -724,3 +724,8 @@
&lcdc {
status = "okay";
};
&rtc {
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};

6
arch/arm/dts/am335x-osd335x-common.dtsi
View file

@ -122,3 +122,9 @@
&sham {
status = "okay";
};
&rtc {
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
system-power-controller;
};

2
arch/arm/dts/avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dts
View file

@ -15,10 +15,10 @@
"xlnx,zynqmp";
chosen {
stdout-path = "serial0:115200n8";
xlnx,eeprom = &eeprom;
};
aliases {
ethernet0 = &gem3;
nvmem0 = &eeprom;
serial0 = &uart0;
};
};

32
arch/arm/dts/k3-am64-main.dtsi
View file

@ -14,7 +14,7 @@
ranges = <0x0 0x00 0x70000000 0x200000>;
atf-sram@0 {
reg = <0x0 0x1a000>;
reg = <0x1a0000 0x1c000>;
};
};
@ -499,6 +499,36 @@
clock-names = "gpio";
};
usbss0: cdns-usb@f900000{
compatible = "ti,am64-usb", "ti,j721e-usb";
reg = <0x00 0xf900000 0x00 0x100>;
power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 161 9>, <&k3_clks 161 1>;
clock-names = "ref", "lpm";
assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */
assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */
#address-cells = <2>;
#size-cells = <2>;
ranges;
usb0: usb@f400000{
compatible = "cdns,usb3";
reg = <0x00 0xf400000 0x00 0x10000>,
<0x00 0xf410000 0x00 0x10000>,
<0x00 0xf420000 0x00 0x10000>;
reg-names = "otg",
"xhci",
"dev";
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
interrupt-names = "host",
"peripheral",
"otg";
maximum-speed = "super-speed";
dr_mode = "otg";
};
};
main_gpio1: gpio@601000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00601000 0x00 0x100>;

13
arch/arm/dts/k3-am642-evm-u-boot.dtsi
View file

@ -50,6 +50,19 @@
u-boot,dm-spl;
};
&usb0 {
dr_mode="peripheral";
u-boot,dm-spl;
};
&usbss0 {
u-boot,dm-spl;
};
&main_usb0_pins_default {
u-boot,dm-spl;
};
&dmss {
u-boot,dm-spl;
};

18
arch/arm/dts/k3-am642-evm.dts
View file

@ -201,6 +201,12 @@
AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
>;
};
main_usb0_pins_default: main-usb0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
};
&main_uart0 {
@ -337,3 +343,15 @@
ti,driver-strength-ohm = <50>;
disable-wp;
};
&usbss0 {
ti,vbus-divider;
ti,usb2-only;
};
&usb0 {
dr_mode = "otg";
maximum-speed = "high-speed";
pinctrl-names = "default";
pinctrl-0 = <&main_usb0_pins_default>;
};

18
arch/arm/dts/k3-am642-r5-evm.dts
View file

@ -141,6 +141,12 @@
AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */
>;
};
main_usb0_pins_default: main-usb0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
};
&dmsc {
@ -201,4 +207,16 @@
/delete-property/ power-domains;
};
&usbss0 {
ti,vbus-divider;
ti,usb2-only;
};
&usb0 {
dr_mode = "otg";
maximum-speed = "high-speed";
pinctrl-names = "default";
pinctrl-0 = <&main_usb0_pins_default>;
};
#include "k3-am642-evm-u-boot.dtsi"

14
arch/arm/dts/k3-am654-base-board-u-boot.dtsi
View file

@ -35,11 +35,25 @@
u-boot,dm-spl;
ringacc@2b800000 {
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
<0x0 0x28590000 0x0 0x100>,
<0x0 0x2a500000 0x0 0x40000>,
<0x0 0x28440000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
u-boot,dm-spl;
ti,dma-ring-reset-quirk;
};
dma-controller@285c0000 {
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x284c0000 0x0 0x4000>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x284a0000 0x0 0x4000>,
<0x0 0x2aa00000 0x0 0x40000>,
<0x0 0x28400000 0x0 0x2000>;
reg-names = "gcfg", "rchan", "rchanrt", "tchan",
"tchanrt", "rflow";
u-boot,dm-spl;
};
};

30
arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
View file

@ -33,13 +33,41 @@
compatible = "ti,omap5430-timer";
reg = <0x0 0x40400000 0x0 0x80>;
ti,timer-alwon;
clock-frequency = <25000000>;
clock-frequency = <250000000>;
u-boot,dm-spl;
};
chipid@43000014 {
u-boot,dm-spl;
};
mcu-navss{
u-boot,dm-spl;
#address-cells = <2>;
#size-cells = <2>;
ringacc@2b800000 {
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
<0x0 0x28590000 0x0 0x100>,
<0x0 0x2a500000 0x0 0x40000>,
<0x0 0x28440000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
u-boot,dm-spl;
};
dma-controller@285c0000 {
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x284c0000 0x0 0x4000>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x284a0000 0x0 0x4000>,
<0x0 0x2aa00000 0x0 0x40000>,
<0x0 0x28400000 0x0 0x2000>;
reg-names = "gcfg", "rchan", "rchanrt", "tchan",
"tchanrt", "rflow";
u-boot,dm-spl;
};
};
};
&secure_proxy_main {

437
arch/arm/dts/k3-j7200-ddr-evm-lp4-1600.dtsi → arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi
View file

@ -1,13 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* This file was generated by the AM752x_DRA82x_TDA4x_DDRSS_RegConfigTool, Revision: 0.3.0
* This file was generated on 06/08/2020
* Includes hand edits
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.5.0
* This file was generated on 08/07/2020
* Includes hand-edits
*/
#define DDRSS_PLL_FHS_CNT 10
#define DDRSS_PLL_FREQUENCY_1 400000000
#define DDRSS_PLL_FREQUENCY_2 400000000
#define DDRSS_PLL_FREQUENCY_1 666500000
#define DDRSS_PLL_FREQUENCY_2 666500000
#define DDRSS_CTL_00_DATA 0x00000B00
#define DDRSS_CTL_01_DATA 0x00000000
@ -20,14 +21,14 @@
#define DDRSS_CTL_08_DATA 0x000186A0
#define DDRSS_CTL_09_DATA 0x00000005
#define DDRSS_CTL_10_DATA 0x00000064
#define DDRSS_CTL_11_DATA 0x00027100
#define DDRSS_CTL_12_DATA 0x00186A00
#define DDRSS_CTL_11_DATA 0x000411AB
#define DDRSS_CTL_12_DATA 0x0028B0AB
#define DDRSS_CTL_13_DATA 0x00000005
#define DDRSS_CTL_14_DATA 0x00000640
#define DDRSS_CTL_15_DATA 0x00027100
#define DDRSS_CTL_16_DATA 0x00186A00
#define DDRSS_CTL_14_DATA 0x00000A6B
#define DDRSS_CTL_15_DATA 0x000411AB
#define DDRSS_CTL_16_DATA 0x0028B0AB
#define DDRSS_CTL_17_DATA 0x00000005
#define DDRSS_CTL_18_DATA 0x00000640
#define DDRSS_CTL_18_DATA 0x00000A6B
#define DDRSS_CTL_19_DATA 0x01010000
#define DDRSS_CTL_20_DATA 0x02011001
#define DDRSS_CTL_21_DATA 0x02010000
@ -37,66 +38,66 @@
#define DDRSS_CTL_25_DATA 0x00000000
#define DDRSS_CTL_26_DATA 0x00000000
#define DDRSS_CTL_27_DATA 0x02020200
#define DDRSS_CTL_28_DATA 0x00002020
#define DDRSS_CTL_28_DATA 0x00003636
#define DDRSS_CTL_29_DATA 0x00100000
#define DDRSS_CTL_30_DATA 0x00000000
#define DDRSS_CTL_31_DATA 0x00000000
#define DDRSS_CTL_32_DATA 0x00000000
#define DDRSS_CTL_33_DATA 0x00000000
#define DDRSS_CTL_34_DATA 0x040C0000
#define DDRSS_CTL_35_DATA 0x081C081C
#define DDRSS_CTL_35_DATA 0x0C300C30
#define DDRSS_CTL_36_DATA 0x00050804
#define DDRSS_CTL_37_DATA 0x09040008
#define DDRSS_CTL_38_DATA 0x08000204
#define DDRSS_CTL_39_DATA 0x0B240034
#define DDRSS_CTL_40_DATA 0x08001910
#define DDRSS_CTL_41_DATA 0x0B240034
#define DDRSS_CTL_42_DATA 0x20001910
#define DDRSS_CTL_38_DATA 0x0D000204
#define DDRSS_CTL_39_DATA 0x113C0057
#define DDRSS_CTL_40_DATA 0x0D00291B
#define DDRSS_CTL_41_DATA 0x113C0057
#define DDRSS_CTL_42_DATA 0x2000291B
#define DDRSS_CTL_43_DATA 0x000A0A09
#define DDRSS_CTL_44_DATA 0x040006DB
#define DDRSS_CTL_45_DATA 0x0C0A0904
#define DDRSS_CTL_46_DATA 0x06006DB0
#define DDRSS_CTL_47_DATA 0x0C0A0906
#define DDRSS_CTL_48_DATA 0x06006DB0
#define DDRSS_CTL_49_DATA 0x02030406
#define DDRSS_CTL_50_DATA 0x11040500
#define DDRSS_CTL_51_DATA 0x08121112
#define DDRSS_CTL_45_DATA 0x130E0B04
#define DDRSS_CTL_46_DATA 0x0A00B6D0
#define DDRSS_CTL_47_DATA 0x130E0B0A
#define DDRSS_CTL_48_DATA 0x0A00B6D0
#define DDRSS_CTL_49_DATA 0x0203040A
#define DDRSS_CTL_50_DATA 0x1C040500
#define DDRSS_CTL_51_DATA 0x081D1C1D
#define DDRSS_CTL_52_DATA 0x14000D0A
#define DDRSS_CTL_53_DATA 0x02010A0A
#define DDRSS_CTL_54_DATA 0x01010002
#define DDRSS_CTL_55_DATA 0x04222208
#define DDRSS_CTL_56_DATA 0x04131304
#define DDRSS_CTL_57_DATA 0x00001313
#define DDRSS_CTL_55_DATA 0x04383808
#define DDRSS_CTL_56_DATA 0x041F1F04
#define DDRSS_CTL_57_DATA 0x00001F1F
#define DDRSS_CTL_58_DATA 0x00010100
#define DDRSS_CTL_59_DATA 0x03010000
#define DDRSS_CTL_60_DATA 0x00000E08
#define DDRSS_CTL_61_DATA 0x000000BB
#define DDRSS_CTL_62_DATA 0x000000E0
#define DDRSS_CTL_63_DATA 0x00000C28
#define DDRSS_CTL_64_DATA 0x000000E0
#define DDRSS_CTL_65_DATA 0x00000C28
#define DDRSS_CTL_62_DATA 0x00000176
#define DDRSS_CTL_63_DATA 0x00001448
#define DDRSS_CTL_64_DATA 0x00000176
#define DDRSS_CTL_65_DATA 0x00001448
#define DDRSS_CTL_66_DATA 0x00000005
#define DDRSS_CTL_67_DATA 0x00030000
#define DDRSS_CTL_68_DATA 0x00380010
#define DDRSS_CTL_69_DATA 0x0038017E
#define DDRSS_CTL_70_DATA 0x0040017E
#define DDRSS_CTL_68_DATA 0x005D0010
#define DDRSS_CTL_69_DATA 0x005D0282
#define DDRSS_CTL_70_DATA 0x00400282
#define DDRSS_CTL_71_DATA 0x00120103
#define DDRSS_CTL_72_DATA 0x00060005
#define DDRSS_CTL_73_DATA 0x14080006
#define DDRSS_CTL_74_DATA 0x05050114
#define DDRSS_CTL_75_DATA 0x0201030A
#define DDRSS_CTL_76_DATA 0x030C0605
#define DDRSS_CTL_77_DATA 0x06050201
#define DDRSS_CTL_78_DATA 0x0001030C
#define DDRSS_CTL_72_DATA 0x000A0005
#define DDRSS_CTL_73_DATA 0x1F08000A
#define DDRSS_CTL_74_DATA 0x0505011F
#define DDRSS_CTL_75_DATA 0x0301030A
#define DDRSS_CTL_76_DATA 0x03130A07
#define DDRSS_CTL_77_DATA 0x0A070301
#define DDRSS_CTL_78_DATA 0x00010313
#define DDRSS_CTL_79_DATA 0x000F000F
#define DDRSS_CTL_80_DATA 0x00E600E6
#define DDRSS_CTL_81_DATA 0x00E600E6
#define DDRSS_CTL_80_DATA 0x01800180
#define DDRSS_CTL_81_DATA 0x01800180
#define DDRSS_CTL_82_DATA 0x03050505
#define DDRSS_CTL_83_DATA 0x03010303
#define DDRSS_CTL_84_DATA 0x0C050605
#define DDRSS_CTL_85_DATA 0x03020603
#define DDRSS_CTL_86_DATA 0x0C050605
#define DDRSS_CTL_87_DATA 0x03020603
#define DDRSS_CTL_84_DATA 0x14070A07
#define DDRSS_CTL_85_DATA 0x03030A03
#define DDRSS_CTL_86_DATA 0x14070A07
#define DDRSS_CTL_87_DATA 0x03030A03
#define DDRSS_CTL_88_DATA 0x03010000
#define DDRSS_CTL_89_DATA 0x00010000
#define DDRSS_CTL_90_DATA 0x00000000
@ -118,20 +119,20 @@
#define DDRSS_CTL_106_DATA 0x00002EC0
#define DDRSS_CTL_107_DATA 0x00000000
#define DDRSS_CTL_108_DATA 0x0000051D
#define DDRSS_CTL_109_DATA 0x00030A00
#define DDRSS_CTL_110_DATA 0x00030A00
#define DDRSS_CTL_111_DATA 0x00030A00
#define DDRSS_CTL_112_DATA 0x00030A00
#define DDRSS_CTL_113_DATA 0x00030A00
#define DDRSS_CTL_109_DATA 0x00051200
#define DDRSS_CTL_110_DATA 0x00051200
#define DDRSS_CTL_111_DATA 0x00051200
#define DDRSS_CTL_112_DATA 0x00051200
#define DDRSS_CTL_113_DATA 0x00051200
#define DDRSS_CTL_114_DATA 0x00000000
#define DDRSS_CTL_115_DATA 0x00005518
#define DDRSS_CTL_116_DATA 0x00030A00
#define DDRSS_CTL_117_DATA 0x00030A00
#define DDRSS_CTL_118_DATA 0x00030A00
#define DDRSS_CTL_119_DATA 0x00030A00
#define DDRSS_CTL_120_DATA 0x00030A00
#define DDRSS_CTL_115_DATA 0x00008DF8
#define DDRSS_CTL_116_DATA 0x00051200
#define DDRSS_CTL_117_DATA 0x00051200
#define DDRSS_CTL_118_DATA 0x00051200
#define DDRSS_CTL_119_DATA 0x00051200
#define DDRSS_CTL_120_DATA 0x00051200
#define DDRSS_CTL_121_DATA 0x00000000
#define DDRSS_CTL_122_DATA 0x00005518
#define DDRSS_CTL_122_DATA 0x00008DF8
#define DDRSS_CTL_123_DATA 0x00000000
#define DDRSS_CTL_124_DATA 0x00000000
#define DDRSS_CTL_125_DATA 0x00000000
@ -140,8 +141,8 @@
#define DDRSS_CTL_128_DATA 0x00000000
#define DDRSS_CTL_129_DATA 0x00000000
#define DDRSS_CTL_130_DATA 0x00000000
#define DDRSS_CTL_131_DATA 0x05030500
#define DDRSS_CTL_132_DATA 0x00030503
#define DDRSS_CTL_131_DATA 0x07030500
#define DDRSS_CTL_132_DATA 0x00030703
#define DDRSS_CTL_133_DATA 0x0A090000
#define DDRSS_CTL_134_DATA 0x0A090701
#define DDRSS_CTL_135_DATA 0x0900000E
@ -176,23 +177,23 @@
#define DDRSS_CTL_164_DATA 0x000A0000
#define DDRSS_CTL_165_DATA 0x000D0005
#define DDRSS_CTL_166_DATA 0x000D0404
#define DDRSS_CTL_167_DATA 0x005000A0
#define DDRSS_CTL_168_DATA 0x060600C8
#define DDRSS_CTL_169_DATA 0x00A000C8
#define DDRSS_CTL_170_DATA 0x00C80050
#define DDRSS_CTL_171_DATA 0x00C80606
#define DDRSS_CTL_167_DATA 0x0086010B
#define DDRSS_CTL_168_DATA 0x0A0A014E
#define DDRSS_CTL_169_DATA 0x010B014E
#define DDRSS_CTL_170_DATA 0x014E0086
#define DDRSS_CTL_171_DATA 0x014E0A0A
#define DDRSS_CTL_172_DATA 0x00000000
#define DDRSS_CTL_173_DATA 0x00000000
#define DDRSS_CTL_174_DATA 0x00000000
#define DDRSS_CTL_175_DATA 0x12A40084
#define DDRSS_CTL_176_DATA 0x2B0012A4
#define DDRSS_CTL_175_DATA 0x24C40084
#define DDRSS_CTL_176_DATA 0x2B0024C4
#define DDRSS_CTL_177_DATA 0x00002B2B
#define DDRSS_CTL_178_DATA 0x36000000
#define DDRSS_CTL_179_DATA 0x27270036
#define DDRSS_CTL_180_DATA 0x0F0F0000
#define DDRSS_CTL_181_DATA 0x00000000
#define DDRSS_CTL_182_DATA 0x00841515
#define DDRSS_CTL_183_DATA 0x12A412A4
#define DDRSS_CTL_183_DATA 0x24C424C4
#define DDRSS_CTL_184_DATA 0x2B2B2B00
#define DDRSS_CTL_185_DATA 0x00000000
#define DDRSS_CTL_186_DATA 0x00363600
@ -270,12 +271,12 @@
#define DDRSS_CTL_258_DATA 0x00320040
#define DDRSS_CTL_259_DATA 0x00020008
#define DDRSS_CTL_260_DATA 0x00400100
#define DDRSS_CTL_261_DATA 0x00180320
#define DDRSS_CTL_261_DATA 0x00280536
#define DDRSS_CTL_262_DATA 0x01000200
#define DDRSS_CTL_263_DATA 0x03200040
#define DDRSS_CTL_264_DATA 0x00000018
#define DDRSS_CTL_265_DATA 0x00280003
#define DDRSS_CTL_266_DATA 0x01000028
#define DDRSS_CTL_263_DATA 0x05360040
#define DDRSS_CTL_264_DATA 0x00000028
#define DDRSS_CTL_265_DATA 0x00430003
#define DDRSS_CTL_266_DATA 0x01000043
#define DDRSS_CTL_267_DATA 0x00000000
#define DDRSS_CTL_268_DATA 0x01010000
#define DDRSS_CTL_269_DATA 0x00000202
@ -327,14 +328,14 @@
#define DDRSS_CTL_315_DATA 0x01000101
#define DDRSS_CTL_316_DATA 0x01010001
#define DDRSS_CTL_317_DATA 0x00010101
#define DDRSS_CTL_318_DATA 0x05050503
#define DDRSS_CTL_319_DATA 0x08080C0C
#define DDRSS_CTL_320_DATA 0x00090308
#define DDRSS_CTL_321_DATA 0x000C030F
#define DDRSS_CTL_322_DATA 0x000C0311
#define DDRSS_CTL_323_DATA 0x0C090011
#define DDRSS_CTL_318_DATA 0x05070703
#define DDRSS_CTL_319_DATA 0x0A081414
#define DDRSS_CTL_320_DATA 0x0009030A
#define DDRSS_CTL_321_DATA 0x080C030F
#define DDRSS_CTL_322_DATA 0x080C0306
#define DDRSS_CTL_323_DATA 0x0C090006
#define DDRSS_CTL_324_DATA 0x0100000C
#define DDRSS_CTL_325_DATA 0x03020301
#define DDRSS_CTL_325_DATA 0x05020501
#define DDRSS_CTL_326_DATA 0x00000002
#define DDRSS_CTL_327_DATA 0x00000000
#define DDRSS_CTL_328_DATA 0x00010000
@ -396,7 +397,7 @@
#define DDRSS_CTL_384_DATA 0x00000000
#define DDRSS_CTL_385_DATA 0x00000000
#define DDRSS_CTL_386_DATA 0x00000000
#define DDRSS_CTL_387_DATA 0x26261B00
#define DDRSS_CTL_387_DATA 0x2E2E1B00
#define DDRSS_CTL_388_DATA 0x000A0000
#define DDRSS_CTL_389_DATA 0x00000176
#define DDRSS_CTL_390_DATA 0x00000200
@ -406,22 +407,22 @@
#define DDRSS_CTL_394_DATA 0x00000462
#define DDRSS_CTL_395_DATA 0x00000E9C
#define DDRSS_CTL_396_DATA 0x00000204
#define DDRSS_CTL_397_DATA 0x00001850
#define DDRSS_CTL_397_DATA 0x00002890
#define DDRSS_CTL_398_DATA 0x00000200
#define DDRSS_CTL_399_DATA 0x00000200
#define DDRSS_CTL_400_DATA 0x00000200
#define DDRSS_CTL_401_DATA 0x00000200
#define DDRSS_CTL_402_DATA 0x000048F0
#define DDRSS_CTL_403_DATA 0x0000F320
#define DDRSS_CTL_404_DATA 0x00000408
#define DDRSS_CTL_405_DATA 0x00001850
#define DDRSS_CTL_402_DATA 0x000079B0
#define DDRSS_CTL_403_DATA 0x000195A0
#define DDRSS_CTL_404_DATA 0x0000080E
#define DDRSS_CTL_405_DATA 0x00002890
#define DDRSS_CTL_406_DATA 0x00000200
#define DDRSS_CTL_407_DATA 0x00000200
#define DDRSS_CTL_408_DATA 0x00000200
#define DDRSS_CTL_409_DATA 0x00000200
#define DDRSS_CTL_410_DATA 0x000048F0
#define DDRSS_CTL_411_DATA 0x0000F320
#define DDRSS_CTL_412_DATA 0x02020408
#define DDRSS_CTL_410_DATA 0x000079B0
#define DDRSS_CTL_411_DATA 0x000195A0
#define DDRSS_CTL_412_DATA 0x0202080E
#define DDRSS_CTL_413_DATA 0x03030202
#define DDRSS_CTL_414_DATA 0x00000022
#define DDRSS_CTL_415_DATA 0x00000000
@ -432,13 +433,13 @@
#define DDRSS_CTL_420_DATA 0x00000000
#define DDRSS_CTL_421_DATA 0x00030000
#define DDRSS_CTL_422_DATA 0x0006001E
#define DDRSS_CTL_423_DATA 0x000E0026
#define DDRSS_CTL_424_DATA 0x000E0026
#define DDRSS_CTL_423_DATA 0x0013002B
#define DDRSS_CTL_424_DATA 0x0013002B
#define DDRSS_CTL_425_DATA 0x00000000
#define DDRSS_CTL_426_DATA 0x00000000
#define DDRSS_CTL_427_DATA 0x02000000
#define DDRSS_CTL_428_DATA 0x01000404
#define DDRSS_CTL_429_DATA 0x01080108
#define DDRSS_CTL_429_DATA 0x05120512
#define DDRSS_CTL_430_DATA 0x00000105
#define DDRSS_CTL_431_DATA 0x00010101
#define DDRSS_CTL_432_DATA 0x00010101
@ -447,8 +448,8 @@
#define DDRSS_CTL_435_DATA 0x02000201
#define DDRSS_CTL_436_DATA 0x02010000
#define DDRSS_CTL_437_DATA 0x00000200
#define DDRSS_CTL_438_DATA 0x10060000
#define DDRSS_CTL_439_DATA 0x00000110
#define DDRSS_CTL_438_DATA 0x18060000
#define DDRSS_CTL_439_DATA 0x00000118
#define DDRSS_CTL_440_DATA 0xFFFFFFFF
#define DDRSS_CTL_441_DATA 0xFFFFFFFF
#define DDRSS_CTL_442_DATA 0x00000000
@ -504,10 +505,10 @@
#define DDRSS_PI_32_DATA 0x00000000
#define DDRSS_PI_33_DATA 0x01010102
#define DDRSS_PI_34_DATA 0x00000000
#define DDRSS_PI_35_DATA 0x000000AA
#define DDRSS_PI_36_DATA 0x00000055
#define DDRSS_PI_37_DATA 0x000000B5
#define DDRSS_PI_38_DATA 0x0000004A
#define DDRSS_PI_35_DATA 0x55555A5A
#define DDRSS_PI_36_DATA 0x5555A5A5
#define DDRSS_PI_37_DATA 0x00005A5A
#define DDRSS_PI_38_DATA 0x0000A5A5
#define DDRSS_PI_39_DATA 0x00000056
#define DDRSS_PI_40_DATA 0x000000A9
#define DDRSS_PI_41_DATA 0x000000A9
@ -515,12 +516,12 @@
#define DDRSS_PI_43_DATA 0x00000000
#define DDRSS_PI_44_DATA 0x00000000
#define DDRSS_PI_45_DATA 0x000F0F00
#define DDRSS_PI_46_DATA 0x00000015
#define DDRSS_PI_46_DATA 0x00000017
#define DDRSS_PI_47_DATA 0x000007D0
#define DDRSS_PI_48_DATA 0x00000300
#define DDRSS_PI_49_DATA 0x00000000
#define DDRSS_PI_50_DATA 0x00000000
#define DDRSS_PI_51_DATA 0x01000000
#define DDRSS_PI_51_DATA 0x04080000
#define DDRSS_PI_52_DATA 0x00010101
#define DDRSS_PI_53_DATA 0x00000000
#define DDRSS_PI_54_DATA 0x00030000
@ -632,18 +633,18 @@
#define DDRSS_PI_160_DATA 0x00000000
#define DDRSS_PI_161_DATA 0x00010000
#define DDRSS_PI_162_DATA 0x00000000
#define DDRSS_PI_163_DATA 0x10100100
#define DDRSS_PI_163_DATA 0x1B1B0100
#define DDRSS_PI_164_DATA 0x00000034
#define DDRSS_PI_165_DATA 0x00000043
#define DDRSS_PI_166_DATA 0x00020043
#define DDRSS_PI_165_DATA 0x00000051
#define DDRSS_PI_166_DATA 0x00020051
#define DDRSS_PI_167_DATA 0x02000200
#define DDRSS_PI_168_DATA 0x1C080C04
#define DDRSS_PI_169_DATA 0x000E1C08
#define DDRSS_PI_168_DATA 0x300C0C04
#define DDRSS_PI_169_DATA 0x000E300C
#define DDRSS_PI_170_DATA 0x000000BB
#define DDRSS_PI_171_DATA 0x000000E0
#define DDRSS_PI_172_DATA 0x00000C28
#define DDRSS_PI_173_DATA 0x000000E0
#define DDRSS_PI_174_DATA 0x04000C28
#define DDRSS_PI_171_DATA 0x00000176
#define DDRSS_PI_172_DATA 0x00001448
#define DDRSS_PI_173_DATA 0x00000176
#define DDRSS_PI_174_DATA 0x04001448
#define DDRSS_PI_175_DATA 0x01010404
#define DDRSS_PI_176_DATA 0x00001501
#define DDRSS_PI_177_DATA 0x00150015
@ -652,82 +653,82 @@
#define DDRSS_PI_180_DATA 0x00000000
#define DDRSS_PI_181_DATA 0x01010101
#define DDRSS_PI_182_DATA 0x00000101
#define DDRSS_PI_183_DATA 0x00000000
#define DDRSS_PI_184_DATA 0x00000000
#define DDRSS_PI_185_DATA 0x08040000
#define DDRSS_PI_186_DATA 0x04040208
#define DDRSS_PI_183_DATA 0x00000100
#define DDRSS_PI_184_DATA 0x00000100
#define DDRSS_PI_185_DATA 0x0E040100
#define DDRSS_PI_186_DATA 0x0808020E
#define DDRSS_PI_187_DATA 0x00040402
#define DDRSS_PI_188_DATA 0x000C8034
#define DDRSS_PI_189_DATA 0x0014003C
#define DDRSS_PI_190_DATA 0x0014003C
#define DDRSS_PI_189_DATA 0x00198041
#define DDRSS_PI_190_DATA 0x00198041
#define DDRSS_PI_191_DATA 0x01010101
#define DDRSS_PI_192_DATA 0x0002000D
#define DDRSS_PI_193_DATA 0x000200C8
#define DDRSS_PI_194_DATA 0x010000C8
#define DDRSS_PI_193_DATA 0x0002014E
#define DDRSS_PI_194_DATA 0x0100014E
#define DDRSS_PI_195_DATA 0x000E000E
#define DDRSS_PI_196_DATA 0x00C90100
#define DDRSS_PI_197_DATA 0x010000C9
#define DDRSS_PI_198_DATA 0x00C900C9
#define DDRSS_PI_196_DATA 0x014F0100
#define DDRSS_PI_197_DATA 0x0100014F
#define DDRSS_PI_198_DATA 0x014F014F
#define DDRSS_PI_199_DATA 0x32103200
#define DDRSS_PI_200_DATA 0x01013210
#define DDRSS_PI_201_DATA 0x0A070601
#define DDRSS_PI_202_DATA 0x0D09070D
#define DDRSS_PI_203_DATA 0x0D09070D
#define DDRSS_PI_204_DATA 0x0000C00D
#define DDRSS_PI_202_DATA 0x140D080D
#define DDRSS_PI_203_DATA 0x140D0810
#define DDRSS_PI_204_DATA 0x0000C010
#define DDRSS_PI_205_DATA 0x00C01000
#define DDRSS_PI_206_DATA 0x00C01000
#define DDRSS_PI_207_DATA 0x00021000
#define DDRSS_PI_208_DATA 0x0016000D
#define DDRSS_PI_209_DATA 0x001600C8
#define DDRSS_PI_210_DATA 0x001100C8
#define DDRSS_PI_208_DATA 0x001C000D
#define DDRSS_PI_209_DATA 0x001C014E
#define DDRSS_PI_210_DATA 0x0011014E
#define DDRSS_PI_211_DATA 0x32000056
#define DDRSS_PI_212_DATA 0x00000301
#define DDRSS_PI_213_DATA 0x00580020
#define DDRSS_PI_213_DATA 0x005A002A
#define DDRSS_PI_214_DATA 0x03013212
#define DDRSS_PI_215_DATA 0x00002000
#define DDRSS_PI_216_DATA 0x32120058
#define DDRSS_PI_215_DATA 0x00002A00
#define DDRSS_PI_216_DATA 0x3212005A
#define DDRSS_PI_217_DATA 0x09000301
#define DDRSS_PI_218_DATA 0x04010504
#define DDRSS_PI_219_DATA 0x0400062B
#define DDRSS_PI_220_DATA 0x0A032001
#define DDRSS_PI_221_DATA 0x1113090A
#define DDRSS_PI_222_DATA 0x0000120C
#define DDRSS_PI_223_DATA 0x240062B8
#define DDRSS_PI_224_DATA 0x0C0C2003
#define DDRSS_PI_225_DATA 0x1113090A
#define DDRSS_PI_226_DATA 0x0000120C
#define DDRSS_PI_227_DATA 0x240062B8
#define DDRSS_PI_228_DATA 0x0C0C2003
#define DDRSS_PI_229_DATA 0x0001760A
#define DDRSS_PI_221_DATA 0x1C1F0B0A
#define DDRSS_PI_222_DATA 0x00001D12
#define DDRSS_PI_223_DATA 0x3C00A488
#define DDRSS_PI_224_DATA 0x13142005
#define DDRSS_PI_225_DATA 0x1C1F0B0E
#define DDRSS_PI_226_DATA 0x00001D12
#define DDRSS_PI_227_DATA 0x3C00A488
#define DDRSS_PI_228_DATA 0x13142005
#define DDRSS_PI_229_DATA 0x0001760E
#define DDRSS_PI_230_DATA 0x00000E9C
#define DDRSS_PI_231_DATA 0x00001850
#define DDRSS_PI_232_DATA 0x0000F320
#define DDRSS_PI_233_DATA 0x00001850
#define DDRSS_PI_234_DATA 0x0000F320
#define DDRSS_PI_235_DATA 0x00E6000F
#define DDRSS_PI_236_DATA 0x030300E6
#define DDRSS_PI_231_DATA 0x00002890
#define DDRSS_PI_232_DATA 0x000195A0
#define DDRSS_PI_233_DATA 0x00002890
#define DDRSS_PI_234_DATA 0x000195A0
#define DDRSS_PI_235_DATA 0x0180000F
#define DDRSS_PI_236_DATA 0x03030180
#define DDRSS_PI_237_DATA 0x00271003
#define DDRSS_PI_238_DATA 0x000186A0
#define DDRSS_PI_239_DATA 0x00000005
#define DDRSS_PI_240_DATA 0x00000064
#define DDRSS_PI_241_DATA 0x0000000F
#define DDRSS_PI_242_DATA 0x00027100
#define DDRSS_PI_242_DATA 0x000411AB
#define DDRSS_PI_243_DATA 0x000186A0
#define DDRSS_PI_244_DATA 0x00000005
#define DDRSS_PI_245_DATA 0x00000640
#define DDRSS_PI_246_DATA 0x000000E6
#define DDRSS_PI_247_DATA 0x00027100
#define DDRSS_PI_245_DATA 0x00000A6B
#define DDRSS_PI_246_DATA 0x00000180
#define DDRSS_PI_247_DATA 0x000411AB
#define DDRSS_PI_248_DATA 0x000186A0
#define DDRSS_PI_249_DATA 0x00000005
#define DDRSS_PI_250_DATA 0x00000640
#define DDRSS_PI_251_DATA 0x010000E6
#define DDRSS_PI_250_DATA 0x00000A6B
#define DDRSS_PI_251_DATA 0x01000180
#define DDRSS_PI_252_DATA 0x00320040
#define DDRSS_PI_253_DATA 0x00010008
#define DDRSS_PI_254_DATA 0x03200040
#define DDRSS_PI_255_DATA 0x00010018
#define DDRSS_PI_256_DATA 0x03200040
#define DDRSS_PI_257_DATA 0x00000318
#define DDRSS_PI_258_DATA 0x00280028
#define DDRSS_PI_254_DATA 0x05360040
#define DDRSS_PI_255_DATA 0x00010028
#define DDRSS_PI_256_DATA 0x05360040
#define DDRSS_PI_257_DATA 0x00000328
#define DDRSS_PI_258_DATA 0x00430043
#define DDRSS_PI_259_DATA 0x00040404
#define DDRSS_PI_260_DATA 0x00000055
#define DDRSS_PI_261_DATA 0x55003C5A
@ -746,27 +747,27 @@
#define DDRSS_PI_274_DATA 0x00000000
#define DDRSS_PI_275_DATA 0x002B0084
#define DDRSS_PI_276_DATA 0x00150000
#define DDRSS_PI_277_DATA 0x362B12A4
#define DDRSS_PI_277_DATA 0x362B24C4
#define DDRSS_PI_278_DATA 0x00150F27
#define DDRSS_PI_279_DATA 0x362B12A4
#define DDRSS_PI_279_DATA 0x362B24C4
#define DDRSS_PI_280_DATA 0x00150F27
#define DDRSS_PI_281_DATA 0x002B0084
#define DDRSS_PI_282_DATA 0x00150000
#define DDRSS_PI_283_DATA 0x362B12A4
#define DDRSS_PI_283_DATA 0x362B24C4
#define DDRSS_PI_284_DATA 0x00150F27
#define DDRSS_PI_285_DATA 0x362B12A4
#define DDRSS_PI_285_DATA 0x362B24C4
#define DDRSS_PI_286_DATA 0x00150F27
#define DDRSS_PI_287_DATA 0x002B0084
#define DDRSS_PI_288_DATA 0x00150000
#define DDRSS_PI_289_DATA 0x362B12A4
#define DDRSS_PI_289_DATA 0x362B24C4
#define DDRSS_PI_290_DATA 0x00150F27
#define DDRSS_PI_291_DATA 0x362B12A4
#define DDRSS_PI_291_DATA 0x362B24C4
#define DDRSS_PI_292_DATA 0x00150F27
#define DDRSS_PI_293_DATA 0x002B0084
#define DDRSS_PI_294_DATA 0x00150000
#define DDRSS_PI_295_DATA 0x362B12A4
#define DDRSS_PI_295_DATA 0x362B24C4
#define DDRSS_PI_296_DATA 0x00150F27
#define DDRSS_PI_297_DATA 0x362B12A4
#define DDRSS_PI_297_DATA 0x362B24C4
#define DDRSS_PI_298_DATA 0x00150F27
#define DDRSS_PI_299_DATA 0x00000000
@ -788,10 +789,10 @@
#define DDRSS_PHY_15_DATA 0x00030066
#define DDRSS_PHY_16_DATA 0x00000000
#define DDRSS_PHY_17_DATA 0x00000301
#define DDRSS_PHY_18_DATA 0x0000AAAA
#define DDRSS_PHY_19_DATA 0x00005555
#define DDRSS_PHY_20_DATA 0x0000B5B5
#define DDRSS_PHY_21_DATA 0x00004A4A
#define DDRSS_PHY_18_DATA 0x55555A5A
#define DDRSS_PHY_19_DATA 0x5555A5A5
#define DDRSS_PHY_20_DATA 0x00005A5A
#define DDRSS_PHY_21_DATA 0x0000A5A5
#define DDRSS_PHY_22_DATA 0x00005656
#define DDRSS_PHY_23_DATA 0x0000A9A9
#define DDRSS_PHY_24_DATA 0x0000A9A9
@ -862,7 +863,7 @@
#define DDRSS_PHY_89_DATA 0x10100303
#define DDRSS_PHY_90_DATA 0x10101010
#define DDRSS_PHY_91_DATA 0x10101010
#define DDRSS_PHY_92_DATA 0x00011010
#define DDRSS_PHY_92_DATA 0x00021010
#define DDRSS_PHY_93_DATA 0x00100010
#define DDRSS_PHY_94_DATA 0x00100010
#define DDRSS_PHY_95_DATA 0x00100010
@ -872,18 +873,18 @@
#define DDRSS_PHY_99_DATA 0x31C06000
#define DDRSS_PHY_100_DATA 0x07AB0340
#define DDRSS_PHY_101_DATA 0x00C0C001
#define DDRSS_PHY_102_DATA 0x05040001
#define DDRSS_PHY_102_DATA 0x09080001
#define DDRSS_PHY_103_DATA 0x10001000
#define DDRSS_PHY_104_DATA 0x0C053E42
#define DDRSS_PHY_105_DATA 0x0F0C1D01
#define DDRSS_PHY_104_DATA 0x0C063E42
#define DDRSS_PHY_105_DATA 0x0F0C2701
#define DDRSS_PHY_106_DATA 0x01000140
#define DDRSS_PHY_107_DATA 0x0C000420
#define DDRSS_PHY_108_DATA 0x000001CC
#define DDRSS_PHY_107_DATA 0x04000420
#define DDRSS_PHY_108_DATA 0x00000255
#define DDRSS_PHY_109_DATA 0x0A0000D0
#define DDRSS_PHY_110_DATA 0x00030200
#define DDRSS_PHY_111_DATA 0x02800000
#define DDRSS_PHY_112_DATA 0x80800000
#define DDRSS_PHY_113_DATA 0x00052010
#define DDRSS_PHY_113_DATA 0x00092010
#define DDRSS_PHY_114_DATA 0x76543210
#define DDRSS_PHY_115_DATA 0x00000008
#define DDRSS_PHY_116_DATA 0x02800280
@ -900,8 +901,8 @@
#define DDRSS_PHY_127_DATA 0x00A000A0
#define DDRSS_PHY_128_DATA 0x00A000A0
#define DDRSS_PHY_129_DATA 0x00A000A0
#define DDRSS_PHY_130_DATA 0x011900A0
#define DDRSS_PHY_131_DATA 0x01A00002
#define DDRSS_PHY_130_DATA 0x01C400A0
#define DDRSS_PHY_131_DATA 0x01A00003
#define DDRSS_PHY_132_DATA 0x00000000
#define DDRSS_PHY_133_DATA 0x00000000
#define DDRSS_PHY_134_DATA 0x00080200
@ -1044,10 +1045,10 @@
#define DDRSS_PHY_271_DATA 0x00030066
#define DDRSS_PHY_272_DATA 0x00000000
#define DDRSS_PHY_273_DATA 0x00000301
#define DDRSS_PHY_274_DATA 0x0000AAAA
#define DDRSS_PHY_275_DATA 0x00005555
#define DDRSS_PHY_276_DATA 0x0000B5B5
#define DDRSS_PHY_277_DATA 0x00004A4A
#define DDRSS_PHY_274_DATA 0x55555A5A
#define DDRSS_PHY_275_DATA 0x5555A5A5
#define DDRSS_PHY_276_DATA 0x00005A5A
#define DDRSS_PHY_277_DATA 0x0000A5A5
#define DDRSS_PHY_278_DATA 0x00005656
#define DDRSS_PHY_279_DATA 0x0000A9A9
#define DDRSS_PHY_280_DATA 0x0000A9A9
@ -1118,7 +1119,7 @@
#define DDRSS_PHY_345_DATA 0x10100303
#define DDRSS_PHY_346_DATA 0x10101010
#define DDRSS_PHY_347_DATA 0x10101010
#define DDRSS_PHY_348_DATA 0x00011010
#define DDRSS_PHY_348_DATA 0x00021010
#define DDRSS_PHY_349_DATA 0x00100010
#define DDRSS_PHY_350_DATA 0x00100010
#define DDRSS_PHY_351_DATA 0x00100010
@ -1128,18 +1129,18 @@
#define DDRSS_PHY_355_DATA 0x31C06000
#define DDRSS_PHY_356_DATA 0x07AB0340
#define DDRSS_PHY_357_DATA 0x00C0C001
#define DDRSS_PHY_358_DATA 0x05040001
#define DDRSS_PHY_358_DATA 0x09080001
#define DDRSS_PHY_359_DATA 0x10001000
#define DDRSS_PHY_360_DATA 0x0C053E42
#define DDRSS_PHY_361_DATA 0x0F0C1D01
#define DDRSS_PHY_360_DATA 0x0C063E42
#define DDRSS_PHY_361_DATA 0x0F0C2701
#define DDRSS_PHY_362_DATA 0x01000140
#define DDRSS_PHY_363_DATA 0x0C000420
#define DDRSS_PHY_364_DATA 0x000001CC
#define DDRSS_PHY_363_DATA 0x04000420
#define DDRSS_PHY_364_DATA 0x00000255
#define DDRSS_PHY_365_DATA 0x0A0000D0
#define DDRSS_PHY_366_DATA 0x00030200
#define DDRSS_PHY_367_DATA 0x02800000
#define DDRSS_PHY_368_DATA 0x80800000
#define DDRSS_PHY_369_DATA 0x00052010
#define DDRSS_PHY_369_DATA 0x00092010
#define DDRSS_PHY_370_DATA 0x76543210
#define DDRSS_PHY_371_DATA 0x00000008
#define DDRSS_PHY_372_DATA 0x02800280
@ -1156,8 +1157,8 @@
#define DDRSS_PHY_383_DATA 0x00A000A0
#define DDRSS_PHY_384_DATA 0x00A000A0
#define DDRSS_PHY_385_DATA 0x00A000A0
#define DDRSS_PHY_386_DATA 0x011900A0
#define DDRSS_PHY_387_DATA 0x01A00002
#define DDRSS_PHY_386_DATA 0x01C400A0
#define DDRSS_PHY_387_DATA 0x01A00003
#define DDRSS_PHY_388_DATA 0x00000000
#define DDRSS_PHY_389_DATA 0x00000000
#define DDRSS_PHY_390_DATA 0x00080200
@ -1300,10 +1301,10 @@
#define DDRSS_PHY_527_DATA 0x00030066
#define DDRSS_PHY_528_DATA 0x00000000
#define DDRSS_PHY_529_DATA 0x00000301
#define DDRSS_PHY_530_DATA 0x0000AAAA
#define DDRSS_PHY_531_DATA 0x00005555
#define DDRSS_PHY_532_DATA 0x0000B5B5
#define DDRSS_PHY_533_DATA 0x00004A4A
#define DDRSS_PHY_530_DATA 0x55555A5A
#define DDRSS_PHY_531_DATA 0x5555A5A5
#define DDRSS_PHY_532_DATA 0x00005A5A
#define DDRSS_PHY_533_DATA 0x0000A5A5
#define DDRSS_PHY_534_DATA 0x00005656
#define DDRSS_PHY_535_DATA 0x0000A9A9
#define DDRSS_PHY_536_DATA 0x0000A9A9
@ -1374,7 +1375,7 @@
#define DDRSS_PHY_601_DATA 0x10100303
#define DDRSS_PHY_602_DATA 0x10101010
#define DDRSS_PHY_603_DATA 0x10101010
#define DDRSS_PHY_604_DATA 0x00011010
#define DDRSS_PHY_604_DATA 0x00021010
#define DDRSS_PHY_605_DATA 0x00100010
#define DDRSS_PHY_606_DATA 0x00100010
#define DDRSS_PHY_607_DATA 0x00100010
@ -1384,18 +1385,18 @@
#define DDRSS_PHY_611_DATA 0x31C06000
#define DDRSS_PHY_612_DATA 0x07AB0340
#define DDRSS_PHY_613_DATA 0x00C0C001
#define DDRSS_PHY_614_DATA 0x05040001
#define DDRSS_PHY_614_DATA 0x09080001
#define DDRSS_PHY_615_DATA 0x10001000
#define DDRSS_PHY_616_DATA 0x0C053E42
#define DDRSS_PHY_617_DATA 0x0F0C1D01
#define DDRSS_PHY_616_DATA 0x0C063E42
#define DDRSS_PHY_617_DATA 0x0F0C2701
#define DDRSS_PHY_618_DATA 0x01000140
#define DDRSS_PHY_619_DATA 0x0C000420
#define DDRSS_PHY_620_DATA 0x000001CC
#define DDRSS_PHY_619_DATA 0x04000420
#define DDRSS_PHY_620_DATA 0x00000255
#define DDRSS_PHY_621_DATA 0x0A0000D0
#define DDRSS_PHY_622_DATA 0x00030200
#define DDRSS_PHY_623_DATA 0x02800000
#define DDRSS_PHY_624_DATA 0x80800000
#define DDRSS_PHY_625_DATA 0x00052010
#define DDRSS_PHY_625_DATA 0x00092010
#define DDRSS_PHY_626_DATA 0x76543210
#define DDRSS_PHY_627_DATA 0x00000008
#define DDRSS_PHY_628_DATA 0x02800280
@ -1412,8 +1413,8 @@
#define DDRSS_PHY_639_DATA 0x00A000A0
#define DDRSS_PHY_640_DATA 0x00A000A0
#define DDRSS_PHY_641_DATA 0x00A000A0
#define DDRSS_PHY_642_DATA 0x011900A0
#define DDRSS_PHY_643_DATA 0x01A00002
#define DDRSS_PHY_642_DATA 0x01C400A0
#define DDRSS_PHY_643_DATA 0x01A00003
#define DDRSS_PHY_644_DATA 0x00000000
#define DDRSS_PHY_645_DATA 0x00000000
#define DDRSS_PHY_646_DATA 0x00080200
@ -1556,10 +1557,10 @@
#define DDRSS_PHY_783_DATA 0x00030066
#define DDRSS_PHY_784_DATA 0x00000000
#define DDRSS_PHY_785_DATA 0x00000301
#define DDRSS_PHY_786_DATA 0x0000AAAA
#define DDRSS_PHY_787_DATA 0x00005555
#define DDRSS_PHY_788_DATA 0x0000B5B5
#define DDRSS_PHY_789_DATA 0x00004A4A
#define DDRSS_PHY_786_DATA 0x55555A5A
#define DDRSS_PHY_787_DATA 0x5555A5A5
#define DDRSS_PHY_788_DATA 0x00005A5A
#define DDRSS_PHY_789_DATA 0x0000A5A5
#define DDRSS_PHY_790_DATA 0x00005656
#define DDRSS_PHY_791_DATA 0x0000A9A9
#define DDRSS_PHY_792_DATA 0x0000A9A9
@ -1630,7 +1631,7 @@
#define DDRSS_PHY_857_DATA 0x10100303
#define DDRSS_PHY_858_DATA 0x10101010
#define DDRSS_PHY_859_DATA 0x10101010
#define DDRSS_PHY_860_DATA 0x00011010
#define DDRSS_PHY_860_DATA 0x00021010
#define DDRSS_PHY_861_DATA 0x00100010
#define DDRSS_PHY_862_DATA 0x00100010
#define DDRSS_PHY_863_DATA 0x00100010
@ -1640,18 +1641,18 @@
#define DDRSS_PHY_867_DATA 0x31C06000
#define DDRSS_PHY_868_DATA 0x07AB0340
#define DDRSS_PHY_869_DATA 0x00C0C001
#define DDRSS_PHY_870_DATA 0x05040001
#define DDRSS_PHY_870_DATA 0x09080001
#define DDRSS_PHY_871_DATA 0x10001000
#define DDRSS_PHY_872_DATA 0x0C053E42
#define DDRSS_PHY_873_DATA 0x0F0C1D01
#define DDRSS_PHY_872_DATA 0x0C063E42
#define DDRSS_PHY_873_DATA 0x0F0C2701
#define DDRSS_PHY_874_DATA 0x01000140
#define DDRSS_PHY_875_DATA 0x0C000420
#define DDRSS_PHY_876_DATA 0x000001CC
#define DDRSS_PHY_875_DATA 0x04000420
#define DDRSS_PHY_876_DATA 0x00000255
#define DDRSS_PHY_877_DATA 0x0A0000D0
#define DDRSS_PHY_878_DATA 0x00030200
#define DDRSS_PHY_879_DATA 0x02800000
#define DDRSS_PHY_880_DATA 0x80800000
#define DDRSS_PHY_881_DATA 0x00052010
#define DDRSS_PHY_881_DATA 0x00092010
#define DDRSS_PHY_882_DATA 0x76543210
#define DDRSS_PHY_883_DATA 0x00000008
#define DDRSS_PHY_884_DATA 0x02800280
@ -1668,13 +1669,13 @@
#define DDRSS_PHY_895_DATA 0x00A000A0
#define DDRSS_PHY_896_DATA 0x00A000A0
#define DDRSS_PHY_897_DATA 0x00A000A0
#define DDRSS_PHY_898_DATA 0x011900A0
#define DDRSS_PHY_899_DATA 0x01A00002
#define DDRSS_PHY_898_DATA 0x01C400A0
#define DDRSS_PHY_899_DATA 0x01A00003
#define DDRSS_PHY_900_DATA 0x00000000
#define DDRSS_PHY_901_DATA 0x00000000
#define DDRSS_PHY_902_DATA 0x00080200
#define DDRSS_PHY_903_DATA 0x00000000
#define DDRSS_PHY_904_DATA 0x20202010
#define DDRSS_PHY_904_DATA 0x20202000
#define DDRSS_PHY_905_DATA 0x20202020
#define DDRSS_PHY_906_DATA 0xF0F02020
#define DDRSS_PHY_907_DATA 0x00000000

19
arch/arm/dts/k3-j7200-r5-common-proc-board.dts
View file

@ -6,7 +6,7 @@
/dts-v1/;
#include "k3-j7200-som-p0.dtsi"
#include "k3-j7200-ddr-evm-lp4-1600.dtsi"
#include "k3-j7200-ddr-evm-lp4-2666.dtsi"
#include "k3-j721e-ddr.dtsi"
/ {
@ -79,6 +79,16 @@
mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
mbox-names = "tx", "rx";
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <3>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&mcu_secproxy 21>,
<&mcu_secproxy 23>;
u-boot,dm-spl;
};
};
&dmsc {
@ -276,4 +286,11 @@
};
};
&mcu_ringacc {
ti,sci = <&dm_tifs>;
};
&mcu_udmap {
ti,sci = <&dm_tifs>;
};
#include "k3-j7200-common-proc-board-u-boot.dtsi"

16
arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
View file

@ -46,7 +46,7 @@
compatible = "ti,omap5430-timer";
reg = <0x0 0x40400000 0x0 0x80>;
ti,timer-alwon;
clock-frequency = <25000000>;
clock-frequency = <250000000>;
u-boot,dm-spl;
};
@ -54,10 +54,24 @@
u-boot,dm-spl;
ringacc@2b800000 {
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
<0x0 0x28590000 0x0 0x100>,
<0x0 0x2a500000 0x0 0x40000>,
<0x0 0x28440000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
u-boot,dm-spl;
};
dma-controller@285c0000 {
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x284c0000 0x0 0x4000>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x284a0000 0x0 0x4000>,
<0x0 0x2aa00000 0x0 0x40000>,
<0x0 0x28400000 0x0 0x2000>;
reg-names = "gcfg", "rchan", "rchanrt", "tchan",
"tchanrt", "rflow";
u-boot,dm-spl;
};
};

18
arch/arm/dts/k3-j721e-r5-common-proc-board.dts
View file

@ -76,6 +76,16 @@
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <3>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&mcu_secproxy 21>,
<&mcu_secproxy 23>;
u-boot,dm-spl;
};
};
&cbass_main {
@ -345,3 +355,11 @@
u-boot,dm-spl;
};
};
&mcu_ringacc {
ti,sci = <&dm_tifs>;
};
&mcu_udmap {
ti,sci = <&dm_tifs>;
};

184
arch/arm/dts/r8a779a0-falcon-cpu.dtsi Normal file
View file

@ -0,0 +1,184 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Falcon CPU board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
#include "r8a779a0.dtsi"
/ {
model = "Renesas Falcon CPU board";
compatible = "renesas,falcon-cpu", "renesas,r8a779a0";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@500000000 {
device_type = "memory";
reg = <0x5 0x00000000 0x0 0x80000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x0 0x80000000>;
};
memory@700000000 {
device_type = "memory";
reg = <0x7 0x00000000 0x0 0x80000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&avb0 {
pinctrl-0 = <&avb0_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
tx-internal-delay-ps = <2000>;
status = "okay";
phy0: ethernet-phy@0 {
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio4>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
};
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
};
&i2c6 {
pinctrl-0 = <&i2c6_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
};
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-1 = <&mmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
full-pwr-cycle-in-suspend;
status = "okay";
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
avb0_pins: avb0 {
mux {
groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
function = "avb0";
};
pins_mdio {
groups = "avb0_mdio";
drive-strength = <21>;
};
pins_mii {
groups = "avb0_rgmii";
drive-strength = <21>;
};
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
i2c1_pins: i2c1 {
groups = "i2c1";
function = "i2c1";
};
i2c6_pins: i2c6 {
groups = "i2c6";
function = "i2c6";
};
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
power-source = <1800>;
};
scif0_pins: scif0 {
groups = "scif0_data", "scif0_ctrl";
function = "scif0";
};
scif_clk_pins: scif_clk {
groups = "scif_clk";
function = "scif_clk";
};
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&scif_clk {
clock-frequency = <24000000>;
};

32
arch/arm/dts/r8a779a0-falcon-u-boot.dts Normal file
View file

@ -0,0 +1,32 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot for the Falcon board
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a779a0-falcon.dts"
#include "r8a779a0-u-boot.dtsi"
/ {
aliases {
spi0 = &rpc;
};
};
&rpc {
#address-cells = <1>;
#size-cells = <0>;
num-cs = <1>;
spi-max-frequency = <50000000>;
status = "okay";
spi-flash@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
status = "okay";
};
};

28
arch/arm/dts/r8a779a0-falcon.dts Normal file
View file

@ -0,0 +1,28 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Falcon CPU and BreakOut boards
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a779a0-falcon-cpu.dtsi"
/ {
model = "Renesas Falcon CPU and Breakout boards based on r8a779a0";
compatible = "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0";
aliases {
ethernet0 = &avb0;
serial0 = &scif0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};

25
arch/arm/dts/r8a779a0-u-boot.dtsi Normal file
View file

@ -0,0 +1,25 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source extras for U-Boot on R-Car R8A779A0 SoC
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include "r8a779x-u-boot.dtsi"
/ {
soc {
rpc: spi@ee200000 {
compatible = "renesas,rpc-r8a779a0", "renesas,rcar-gen3-rpc";
reg = <0 0xee200000 0 0x200>, <0 0x08000000 0 0x04000000>;
clocks = <&cpg CPG_MOD 629>;
bank-width = <2>;
num-cs = <1>;
status = "disabled";
};
};
};
&extalr_clk {
u-boot,dm-pre-reloc;
};

970
arch/arm/dts/r8a779a0.dtsi Normal file
View file

@ -0,0 +1,970 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the R-Car V3U (R8A779A0) SoC
*
* Copyright (C) 2020 Renesas Electronics Corp.
*/
#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a779a0-sysc.h>
/ {
compatible = "renesas,r8a779a0";
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
a76_0: cpu@0 {
compatible = "arm,cortex-a76";
reg = <0>;
device_type = "cpu";
power-domains = <&sysc R8A779A0_PD_A1E0D0C0>;
next-level-cache = <&L3_CA76_0>;
};
L3_CA76_0: cache-controller-0 {
compatible = "cache";
power-domains = <&sysc R8A779A0_PD_A2E0D0>;
cache-unified;
cache-level = <3>;
};
};
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
extalr_clk: extalr {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
pmu_a76 {
compatible = "arm,cortex-a76-pmu";
interrupts-extended = <&gic GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
};
/* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a779a0-wdt",
"renesas,rcar-gen3-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 907>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 907>;
status = "disabled";
};
pfc: pin-controller@e6050000 {
compatible = "renesas,pfc-r8a779a0";
reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
<0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
<0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
<0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>,
<0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>;
};
gpio0: gpio@e6058180 {
compatible = "renesas,gpio-r8a779a0";
reg = <0 0xe6058180 0 0x54>;
interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 916>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 916>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 0 28>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@e6050180 {
compatible = "renesas,gpio-r8a779a0";
reg = <0 0xe6050180 0 0x54>;
interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 915>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 915>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 32 31>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@e6050980 {
compatible = "renesas,gpio-r8a779a0";
reg = <0 0xe6050980 0 0x54>;
interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 915>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 915>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 64 25>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@e6058980 {
compatible = "renesas,gpio-r8a779a0";
reg = <0 0xe6058980 0 0x54>;
interrupts = <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 916>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 916>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 96 17>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@e6060180 {
compatible = "renesas,gpio-r8a779a0";
reg = <0 0xe6060180 0 0x54>;
interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 917>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 128 27>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio5: gpio@e6060980 {
compatible = "renesas,gpio-r8a779a0";
reg = <0 0xe6060980 0 0x54>;
interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 917>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 160 21>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio6: gpio@e6068180 {
compatible = "renesas,gpio-r8a779a0";
reg = <0 0xe6068180 0 0x54>;
interrupts = <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 918>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 918>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 192 21>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio7: gpio@e6068980 {
compatible = "renesas,gpio-r8a779a0";
reg = <0 0xe6068980 0 0x54>;
interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 918>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 918>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 224 21>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio8: gpio@e6069180 {
compatible = "renesas,gpio-r8a779a0";
reg = <0 0xe6069180 0 0x54>;
interrupts = <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 918>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 918>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 256 21>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio9: gpio@e6069980 {
compatible = "renesas,gpio-r8a779a0";
reg = <0 0xe6069980 0 0x54>;
interrupts = <GIC_SPI 868 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 918>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 918>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pfc 0 288 21>;
interrupt-controller;
#interrupt-cells = <2>;
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a779a0-cpg-mssr";
reg = <0 0xe6150000 0 0x4000>;
clocks = <&extal_clk>, <&extalr_clk>;
clock-names = "extal", "extalr";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a779a0-rst";
reg = <0 0xe6160000 0 0x4000>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a779a0-sysc";
reg = <0 0xe6180000 0 0x4000>;
#power-domain-cells = <1>;
};
i2c0: i2c@e6500000 {
compatible = "renesas,i2c-r8a779a0",
"renesas,rcar-gen3-i2c";
reg = <0 0xe6500000 0 0x40>;
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 518>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 518>;
dmas = <&dmac1 0x91>, <&dmac1 0x90>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@e6508000 {
compatible = "renesas,i2c-r8a779a0",
"renesas,rcar-gen3-i2c";
reg = <0 0xe6508000 0 0x40>;
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 519>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 519>;
dmas = <&dmac1 0x93>, <&dmac1 0x92>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@e6510000 {
compatible = "renesas,i2c-r8a779a0",
"renesas,rcar-gen3-i2c";
reg = <0 0xe6510000 0 0x40>;
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 520>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 520>;
dmas = <&dmac1 0x95>, <&dmac1 0x94>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@e66d0000 {
compatible = "renesas,i2c-r8a779a0",
"renesas,rcar-gen3-i2c";
reg = <0 0xe66d0000 0 0x40>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 521>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 521>;
dmas = <&dmac1 0x97>, <&dmac1 0x96>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@e66d8000 {
compatible = "renesas,i2c-r8a779a0",
"renesas,rcar-gen3-i2c";
reg = <0 0xe66d8000 0 0x40>;
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 522>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 522>;
dmas = <&dmac1 0x99>, <&dmac1 0x98>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c5: i2c@e66e0000 {
compatible = "renesas,i2c-r8a779a0",
"renesas,rcar-gen3-i2c";
reg = <0 0xe66e0000 0 0x40>;
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 523>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 523>;
dmas = <&dmac1 0x9b>, <&dmac1 0x9a>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c6: i2c@e66e8000 {
compatible = "renesas,i2c-r8a779a0",
"renesas,rcar-gen3-i2c";
reg = <0 0xe66e8000 0 0x40>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 524>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 524>;
dmas = <&dmac1 0x9d>, <&dmac1 0x9c>;
dma-names = "tx", "rx";
i2c-scl-internal-delay-ns = <110>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
hscif0: serial@e6540000 {
compatible = "renesas,hscif-r8a779a0",
"renesas,rcar-gen3-hscif", "renesas,hscif";
reg = <0 0xe6540000 0 0x60>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 514>,
<&cpg CPG_CORE R8A779A0_CLK_S1D2>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x31>, <&dmac1 0x30>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 514>;
status = "disabled";
};
hscif1: serial@e6550000 {
compatible = "renesas,hscif-r8a779a0",
"renesas,rcar-gen3-hscif", "renesas,hscif";
reg = <0 0xe6550000 0 0x60>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 515>,
<&cpg CPG_CORE R8A779A0_CLK_S1D2>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x33>, <&dmac1 0x32>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 515>;
status = "disabled";
};
hscif2: serial@e6560000 {
compatible = "renesas,hscif-r8a779a0",
"renesas,rcar-gen3-hscif", "renesas,hscif";
reg = <0 0xe6560000 0 0x60>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 516>,
<&cpg CPG_CORE R8A779A0_CLK_S1D2>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x35>, <&dmac1 0x34>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 516>;
status = "disabled";
};
hscif3: serial@e66a0000 {
compatible = "renesas,hscif-r8a779a0",
"renesas,rcar-gen3-hscif", "renesas,hscif";
reg = <0 0xe66a0000 0 0x60>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 517>,
<&cpg CPG_CORE R8A779A0_CLK_S1D2>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x37>, <&dmac1 0x36>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 517>;
status = "disabled";
};
avb0: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a779a0",
"renesas,etheravb-rcar-gen3";
reg = <0 0xe6800000 0 0x800>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15",
"ch16", "ch17", "ch18", "ch19",
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 211>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 211>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
avb1: ethernet@e6810000 {
compatible = "renesas,etheravb-r8a779a0",
"renesas,etheravb-rcar-gen3";
reg = <0 0xe6810000 0 0x800>;
interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15",
"ch16", "ch17", "ch18", "ch19",
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 212>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 212>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
avb2: ethernet@e6820000 {
compatible = "renesas,etheravb-r8a779a0",
"renesas,etheravb-rcar-gen3";
reg = <0 0xe6820000 0 0x1000>;
interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15",
"ch16", "ch17", "ch18", "ch19",
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 213>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 213>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
avb3: ethernet@e6830000 {
compatible = "renesas,etheravb-r8a779a0",
"renesas,etheravb-rcar-gen3";
reg = <0 0xe6830000 0 0x1000>;
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15",
"ch16", "ch17", "ch18", "ch19",
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 214>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 214>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
avb4: ethernet@e6840000 {
compatible = "renesas,etheravb-r8a779a0",
"renesas,etheravb-rcar-gen3";
reg = <0 0xe6840000 0 0x1000>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15",
"ch16", "ch17", "ch18", "ch19",
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 215>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 215>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
avb5: ethernet@e6850000 {
compatible = "renesas,etheravb-r8a779a0",
"renesas,etheravb-rcar-gen3";
reg = <0 0xe6850000 0 0x1000>;
interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15",
"ch16", "ch17", "ch18", "ch19",
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 216>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 216>;
phy-mode = "rgmii";
rx-internal-delay-ps = <0>;
tx-internal-delay-ps = <0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a779a0",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6e60000 0 64>;
interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 702>,
<&cpg CPG_CORE R8A779A0_CLK_S1D2>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x51>, <&dmac1 0x50>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 702>;
status = "disabled";
};
scif1: serial@e6e68000 {
compatible = "renesas,scif-r8a779a0",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6e68000 0 64>;
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>,
<&cpg CPG_CORE R8A779A0_CLK_S1D2>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x53>, <&dmac1 0x52>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 703>;
status = "disabled";
};
scif3: serial@e6c50000 {
compatible = "renesas,scif-r8a779a0",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6c50000 0 64>;
interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 704>,
<&cpg CPG_CORE R8A779A0_CLK_S1D2>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x57>, <&dmac1 0x56>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 704>;
status = "disabled";
};
scif4: serial@e6c40000 {
compatible = "renesas,scif-r8a779a0",
"renesas,rcar-gen3-scif", "renesas,scif";
reg = <0 0xe6c40000 0 64>;
interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 705>,
<&cpg CPG_CORE R8A779A0_CLK_S1D2>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac1 0x59>, <&dmac1 0x58>;
dma-names = "tx", "rx";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 705>;
status = "disabled";
};
msiof0: spi@e6e90000 {
compatible = "renesas,msiof-r8a779a0",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6e90000 0 0x0064>;
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 618>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 618>;
dmas = <&dmac1 0x41>, <&dmac1 0x40>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof1: spi@e6ea0000 {
compatible = "renesas,msiof-r8a779a0",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6ea0000 0 0x0064>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 619>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 619>;
dmas = <&dmac1 0x43>, <&dmac1 0x42>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof2: spi@e6c00000 {
compatible = "renesas,msiof-r8a779a0",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6c00000 0 0x0064>;
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 620>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 620>;
dmas = <&dmac1 0x45>, <&dmac1 0x44>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof3: spi@e6c10000 {
compatible = "renesas,msiof-r8a779a0",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6c10000 0 0x0064>;
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 621>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 621>;
dmas = <&dmac1 0x47>, <&dmac1 0x46>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof4: spi@e6c20000 {
compatible = "renesas,msiof-r8a779a0",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6c20000 0 0x0064>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 622>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 622>;
dmas = <&dmac1 0x49>, <&dmac1 0x48>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof5: spi@e6c28000 {
compatible = "renesas,msiof-r8a779a0",
"renesas,rcar-gen3-msiof";
reg = <0 0xe6c28000 0 0x0064>;
interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 623>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 623>;
dmas = <&dmac1 0x4b>, <&dmac1 0x4a>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
dmac1: dma-controller@e7350000 {
compatible = "renesas,dmac-r8a779a0";
reg = <0 0xe7350000 0 0x1000>,
<0 0xe7300000 0 0x10000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3", "ch4",
"ch5", "ch6", "ch7", "ch8", "ch9",
"ch10", "ch11", "ch12", "ch13",
"ch14", "ch15";
clocks = <&cpg CPG_MOD 709>;
clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 709>;
#dma-cells = <1>;
dma-channels = <16>;
};
dmac2: dma-controller@e7351000 {
compatible = "renesas,dmac-r8a779a0";
reg = <0 0xe7351000 0 0x1000>,
<0 0xe7310000 0 0x10000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3", "ch4",
"ch5", "ch6", "ch7";
clocks = <&cpg CPG_MOD 710>;
clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 710>;
#dma-cells = <1>;
dma-channels = <8>;
};
mmc0: mmc@ee140000 {
compatible = "renesas,sdhi-r8a779a0",
"renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 706>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 706>;
max-frequency = <200000000>;
status = "disabled";
};
gic: interrupt-controller@f1000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xf1000000 0 0x20000>,
<0x0 0xf1060000 0 0x110000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
};
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
};

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// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
*/
#include "rk3568-u-boot.dtsi"
/ {
chosen {
stdout-path = &uart2;
u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
};
};
&sdmmc0 {
status = "okay";
};
&uart2 {
clock-frequency = <24000000>;
u-boot,dm-spl;
status = "okay";
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3568.dtsi"
/ {
model = "Rockchip RK3568 EVB1 DDR4 V10 Board";
compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568";
chosen: chosen {
stdout-path = "serial2:1500000n8";
};
dc_12v: dc-12v {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc3v3_sys: vcc3v3-sys {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&dc_12v>;
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_12v>;
};
vcc3v3_lcd0_n: vcc3v3-lcd0-n {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_lcd0_n";
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vcc3v3_lcd1_n: vcc3v3-lcd1-n {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_lcd1_n";
regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
};
&sdhci {
bus-width = <8>;
max-frequency = <200000000>;
non-removable;
status = "okay";
};
&uart2 {
status = "okay";
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
*/
/ {
aliases {
mmc0 = &sdhci;
mmc1 = &sdmmc0;
};
dmc: dmc {
compatible = "rockchip,rk3568-dmc";
u-boot,dm-pre-reloc;
status = "okay";
};
};
&cru {
u-boot,dm-pre-reloc;
status = "okay";
};
&pmucru {
u-boot,dm-pre-reloc;
status = "okay";
};
&grf {
u-boot,dm-pre-reloc;
status = "okay";
};
&pmugrf {
u-boot,dm-pre-reloc;
status = "okay";
};

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*/
#include <dt-bindings/clock/rk3568-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "rockchip,rk3568";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
gpio4 = &gpio4;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
serial6 = &uart6;
serial7 = &uart7;
serial8 = &uart8;
serial9 = &uart9;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
clocks = <&scmi_clk 0>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
enable-method = "psci";
operating-points-v2 = <&cpu0_opp_table>;
};
};
cpu0_opp_table: cpu0-opp-table {
compatible = "operating-points-v2";
opp-shared;
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <900000 900000 1150000>;
clock-latency-ns = <40000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <900000 900000 1150000>;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <900000 900000 1150000>;
opp-suspend;
};
opp-1104000000 {
opp-hz = /bits/ 64 <1104000000>;
opp-microvolt = <900000 900000 1150000>;
};
opp-1416000000 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <900000 900000 1150000>;
};
opp-1608000000 {
opp-hz = /bits/ 64 <1608000000>;
opp-microvolt = <975000 975000 1150000>;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1050000 1050000 1150000>;
};
opp-1992000000 {
opp-hz = /bits/ 64 <1992000000>;
opp-microvolt = <1150000 1150000 1150000>;
};
};
firmware {
scmi: scmi {
compatible = "arm,scmi-smc";
arm,smc-id = <0x82000010>;
shmem = <&scmi_shmem>;
#address-cells = <1>;
#size-cells = <0>;
scmi_clk: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
};
};
};
pmu {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
arm,no-tick-in-suspend;
};
xin24m: xin24m {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xin24m";
#clock-cells = <0>;
};
xin32k: xin32k {
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "xin32k";
pinctrl-0 = <&clk32k_out0>;
pinctrl-names = "default";
#clock-cells = <0>;
};
sram@10f000 {
compatible = "mmio-sram";
reg = <0x0 0x0010f000 0x0 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x0010f000 0x100>;
scmi_shmem: sram@0 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x100>;
};
};
gic: interrupt-controller@fd400000 {
compatible = "arm,gic-v3";
reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
<0x0 0xfd460000 0 0x80000>; /* GICR */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
mbi-alias = <0x0 0xfd100000>;
mbi-ranges = <296 24>;
msi-controller;
};
pmugrf: syscon@fdc20000 {
compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xfdc20000 0x0 0x10000>;
};
grf: syscon@fdc60000 {
compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
reg = <0x0 0xfdc60000 0x0 0x10000>;
};
pmucru: clock-controller@fdd00000 {
compatible = "rockchip,rk3568-pmucru";
reg = <0x0 0xfdd00000 0x0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
cru: clock-controller@fdd20000 {
compatible = "rockchip,rk3568-cru";
reg = <0x0 0xfdd20000 0x0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
i2c0: i2c@fdd40000 {
compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0xfdd40000 0x0 0x1000>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
clock-names = "i2c", "pclk";
pinctrl-0 = <&i2c0_xfer>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart0: serial@fdd50000 {
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
reg = <0x0 0xfdd50000 0x0 0x100>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac0 0>, <&dmac0 1>;
pinctrl-0 = <&uart0_xfer>;
pinctrl-names = "default";
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
pwm0: pwm@fdd70000 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfdd70000 0x0 0x10>;
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm0m0_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm1: pwm@fdd70010 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfdd70010 0x0 0x10>;
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm1m0_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm2: pwm@fdd70020 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfdd70020 0x0 0x10>;
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm2m0_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm3: pwm@fdd70030 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfdd70030 0x0 0x10>;
clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm3_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
sdmmc2: mmc@fe000000 {
compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe000000 0x0 0x4000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
<&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <150000000>;
resets = <&cru SRST_SDMMC2>;
reset-names = "reset";
status = "disabled";
};
sdmmc0: mmc@fe2b0000 {
compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe2b0000 0x0 0x4000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
<&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <150000000>;
resets = <&cru SRST_SDMMC0>;
reset-names = "reset";
status = "disabled";
};
sdmmc1: mmc@fe2c0000 {
compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe2c0000 0x0 0x4000>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
<&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
fifo-depth = <0x100>;
max-frequency = <150000000>;
resets = <&cru SRST_SDMMC1>;
reset-names = "reset";
status = "disabled";
};
sdhci: mmc@fe310000 {
compatible = "rockchip,rk3568-dwcmshc";
reg = <0x0 0xfe310000 0x0 0x10000>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
assigned-clock-rates = <200000000>, <24000000>;
clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
<&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
<&cru TCLK_EMMC>;
clock-names = "core", "bus", "axi", "block", "timer";
status = "disabled";
};
dmac0: dmac@fe530000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xfe530000 0x0 0x4000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
arm,pl330-periph-burst;
clocks = <&cru ACLK_BUS>;
clock-names = "apb_pclk";
#dma-cells = <1>;
};
dmac1: dmac@fe550000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xfe550000 0x0 0x4000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
arm,pl330-periph-burst;
clocks = <&cru ACLK_BUS>;
clock-names = "apb_pclk";
#dma-cells = <1>;
};
i2c1: i2c@fe5a0000 {
compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0xfe5a0000 0x0 0x1000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
clock-names = "i2c", "pclk";
pinctrl-0 = <&i2c1_xfer>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@fe5b0000 {
compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0xfe5b0000 0x0 0x1000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
clock-names = "i2c", "pclk";
pinctrl-0 = <&i2c2m0_xfer>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@fe5c0000 {
compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0xfe5c0000 0x0 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
clock-names = "i2c", "pclk";
pinctrl-0 = <&i2c3m0_xfer>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@fe5d0000 {
compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0xfe5d0000 0x0 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
clock-names = "i2c", "pclk";
pinctrl-0 = <&i2c4m0_xfer>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c5: i2c@fe5e0000 {
compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0xfe5e0000 0x0 0x1000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
clock-names = "i2c", "pclk";
pinctrl-0 = <&i2c5m0_xfer>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
wdt: watchdog@fe600000 {
compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
reg = <0x0 0xfe600000 0x0 0x100>;
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
clock-names = "tclk", "pclk";
};
uart1: serial@fe650000 {
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
reg = <0x0 0xfe650000 0x0 0x100>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac0 2>, <&dmac0 3>;
pinctrl-0 = <&uart1m0_xfer>;
pinctrl-names = "default";
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart2: serial@fe660000 {
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
reg = <0x0 0xfe660000 0x0 0x100>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac0 4>, <&dmac0 5>;
pinctrl-0 = <&uart2m0_xfer>;
pinctrl-names = "default";
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart3: serial@fe670000 {
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
reg = <0x0 0xfe670000 0x0 0x100>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac0 6>, <&dmac0 7>;
pinctrl-0 = <&uart3m0_xfer>;
pinctrl-names = "default";
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart4: serial@fe680000 {
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
reg = <0x0 0xfe680000 0x0 0x100>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac0 8>, <&dmac0 9>;
pinctrl-0 = <&uart4m0_xfer>;
pinctrl-names = "default";
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart5: serial@fe690000 {
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
reg = <0x0 0xfe690000 0x0 0x100>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac0 10>, <&dmac0 11>;
pinctrl-0 = <&uart5m0_xfer>;
pinctrl-names = "default";
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart6: serial@fe6a0000 {
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
reg = <0x0 0xfe6a0000 0x0 0x100>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac0 12>, <&dmac0 13>;
pinctrl-0 = <&uart6m0_xfer>;
pinctrl-names = "default";
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart7: serial@fe6b0000 {
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
reg = <0x0 0xfe6b0000 0x0 0x100>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac0 14>, <&dmac0 15>;
pinctrl-0 = <&uart7m0_xfer>;
pinctrl-names = "default";
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart8: serial@fe6c0000 {
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
reg = <0x0 0xfe6c0000 0x0 0x100>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac0 16>, <&dmac0 17>;
pinctrl-0 = <&uart8m0_xfer>;
pinctrl-names = "default";
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
uart9: serial@fe6d0000 {
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
reg = <0x0 0xfe6d0000 0x0 0x100>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmac0 18>, <&dmac0 19>;
pinctrl-0 = <&uart9m0_xfer>;
pinctrl-names = "default";
reg-io-width = <4>;
reg-shift = <2>;
status = "disabled";
};
pwm4: pwm@fe6e0000 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe6e0000 0x0 0x10>;
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm4_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm5: pwm@fe6e0010 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe6e0010 0x0 0x10>;
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm5_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm6: pwm@fe6e0020 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe6e0020 0x0 0x10>;
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm6_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm7: pwm@fe6e0030 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe6e0030 0x0 0x10>;
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm7_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm8: pwm@fe6f0000 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe6f0000 0x0 0x10>;
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm8m0_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm9: pwm@fe6f0010 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe6f0010 0x0 0x10>;
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm9m0_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm10: pwm@fe6f0020 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe6f0020 0x0 0x10>;
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm10m0_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm11: pwm@fe6f0030 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe6f0030 0x0 0x10>;
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm11m0_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm12: pwm@fe700000 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe700000 0x0 0x10>;
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm12m0_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm13: pwm@fe700010 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe700010 0x0 0x10>;
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm13m0_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm14: pwm@fe700020 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe700020 0x0 0x10>;
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm14m0_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pwm15: pwm@fe700030 {
compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
reg = <0x0 0xfe700030 0x0 0x10>;
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
clock-names = "pwm", "pclk";
pinctrl-0 = <&pwm15m0_pins>;
pinctrl-names = "active";
#pwm-cells = <3>;
status = "disabled";
};
pinctrl: pinctrl {
compatible = "rockchip,rk3568-pinctrl";
rockchip,grf = <&grf>;
rockchip,pmu = <&pmugrf>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio0: gpio@fdd60000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xfdd60000 0x0 0x100>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@fe740000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xfe740000 0x0 0x100>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@fe750000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xfe750000 0x0 0x100>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@fe760000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xfe760000 0x0 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@fe770000 {
compatible = "rockchip,gpio-bank";
reg = <0x0 0xfe770000 0x0 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
#include "rk3568-pinctrl.dtsi"

344
arch/arm/dts/rockchip-pinconf.dtsi Normal file
View file

@ -0,0 +1,344 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*/
&pinctrl {
/omit-if-no-ref/
pcfg_pull_up: pcfg-pull-up {
bias-pull-up;
};
/omit-if-no-ref/
pcfg_pull_down: pcfg-pull-down {
bias-pull-down;
};
/omit-if-no-ref/
pcfg_pull_none: pcfg-pull-none {
bias-disable;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
bias-disable;
drive-strength = <0>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
bias-disable;
drive-strength = <1>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
bias-disable;
drive-strength = <2>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
bias-disable;
drive-strength = <3>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 {
bias-disable;
drive-strength = <4>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 {
bias-disable;
drive-strength = <5>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 {
bias-disable;
drive-strength = <6>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 {
bias-disable;
drive-strength = <7>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 {
bias-disable;
drive-strength = <8>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 {
bias-disable;
drive-strength = <9>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 {
bias-disable;
drive-strength = <10>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 {
bias-disable;
drive-strength = <11>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 {
bias-disable;
drive-strength = <12>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 {
bias-disable;
drive-strength = <13>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 {
bias-disable;
drive-strength = <14>;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 {
bias-disable;
drive-strength = <15>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 {
bias-pull-up;
drive-strength = <0>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 {
bias-pull-up;
drive-strength = <1>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 {
bias-pull-up;
drive-strength = <2>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 {
bias-pull-up;
drive-strength = <3>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 {
bias-pull-up;
drive-strength = <4>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 {
bias-pull-up;
drive-strength = <5>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 {
bias-pull-up;
drive-strength = <6>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 {
bias-pull-up;
drive-strength = <7>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 {
bias-pull-up;
drive-strength = <8>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 {
bias-pull-up;
drive-strength = <9>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 {
bias-pull-up;
drive-strength = <10>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 {
bias-pull-up;
drive-strength = <11>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 {
bias-pull-up;
drive-strength = <12>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 {
bias-pull-up;
drive-strength = <13>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 {
bias-pull-up;
drive-strength = <14>;
};
/omit-if-no-ref/
pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 {
bias-pull-up;
drive-strength = <15>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 {
bias-pull-down;
drive-strength = <0>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 {
bias-pull-down;
drive-strength = <1>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 {
bias-pull-down;
drive-strength = <2>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 {
bias-pull-down;
drive-strength = <3>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 {
bias-pull-down;
drive-strength = <4>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 {
bias-pull-down;
drive-strength = <5>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 {
bias-pull-down;
drive-strength = <6>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 {
bias-pull-down;
drive-strength = <7>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 {
bias-pull-down;
drive-strength = <8>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 {
bias-pull-down;
drive-strength = <9>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 {
bias-pull-down;
drive-strength = <10>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 {
bias-pull-down;
drive-strength = <11>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 {
bias-pull-down;
drive-strength = <12>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 {
bias-pull-down;
drive-strength = <13>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 {
bias-pull-down;
drive-strength = <14>;
};
/omit-if-no-ref/
pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 {
bias-pull-down;
drive-strength = <15>;
};
/omit-if-no-ref/
pcfg_pull_up_smt: pcfg-pull-up-smt {
bias-pull-up;
input-schmitt-enable;
};
/omit-if-no-ref/
pcfg_pull_down_smt: pcfg-pull-down-smt {
bias-pull-down;
input-schmitt-enable;
};
/omit-if-no-ref/
pcfg_pull_none_smt: pcfg-pull-none-smt {
bias-disable;
input-schmitt-enable;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt {
bias-disable;
drive-strength = <0>;
input-schmitt-enable;
};
/omit-if-no-ref/
pcfg_output_high: pcfg-output-high {
output-high;
};
/omit-if-no-ref/
pcfg_output_low: pcfg-output-low {
output-low;
};
};

21
arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi
View file

@ -123,3 +123,24 @@
u-boot,dm-pre-reloc;
};
};
&sdmmc2 {
u-boot,dm-spl;
};
&sdmmc2_b4_pins_a {
u-boot,dm-spl;
pins1 {
u-boot,dm-spl;
};
pins2 {
u-boot,dm-spl;
};
};
&sdmmc2_d47_pins_d {
u-boot,dm-spl;
pins {
u-boot,dm-spl;
};
};

15
arch/arm/dts/stm32mp157c-odyssey-som.dtsi
View file

@ -264,14 +264,17 @@
&sdmmc2 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc2_b4_pins_a>;
pinctrl-1 = <&sdmmc2_b4_od_pins_a>;
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
broken-cd;
disable-wp;
pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_d>;
pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_d>;
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_d>;
non-removable;
no-sd;
no-sdio;
st,neg-edge;
bus-width = <4>;
bus-width = <8>;
vmmc-supply = <&v3v3>;
vqmmc-supply = <&vdd>;
mmc-ddr-3_3v;
status = "okay";
};

2
arch/arm/dts/zynq-7000.dtsi
View file

@ -95,7 +95,7 @@
};
};
amba: amba {
amba: axi {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
#address-cells = <1>;

2
arch/arm/dts/zynq-syzygy-hub.dts
View file

@ -16,6 +16,7 @@
ethernet0 = &gem0;
serial0 = &uart0;
mmc0 = &sdhci0;
nvmem0 = &eeprom;
i2c0 = &i2c1;
};
@ -27,7 +28,6 @@
chosen {
bootargs = "";
stdout-path = "serial0:115200n8";
xlnx,eeprom = &eeprom;
};
usb_phy0: phy0 {

6
arch/arm/dts/zynq-zc702.dts
View file

@ -68,6 +68,12 @@
ocm: sram@fffc0000 {
compatible = "mmio-sram";
reg = <0xfffc0000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xfffc0000 0x10000>;
ocm-sram@0 {
reg = <0x0 0x10000>;
};
};
};

7
arch/arm/dts/zynq-zc770-xm013.dts
View file

@ -68,13 +68,12 @@
num-cs = <4>;
is-decoded-cs = <0>;
eeprom: eeprom@2 {
at25,byte-len = <8192>;
at25,addr-mode = <2>;
at25,page-size = <32>;
compatible = "atmel,at25";
reg = <2>;
spi-max-frequency = <1000000>;
size = <8192>;
address-width = <16>;
pagesize = <32>;
};
};

4
arch/arm/dts/zynqmp-a2197-revA.dts
View file

@ -18,13 +18,14 @@
aliases {
i2c0 = &i2c0;
nvmem0 = &eeprom1;
nvmem1 = &eeprom0;
serial0 = &uart0;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
xlnx,eeprom = <&eeprom1 &eeprom0 &eeprom0>;
};
memory@0 {
@ -35,7 +36,6 @@
&uart0 { /* uart0 MIO38-39 */
status = "okay";
u-boot,dm-pre-reloc;
};
&i2c0 {

9
arch/arm/dts/zynqmp-clk-ccf.dtsi
View file

@ -2,7 +2,7 @@
/*
* Clock specification for Xilinx ZynqMP
*
* (C) Copyright 2017 - 2020, Xilinx, Inc.
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -67,13 +67,6 @@
#clock-cells = <0>;
clock-frequency = <27000000>;
};
dp_aclk: dp_aclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-accuracy = <100>;
};
};
&zynqmp_firmware {

4
arch/arm/dts/zynqmp-e-a2197-00-revA.dts
View file

@ -20,10 +20,10 @@
aliases {
ethernet0 = &gem0;
gpio0 = &gpio;
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci1;
nvmem0 = &eeprom;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &dcc;
@ -32,7 +32,6 @@
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
xlnx,eeprom = <&eeprom>;
};
memory@0 {
@ -124,7 +123,6 @@
&uart0 { /* uart0 MIO38-39 */
status = "okay";
u-boot,dm-pre-reloc;
};
&sdhci1 { /* sd1 MIO45-51 cd in place */

4
arch/arm/dts/zynqmp-g-a2197-00-revA.dts
View file

@ -19,9 +19,9 @@
aliases {
ethernet0 = &gem0;
gpio0 = &gpio;
i2c0 = &i2c0;
mmc0 = &sdhci0;
nvmem0 = &eeprom;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &dcc;
@ -31,7 +31,6 @@
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
xlnx,eeprom = <&eeprom>;
};
memory@0 {
@ -75,7 +74,6 @@
&uart0 { /* uart0 MIO38-39 */
status = "okay";
u-boot,dm-pre-reloc;
};
&gem0 { /* eth MDIO 76/77 */

5
arch/arm/dts/zynqmp-m-a2197-01-revA.dts
View file

@ -19,11 +19,11 @@
aliases {
ethernet0 = &gem0;
gpio0 = &gpio;
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
nvmem0 = &eeprom;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
@ -36,7 +36,6 @@
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
xlnx,eeprom = <&eeprom>;
};
memory@0 {
@ -94,12 +93,10 @@
&uart0 { /* uart0 MIO38-39 */
status = "okay";
u-boot,dm-pre-reloc;
};
&uart1 { /* uart1 MIO40-41 */
status = "okay";
u-boot,dm-pre-reloc;
};
&sdhci1 { /* sd1 MIO45-51 cd in place */

5
arch/arm/dts/zynqmp-m-a2197-02-revA.dts
View file

@ -19,11 +19,11 @@
aliases {
ethernet0 = &gem0;
gpio0 = &gpio;
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
nvmem0 = &eeprom;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
@ -36,7 +36,6 @@
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
xlnx,eeprom = <&eeprom>;
};
memory@0 {
@ -90,12 +89,10 @@
&uart0 { /* uart0 MIO38-39 */
status = "okay";
u-boot,dm-pre-reloc;
};
&uart1 { /* uart1 MIO40-41 */
status = "okay";
u-boot,dm-pre-reloc;
};
&sdhci1 { /* sd1 MIO45-51 cd in place */

5
arch/arm/dts/zynqmp-m-a2197-03-revA.dts
View file

@ -19,11 +19,11 @@
aliases {
ethernet0 = &gem0;
gpio0 = &gpio;
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
nvmem0 = &eeprom;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
@ -36,7 +36,6 @@
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
xlnx,eeprom = <&eeprom>;
};
memory@0 {
@ -90,12 +89,10 @@
&uart0 { /* uart0 MIO38-39 */
status = "okay";
u-boot,dm-pre-reloc;
};
&uart1 { /* uart1 MIO40-41 */
status = "okay";
u-boot,dm-pre-reloc;
};
&sdhci1 { /* sd1 MIO45-51 cd in place */

6
arch/arm/dts/zynqmp-p-a2197-00-revA.dts
View file

@ -20,11 +20,11 @@
aliases {
ethernet0 = &gem0;
gpio0 = &gpio;
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
nvmem0 = &eeprom;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
@ -36,8 +36,6 @@
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
xlnx,eeprom = <&eeprom>;
/* xlnx,fmc-eeprom = FIXME */
};
memory@0 {
@ -68,12 +66,10 @@
&uart0 { /* uart0 MIO38-39 */
status = "okay";
u-boot,dm-pre-reloc;
};
&uart1 { /* uart1 MIO40-41 */
status = "okay";
u-boot,dm-pre-reloc;
};
&sdhci1 { /* sd1 MIO45-51 cd in place */

624
arch/arm/dts/zynqmp-sck-kv-g-revA.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for KV260 revA Carrier Card
*
* (C) Copyright 2020, Xilinx, Inc.
* (C) Copyright 2020 - 2021, Xilinx, Inc.
*
* SD level shifter:
* "A" – A01 board un-modified (NXP)
@ -20,354 +20,316 @@
/dts-v1/;
/plugin/;
/{
&{/} {
compatible = "xlnx,zynqmp-sk-kv260-revA",
"xlnx,zynqmp-sk-kv260-revY",
"xlnx,zynqmp-sk-kv260-revZ",
"xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
};
fragment1 {
target = <&i2c1>; /* I2C_SCK C23/C24 - MIO from SOM */
&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
u14: ina260@40 { /* u14 */
compatible = "ti,ina260";
#io-channel-cells = <1>;
label = "ina260-u14";
reg = <0x40>;
};
/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
};
u14: ina260@40 { /* u14 */
compatible = "ti,ina260";
#io-channel-cells = <1>;
label = "ina260-u14";
reg = <0x40>;
};
/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
};
&amba {
ina260-u14 {
compatible = "iio-hwmon";
io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
};
fragment1a {
target = <&amba>;
__overlay__ {
ina260-u14 {
compatible = "iio-hwmon";
io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
};
si5332_0: si5332_0 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
si5332_1: si5332_1 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
si5332_2: si5332_2 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
si5332_3: si5332_3 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
si5332_4: si5332_4 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
si5332_5: si5332_5 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
si5332_0: si5332_0 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
si5332_1: si5332_1 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
si5332_2: si5332_2 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
si5332_3: si5332_3 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
si5332_4: si5332_4 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
si5332_5: si5332_5 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
/* DP/USB 3.0 and SATA */
fragment2 {
target = <&psgtr>;
__overlay__ {
status = "okay";
/* pcie, usb3, sata */
clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
clock-names = "ref0", "ref1", "ref2";
};
&psgtr {
status = "okay";
/* pcie, usb3, sata */
clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
clock-names = "ref0", "ref1", "ref2";
};
&sata {
status = "okay";
/* SATA OOB timing settings */
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&psgtr 3 PHY_TYPE_SATA 1 2>;
};
&zynqmp_dpsub {
status = "disabled";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
};
&zynqmp_dpdma {
status = "okay";
};
&usb0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
usbhub: usb5744 { /* u43 */
compatible = "microchip,usb5744";
reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
};
};
fragment3 {
target = <&sata>;
__overlay__ {
status = "okay";
/* SATA OOB timing settings */
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&psgtr 3 PHY_TYPE_SATA 1 2>;
};
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
maximum-speed = "super-speed";
};
fragment4 {
target = <&zynqmp_dpsub>;
__overlay__ {
status = "disabled";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
};
};
&sdhci1 { /* on CC with tuned parameters */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci1_default>;
/*
* SD 3.0 requires level shifter and this property
* should be removed if the board has level shifter and
* need to work in UHS mode
*/
no-1-8-v;
disable-wp;
xlnx,mio-bank = <1>;
};
fragment9 {
target = <&zynqmp_dpdma>;
__overlay__ {
status = "okay";
};
};
&gem3 { /* required by spec */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
fragment10 {
target = <&usb0>;
__overlay__ {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
usbhub: usb5744 { /* u43 */
compatible = "microchip,usb5744";
reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
};
};
};
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
reset-delay-us = <2>;
fragment11 {
target = <&dwc3_0>;
__overlay__ {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
maximum-speed = "super-speed";
};
};
fragment12 {
target = <&sdhci1>; /* on CC with tuned parameters */
__overlay__ {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci1_default>;
/*
* SD 3.0 requires level shifter and this property
* should be removed if the board has level shifter and
* need to work in UHS mode
*/
no-1-8-v;
disable-wp;
xlnx,mio-bank = <1>;
};
};
fragment13 {
target = <&gem3>; /* required by spec */
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
reset-delay-us = <2>;
phy0: ethernet-phy@1 {
#phy-cells = <1>;
reg = <1>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
};
};
};
};
fragment14 {
target = <&pinctrl0>; /* required by spec */
__overlay__ {
status = "okay";
pinctrl_uart1_default: uart1-default {
conf {
groups = "uart1_9_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO37";
bias-high-impedance;
};
conf-tx {
pins = "MIO36";
bias-disable;
};
mux {
groups = "uart1_9_grp";
function = "uart1";
};
};
pinctrl_i2c1_default: i2c1-default {
conf {
groups = "i2c1_6_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "i2c1_6_grp";
function = "i2c1";
};
};
pinctrl_i2c1_gpio: i2c1-gpio {
conf {
groups = "gpio0_24_grp", "gpio0_25_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "gpio0_24_grp", "gpio0_25_grp";
function = "gpio0";
};
};
pinctrl_gem3_default: gem3-default {
conf {
groups = "ethernet3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO70", "MIO72", "MIO74";
bias-high-impedance;
low-power-disable;
};
conf-bootstrap {
pins = "MIO71", "MIO73", "MIO75";
bias-disable;
low-power-disable;
};
conf-tx {
pins = "MIO64", "MIO65", "MIO66",
"MIO67", "MIO68", "MIO69";
bias-disable;
low-power-enable;
};
conf-mdio {
groups = "mdio3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
mux-mdio {
function = "mdio3";
groups = "mdio3_0_grp";
};
mux {
function = "ethernet3";
groups = "ethernet3_0_grp";
};
};
pinctrl_usb0_default: usb0-default {
conf {
groups = "usb0_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO52", "MIO53", "MIO55";
bias-high-impedance;
};
conf-tx {
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
};
mux {
groups = "usb0_0_grp";
function = "usb0";
};
};
pinctrl_sdhci1_default: sdhci1-default {
conf {
groups = "sdio1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
conf-cd {
groups = "sdio1_cd_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux-cd {
groups = "sdio1_cd_0_grp";
function = "sdio1_cd";
};
mux {
groups = "sdio1_0_grp";
function = "sdio1";
};
};
};
};
fragment15 {
target = <&uart1>;
__overlay__ {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
phy0: ethernet-phy@1 {
#phy-cells = <1>;
reg = <1>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
};
};
};
&pinctrl0 { /* required by spec */
status = "okay";
pinctrl_uart1_default: uart1-default {
conf {
groups = "uart1_9_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO37";
bias-high-impedance;
};
conf-tx {
pins = "MIO36";
bias-disable;
};
mux {
groups = "uart1_9_grp";
function = "uart1";
};
};
pinctrl_i2c1_default: i2c1-default {
conf {
groups = "i2c1_6_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "i2c1_6_grp";
function = "i2c1";
};
};
pinctrl_i2c1_gpio: i2c1-gpio {
conf {
groups = "gpio0_24_grp", "gpio0_25_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "gpio0_24_grp", "gpio0_25_grp";
function = "gpio0";
};
};
pinctrl_gem3_default: gem3-default {
conf {
groups = "ethernet3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO70", "MIO72", "MIO74";
bias-high-impedance;
low-power-disable;
};
conf-bootstrap {
pins = "MIO71", "MIO73", "MIO75";
bias-disable;
low-power-disable;
};
conf-tx {
pins = "MIO64", "MIO65", "MIO66",
"MIO67", "MIO68", "MIO69";
bias-disable;
low-power-enable;
};
conf-mdio {
groups = "mdio3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
mux-mdio {
function = "mdio3";
groups = "mdio3_0_grp";
};
mux {
function = "ethernet3";
groups = "ethernet3_0_grp";
};
};
pinctrl_usb0_default: usb0-default {
conf {
groups = "usb0_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO52", "MIO53", "MIO55";
bias-high-impedance;
};
conf-tx {
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
};
mux {
groups = "usb0_0_grp";
function = "usb0";
};
};
pinctrl_sdhci1_default: sdhci1-default {
conf {
groups = "sdio1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
conf-cd {
groups = "sdio1_cd_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux-cd {
groups = "sdio1_cd_0_grp";
function = "sdio1_cd";
};
mux {
groups = "sdio1_0_grp";
function = "sdio1";
};
};
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};

597
arch/arm/dts/zynqmp-sck-kv-g-revB.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for KV260 revA Carrier Card
*
* (C) Copyright 2020, Xilinx, Inc.
* (C) Copyright 2020 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -15,339 +15,304 @@
/dts-v1/;
/plugin/;
/{
&{/} {
compatible = "xlnx,zynqmp-sk-kv260-rev1",
"xlnx,zynqmp-sk-kv260-revB", "xlnx,zynqmp-sk-kv260-revA",
"xlnx,zynqmp-sk-kv260-revB",
"xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
};
fragment1 {
target = <&i2c1>; /* I2C_SCK C23/C24 - MIO from SOM */
&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
u14: ina260@40 { /* u14 */
compatible = "ti,ina260";
#io-channel-cells = <1>;
label = "ina260-u14";
reg = <0x40>;
};
usbhub: usb5744@2d { /* u43 */
compatible = "microchip,usb5744";
reg = <0x2d>;
reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
};
/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
};
u14: ina260@40 { /* u14 */
compatible = "ti,ina260";
#io-channel-cells = <1>;
label = "ina260-u14";
reg = <0x40>;
};
usbhub: usb5744@2d { /* u43 */
compatible = "microchip,usb5744";
reg = <0x2d>;
reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
};
/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
};
&amba {
ina260-u14 {
compatible = "iio-hwmon";
io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
};
fragment1a {
target = <&amba>;
__overlay__ {
ina260-u14 {
compatible = "iio-hwmon";
io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
};
si5332_0: si5332_0 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
si5332_1: si5332_1 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
si5332_2: si5332_2 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
si5332_3: si5332_3 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
si5332_4: si5332_4 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
si5332_5: si5332_5 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
si5332_0: si5332_0 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
si5332_1: si5332_1 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
si5332_2: si5332_2 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
si5332_3: si5332_3 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
si5332_4: si5332_4 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
si5332_5: si5332_5 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
/* DP/USB 3.0 */
fragment2 {
target = <&psgtr>;
__overlay__ {
status = "okay";
/* pcie, usb3, sata */
clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
clock-names = "ref0", "ref1", "ref2";
};
};
&psgtr {
status = "okay";
/* pcie, usb3, sata */
clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
clock-names = "ref0", "ref1", "ref2";
};
fragment4 {
target = <&zynqmp_dpsub>;
__overlay__ {
status = "disabled";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
};
};
&zynqmp_dpsub {
status = "disabled";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
};
fragment9 {
target = <&zynqmp_dpdma>;
__overlay__ {
status = "okay";
};
};
&zynqmp_dpdma {
status = "okay";
};
fragment10 {
target = <&usb0>;
__overlay__ {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
};
};
&usb0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
};
fragment11 {
target = <&dwc3_0>;
__overlay__ {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
maximum-speed = "super-speed";
};
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
maximum-speed = "super-speed";
};
fragment12 {
target = <&sdhci1>; /* on CC with tuned parameters */
__overlay__ {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci1_default>;
/*
* SD 3.0 requires level shifter and this property
* should be removed if the board has level shifter and
* need to work in UHS mode
*/
no-1-8-v;
disable-wp;
xlnx,mio-bank = <1>;
clk-phase-sd-hs = <126>, <60>;
clk-phase-uhs-sdr25 = <120>, <60>;
clk-phase-uhs-ddr50 = <126>, <48>;
};
};
&sdhci1 { /* on CC with tuned parameters */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci1_default>;
/*
* SD 3.0 requires level shifter and this property
* should be removed if the board has level shifter and
* need to work in UHS mode
*/
no-1-8-v;
disable-wp;
xlnx,mio-bank = <1>;
clk-phase-sd-hs = <126>, <60>;
clk-phase-uhs-sdr25 = <120>, <60>;
clk-phase-uhs-ddr50 = <126>, <48>;
};
fragment13 {
target = <&gem3>; /* required by spec */
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
&gem3 { /* required by spec */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
reset-delay-us = <2>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
reset-delay-us = <2>;
phy0: ethernet-phy@1 {
#phy-cells = <1>;
reg = <1>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
};
};
};
};
fragment14 {
target = <&pinctrl0>; /* required by spec */
__overlay__ {
status = "okay";
pinctrl_uart1_default: uart1-default {
conf {
groups = "uart1_9_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO37";
bias-high-impedance;
};
conf-tx {
pins = "MIO36";
bias-disable;
};
mux {
groups = "uart1_9_grp";
function = "uart1";
};
};
pinctrl_i2c1_default: i2c1-default {
conf {
groups = "i2c1_6_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "i2c1_6_grp";
function = "i2c1";
};
};
pinctrl_i2c1_gpio: i2c1-gpio {
conf {
groups = "gpio0_24_grp", "gpio0_25_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "gpio0_24_grp", "gpio0_25_grp";
function = "gpio0";
};
};
pinctrl_gem3_default: gem3-default {
conf {
groups = "ethernet3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO70", "MIO72", "MIO74";
bias-high-impedance;
low-power-disable;
};
conf-bootstrap {
pins = "MIO71", "MIO73", "MIO75";
bias-disable;
low-power-disable;
};
conf-tx {
pins = "MIO64", "MIO65", "MIO66",
"MIO67", "MIO68", "MIO69";
bias-disable;
low-power-enable;
};
conf-mdio {
groups = "mdio3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
mux-mdio {
function = "mdio3";
groups = "mdio3_0_grp";
};
mux {
function = "ethernet3";
groups = "ethernet3_0_grp";
};
};
pinctrl_usb0_default: usb0-default {
conf {
groups = "usb0_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO52", "MIO53", "MIO55";
bias-high-impedance;
};
conf-tx {
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
};
mux {
groups = "usb0_0_grp";
function = "usb0";
};
};
pinctrl_sdhci1_default: sdhci1-default {
conf {
groups = "sdio1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
conf-cd {
groups = "sdio1_cd_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux-cd {
groups = "sdio1_cd_0_grp";
function = "sdio1_cd";
};
mux {
groups = "sdio1_0_grp";
function = "sdio1";
};
};
};
};
fragment15 {
target = <&uart1>;
__overlay__ {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
phy0: ethernet-phy@1 {
#phy-cells = <1>;
reg = <1>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,dp83867-rxctrl-strap-quirk;
};
};
};
&pinctrl0 { /* required by spec */
status = "okay";
pinctrl_uart1_default: uart1-default {
conf {
groups = "uart1_9_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
drive-strength = <12>;
};
conf-rx {
pins = "MIO37";
bias-high-impedance;
};
conf-tx {
pins = "MIO36";
bias-disable;
};
mux {
groups = "uart1_9_grp";
function = "uart1";
};
};
pinctrl_i2c1_default: i2c1-default {
conf {
groups = "i2c1_6_grp";
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "i2c1_6_grp";
function = "i2c1";
};
};
pinctrl_i2c1_gpio: i2c1-gpio {
conf {
groups = "gpio0_24_grp", "gpio0_25_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux {
groups = "gpio0_24_grp", "gpio0_25_grp";
function = "gpio0";
};
};
pinctrl_gem3_default: gem3-default {
conf {
groups = "ethernet3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO70", "MIO72", "MIO74";
bias-high-impedance;
low-power-disable;
};
conf-bootstrap {
pins = "MIO71", "MIO73", "MIO75";
bias-disable;
low-power-disable;
};
conf-tx {
pins = "MIO64", "MIO65", "MIO66",
"MIO67", "MIO68", "MIO69";
bias-disable;
low-power-enable;
};
conf-mdio {
groups = "mdio3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
mux-mdio {
function = "mdio3";
groups = "mdio3_0_grp";
};
mux {
function = "ethernet3";
groups = "ethernet3_0_grp";
};
};
pinctrl_usb0_default: usb0-default {
conf {
groups = "usb0_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO52", "MIO53", "MIO55";
bias-high-impedance;
};
conf-tx {
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
};
mux {
groups = "usb0_0_grp";
function = "usb0";
};
};
pinctrl_sdhci1_default: sdhci1-default {
conf {
groups = "sdio1_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
conf-cd {
groups = "sdio1_cd_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <SLEW_RATE_SLOW>;
power-source = <IO_STANDARD_LVCMOS18>;
};
mux-cd {
groups = "sdio1_cd_0_grp";
function = "sdio1_cd";
};
mux {
groups = "sdio1_0_grp";
function = "sdio1";
};
};
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};

2
arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP K26/KV260 SD wiring
*
* (C) Copyright 2020, Xilinx, Inc.
* (C) Copyright 2020 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/

7
arch/arm/dts/zynqmp-sm-k26-revA.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP SM-K26 rev1/B/A
*
* (C) Copyright 2020, Xilinx, Inc.
* (C) Copyright 2020 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -22,11 +22,12 @@
"xlnx,zynqmp";
aliases {
gpio0 = &gpio;
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
nvmem0 = &eeprom;
nvmem1 = &eeprom_cc;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
@ -36,8 +37,6 @@
spi2 = &spi1;
usb0 = &usb0;
usb1 = &usb1;
nvmem0 = &eeprom;
nvmem1 = &eeprom_cc;
};
chosen {

2
arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP Z2-VSOM
*
* (C) Copyright 2020, Xilinx, Inc.
* (C) Copyright 2020 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/

2
arch/arm/dts/zynqmp-smk-k26-revA.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP SMK-K26 rev1/B/A
*
* (C) Copyright 2020, Xilinx, Inc.
* (C) Copyright 2020 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/

1
arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts
View file

@ -19,7 +19,6 @@
"topic,miamimp", "xlnx,zynqmp";
aliases {
gpio0 = &gpio;
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci0;

3
arch/arm/dts/zynqmp-zc1232-revA.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZC1232
*
* (C) Copyright 2017 - 2020, Xilinx, Inc.
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -11,7 +11,6 @@
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP ZC1232 RevA";

22
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm015-dc1
*
* (C) Copyright 2015 - 2020, Xilinx, Inc.
* (C) Copyright 2015 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -21,7 +21,6 @@
aliases {
ethernet0 = &gem3;
gpio0 = &gpio;
i2c0 = &i2c1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
@ -60,13 +59,6 @@
};
};
&psgtr {
status = "okay";
/* dp, usb3, sata */
clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>;
clock-names = "ref1", "ref2", "ref3";
};
&fpd_dma_chan1 {
status = "okay";
};
@ -345,6 +337,13 @@
};
};
&psgtr {
status = "okay";
/* dp, usb3, sata */
clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>;
clock-names = "ref1", "ref2", "ref3";
};
&qspi {
status = "okay";
flash@0 {
@ -433,6 +432,7 @@
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
maximum-speed = "super-speed";
};
&zynqmp_dpdma {
@ -441,5 +441,7 @@
&zynqmp_dpsub {
status = "okay";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 0>,
<&psgtr 0 PHY_TYPE_DP 1 1>;
};

7
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm016-dc2
*
* (C) Copyright 2015 - 2020, Xilinx, Inc.
* (C) Copyright 2015 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -19,10 +19,7 @@
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
aliases {
can0 = &can0;
can1 = &can1;
ethernet0 = &gem2;
gpio0 = &gpio;
i2c0 = &i2c0;
rtc0 = &rtc;
serial0 = &uart0;
@ -538,6 +535,8 @@
&dwc3_1 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
};
&uart0 {

43
arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm017-dc3
*
* (C) Copyright 2016 - 2020, Xilinx, Inc.
* (C) Copyright 2016 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -11,6 +11,7 @@
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/phy/phy.h>
/ {
model = "ZynqMP zc1751-xm017-dc3 RevA";
@ -18,7 +19,6 @@
aliases {
ethernet0 = &gem0;
gpio0 = &gpio;
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci1;
@ -38,6 +38,18 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
clock_si5338_2: clk26 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
clock_si5338_3: clk125 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
};
&fpd_dma_chan1 {
@ -167,6 +179,13 @@
};
};
&psgtr {
status = "okay";
/* usb3, sata */
clocks = <&clock_si5338_2>, <&clock_si5338_3>;
clock-names = "ref2", "ref3";
};
&rtc {
status = "okay";
};
@ -182,6 +201,8 @@
ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&psgtr 2 PHY_TYPE_SATA 0 3>;
};
&sdhci1 { /* emmc with some settings */
@ -200,11 +221,27 @@
&usb0 {
status = "okay";
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&psgtr 0 PHY_TYPE_USB3 0 2>;
maximum-speed = "super-speed";
};
/* ULPI SMSC USB3320 */
&usb1 {
status = "okay";
dr_mode = "host";
};
&dwc3_1 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
maximum-speed = "super-speed";
};

21
arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm018-dc4
*
* (C) Copyright 2015 - 2020, Xilinx, Inc.
* (C) Copyright 2015 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -17,13 +17,10 @@
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
aliases {
can0 = &can0;
can1 = &can1;
ethernet0 = &gem0;
ethernet1 = &gem1;
ethernet2 = &gem2;
ethernet3 = &gem3;
gpio0 = &gpio;
i2c0 = &i2c0;
i2c1 = &i2c1;
rtc0 = &rtc;
@ -115,14 +112,6 @@
status = "okay";
};
&zynqmp_dpsub {
status = "okay";
};
&zynqmp_dpdma {
status = "okay";
};
&gem0 {
status = "okay";
phy-mode = "rgmii-id";
@ -221,3 +210,11 @@
&watchdog0 {
status = "okay";
};
&zynqmp_dpdma {
status = "okay";
};
&zynqmp_dpsub {
status = "okay";
};

3
arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm019-dc5
*
* (C) Copyright 2015 - 2020, Xilinx, Inc.
* (C) Copyright 2015 - 2021, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
* Michal Simek <michal.simek@xilinx.com>
@ -21,7 +21,6 @@
aliases {
ethernet0 = &gem1;
gpio0 = &gpio;
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci0;

11
arch/arm/dts/zynqmp-zcu100-revC.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU100 revC
*
* (C) Copyright 2016 - 2020, Xilinx, Inc.
* (C) Copyright 2016 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Nathalie Chan King Choy
@ -23,7 +23,6 @@
compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp";
aliases {
gpio0 = &gpio;
i2c0 = &i2c1;
rtc0 = &rtc;
serial0 = &uart1;
@ -132,13 +131,13 @@
io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
};
si5335a_0: clk26 {
si5335_0: si5335_0 { /* clk0_usb - u23 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
si5335a_1: clk27 {
si5335_1: si5335_1 { /* clk1_dp - u23 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
@ -485,8 +484,8 @@
&psgtr {
status = "okay";
/* usb3, dps */
clocks = <&si5335a_0>, <&si5335a_1>;
/* usb3, dp */
clocks = <&si5335_0>, <&si5335_1>;
clock-names = "ref0", "ref1";
};

15
arch/arm/dts/zynqmp-zcu102-revA.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU102 RevA
*
* (C) Copyright 2015 - 2020, Xilinx, Inc.
* (C) Copyright 2015 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -22,10 +22,10 @@
aliases {
ethernet0 = &gem3;
gpio0 = &gpio;
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci1;
nvmem0 = &eeprom;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
@ -37,7 +37,6 @@
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
xlnx,eeprom = &eeprom;
};
memory@0 {
@ -605,15 +604,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
si5328: clock-generator@69 {/* SI5328 - u20 */
compatible = "silabs,si5328";
reg = <0x69>;
/*
* Chip has interrupt present connected to PL
* interrupt-parent = <&>;
* interrupts = <>;
*/
};
/* SI5328 - u20 */
};
/* 5 - 7 unconnected */
};

23
arch/arm/dts/zynqmp-zcu104-revA.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU104
*
* (C) Copyright 2017 - 2020, Xilinx, Inc.
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -21,9 +21,9 @@
aliases {
ethernet0 = &gem3;
gpio0 = &gpio;
i2c0 = &i2c1;
mmc0 = &sdhci1;
nvmem0 = &eeprom;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
@ -165,10 +165,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
compatible = "idt,8t49n287";
reg = <0x6c>;
};
/* 8T49N287 - u182 */
};
i2c@2 {
@ -423,6 +420,13 @@
};
};
&psgtr {
status = "okay";
/* nc, sata, usb3, dp */
clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
clock-names = "ref1", "ref2", "ref3";
};
&qspi {
status = "okay";
flash@0 {
@ -452,13 +456,6 @@
};
};
&psgtr {
status = "okay";
/* nc, sata, usb3, dp */
clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
clock-names = "ref1", "ref2", "ref3";
};
&rtc {
status = "okay";
};

24
arch/arm/dts/zynqmp-zcu104-revC.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU104
*
* (C) Copyright 2017 - 2020, Xilinx, Inc.
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -21,9 +21,9 @@
aliases {
ethernet0 = &gem3;
gpio0 = &gpio;
i2c0 = &i2c1;
mmc0 = &sdhci1;
nvmem0 = &eeprom;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
@ -35,7 +35,6 @@
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
xlnx,eeprom = &eeprom;
};
memory@0 {
@ -190,10 +189,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
compatible = "idt,8t49n287";
reg = <0x6c>;
};
/* 8T49N287 - u182 */
};
i2c@2 {
@ -436,6 +432,13 @@
};
};
&psgtr {
status = "okay";
/* nc, sata, usb3, dp */
clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
clock-names = "ref1", "ref2", "ref3";
};
&qspi {
status = "okay";
flash@0 {
@ -469,13 +472,6 @@
status = "okay";
};
&psgtr {
status = "okay";
/* nc, sata, usb3, dp */
clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
clock-names = "ref1", "ref2", "ref3";
};
&sata {
status = "okay";
/* SATA OOB timing settings */

49
arch/arm/dts/zynqmp-zcu106-revA.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU106
*
* (C) Copyright 2016 - 2020, Xilinx, Inc.
* (C) Copyright 2016 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -22,10 +22,10 @@
aliases {
ethernet0 = &gem3;
gpio0 = &gpio;
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci1;
nvmem0 = &eeprom;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
@ -37,7 +37,6 @@
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
xlnx,eeprom = &eeprom;
};
memory@0 {
@ -163,18 +162,6 @@
status = "okay";
};
&zynqmp_dpdma {
status = "okay";
};
&zynqmp_dpsub {
status = "okay";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
<&psgtr 0 PHY_TYPE_DP 1 3>;
};
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
};
@ -606,25 +593,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
si5328: clock-generator@69 {/* SI5328 - u20 */
reg = <0x69>;
/*
* Chip has interrupt present connected to PL
* interrupt-parent = <&>;
* interrupts = <>;
*/
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
clocks = <&refhdmi>;
clock-names = "xtal";
clock-output-names = "si5328";
si5328_clk: clk0@0 {
reg = <0>;
clock-frequency = <27000000>;
};
};
/* SI5328 - u20 */
};
i2c@5 {
#address-cells = <1>;
@ -1051,8 +1020,20 @@
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
maximum-speed = "super-speed";
};
&watchdog0 {
status = "okay";
};
&zynqmp_dpdma {
status = "okay";
};
&zynqmp_dpsub {
status = "okay";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
<&psgtr 0 PHY_TYPE_DP 1 3>;
};

15
arch/arm/dts/zynqmp-zcu111-revA.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU111
*
* (C) Copyright 2017 - 2020, Xilinx, Inc.
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -22,10 +22,10 @@
aliases {
ethernet0 = &gem3;
gpio0 = &gpio;
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci1;
nvmem0 = &eeprom;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &dcc;
@ -36,7 +36,6 @@
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
xlnx,eeprom = &eeprom;
};
memory@0 {
@ -481,10 +480,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
si5382: clock-generator@69 { /* SI5382 - u48 */
compatible = "silabs,si5382";
reg = <0x69>;
};
/* SI5382 - u48 */
};
i2c@5 {
#address-cells = <1>;
@ -775,8 +771,8 @@
&psgtr {
status = "okay";
/* nc, sata, usb3, dp */
clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
/* nc, dp, usb3, sata */
clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>;
clock-names = "ref1", "ref2", "ref3";
};
@ -861,6 +857,7 @@
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
maximum-speed = "super-speed";
};
&zynqmp_dpdma {

6
arch/arm/dts/zynqmp-zcu1275-revA.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU1275
*
* (C) Copyright 2017 - 2020, Xilinx, Inc.
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
@ -39,6 +39,10 @@
status = "okay";
};
&gpio {
status = "okay";
};
&qspi {
status = "okay";
flash@0 {

6
arch/arm/dts/zynqmp-zcu1275-revB.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU1275 RevB
*
* (C) Copyright 2018 - 2020, Xilinx, Inc.
* (C) Copyright 2018 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
@ -64,6 +64,10 @@
};
};
&gpio {
status = "okay";
};
&qspi {
status = "okay";
flash@0 {

6
arch/arm/dts/zynqmp-zcu1285-revA.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU1285 RevA
*
* (C) Copyright 2018 - 2020, Xilinx, Inc.
* (C) Copyright 2018 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
@ -245,6 +245,10 @@
};
};
&gpio {
status = "okay";
};
&qspi {
status = "okay";
flash@0 {

12
arch/arm/dts/zynqmp-zcu208-revA.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU208
*
* (C) Copyright 2017 - 2020, Xilinx, Inc.
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -22,10 +22,10 @@
aliases {
ethernet0 = &gem3;
gpio0 = &gpio;
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci1;
nvmem0 = &eeprom;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &dcc;
@ -36,7 +36,6 @@
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
xlnx,eeprom = &eeprom;
};
memory@0 {
@ -651,9 +650,9 @@
&psgtr {
status = "okay";
/* pcie, sata, usb3, dp */
clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
clock-names = "ref0", "ref1", "ref2", "ref3";
/* nc, nc, usb3, sata */
clocks = <&si5341 0 2>, <&si5341 0 3>;
clock-names = "ref2", "ref3";
};
&rtc {
@ -701,4 +700,5 @@
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
maximum-speed = "super-speed";
};

12
arch/arm/dts/zynqmp-zcu216-revA.dts
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU216
*
* (C) Copyright 2017 - 2020, Xilinx, Inc.
* (C) Copyright 2017 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -22,10 +22,10 @@
aliases {
ethernet0 = &gem3;
gpio0 = &gpio;
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci1;
nvmem0 = &eeprom;
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &dcc;
@ -36,7 +36,6 @@
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
xlnx,eeprom = <&eeprom>;
};
memory@0 {
@ -132,9 +131,9 @@
&psgtr {
status = "okay";
/* pcie, sata, usb3, dp */
clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
clock-names = "ref0", "ref1", "ref2", "ref3";
/* nc, nc, usb3, sata */
clocks = <&si5341 0 2>, <&si5341 0 3>;
clock-names = "ref2", "ref3";
};
&dcc {
@ -705,4 +704,5 @@
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
maximum-speed = "super-speed";
};

38
arch/arm/dts/zynqmp.dtsi
View file

@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP
*
* (C) Copyright 2014 - 2020, Xilinx, Inc.
* (C) Copyright 2014 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*
@ -100,7 +100,7 @@
};
};
zynqmp_ipi {
zynqmp_ipi: zynqmp_ipi {
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-ipi-mailbox";
interrupt-parent = <&gic>;
@ -246,6 +246,7 @@
cci: cci@fd6e0000 {
compatible = "arm,cci-400";
status = "disabled";
reg = <0x0 0xfd6e0000 0x0 0x9000>;
ranges = <0x0 0x0 0xfd6e0000 0x10000>;
#address-cells = <1>;
@ -647,6 +648,8 @@
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
#stream-id-cells = <1>;
iommus = <&smmu 0x4d0>;
power-domains = <&zynqmp_firmware PD_PCIE>;
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
@ -688,7 +691,7 @@
interrupt-parent = <&gic>;
interrupts = <0 26 4>, <0 27 4>;
interrupt-names = "alarm", "sec";
calibration = <0x8000>;
calibration = <0x7FFF>;
};
sata: ahci@fd0c0000 {
@ -698,6 +701,7 @@
interrupt-parent = <&gic>;
interrupts = <0 133 4>;
power-domains = <&zynqmp_firmware PD_SATA>;
resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
#stream-id-cells = <4>;
iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
<&smmu 0x4c2>, <&smmu 0x4c3>;
@ -715,8 +719,6 @@
xlnx,device_id = <0>;
#stream-id-cells = <1>;
iommus = <&smmu 0x870>;
nvmem-cells = <&soc_revision>;
nvmem-cell-names = "soc_revision";
#clock-cells = <1>;
clock-output-names = "clk_out_sd0", "clk_in_sd0";
power-domains = <&zynqmp_firmware PD_SD_0>;
@ -733,8 +735,6 @@
xlnx,device_id = <1>;
#stream-id-cells = <1>;
iommus = <&smmu 0x871>;
nvmem-cells = <&soc_revision>;
nvmem-cell-names = "soc_revision";
#clock-cells = <1>;
clock-output-names = "clk_out_sd1", "clk_in_sd1";
power-domains = <&zynqmp_firmware PD_SD_1>;
@ -848,20 +848,26 @@
reg = <0x0 0xff9d0000 0x0 0x100>;
clock-names = "bus_clk", "ref_clk";
power-domains = <&zynqmp_firmware PD_USB_0>;
resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
<&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
<&zynqmp_reset ZYNQMP_RESET_USB0_APB>;
reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
ranges;
nvmem-cells = <&soc_revision>;
nvmem-cell-names = "soc_revision";
dwc3_0: dwc3@fe200000 {
compatible = "snps,dwc3";
status = "disabled";
reg = <0x0 0xfe200000 0x0 0x40000>;
interrupt-parent = <&gic>;
interrupts = <0 65 4>, <0 69 4>;
interrupt-names = "dwc_usb3", "otg", "hiber";
interrupts = <0 65 4>, <0 69 4>, <0 75 4>;
#stream-id-cells = <1>;
iommus = <&smmu 0x860>;
snps,quirk-frame-length-adjustment = <0x20>;
snps,refclk_fladj;
snps,enable_guctl1_resume_quirk;
snps,enable_guctl1_ipd_quirk;
snps,xhci-stream-quirk;
/* dma-coherent; */
};
};
@ -874,20 +880,26 @@
reg = <0x0 0xff9e0000 0x0 0x100>;
clock-names = "bus_clk", "ref_clk";
power-domains = <&zynqmp_firmware PD_USB_1>;
resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
<&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
<&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
ranges;
nvmem-cells = <&soc_revision>;
nvmem-cell-names = "soc_revision";
dwc3_1: dwc3@fe300000 {
compatible = "snps,dwc3";
status = "disabled";
reg = <0x0 0xfe300000 0x0 0x40000>;
interrupt-parent = <&gic>;
interrupts = <0 70 4>, <0 74 4>;
interrupt-names = "dwc_usb3", "otg", "hiber";
interrupts = <0 70 4>, <0 74 4>, <0 76 4>;
#stream-id-cells = <1>;
iommus = <&smmu 0x861>;
snps,quirk-frame-length-adjustment = <0x20>;
snps,refclk_fladj;
snps,enable_guctl1_resume_quirk;
snps,enable_guctl1_ipd_quirk;
snps,xhci-stream-quirk;
/* dma-coherent; */
};
};

11
arch/arm/include/asm/arch-rk3568/boot0.h Normal file
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@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
*/
#ifndef __ASM_ARCH_BOOT0_H__
#define __ASM_ARCH_BOOT0_H__
#include <asm/arch-rockchip/boot0.h>
#endif

11
arch/arm/include/asm/arch-rk3568/gpio.h Normal file
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@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
*/
#ifndef __ASM_ARCH_GPIO_H__
#define __ASM_ARCH_GPIO_H__
#include <asm/arch-rockchip/gpio.h>
#endif

504
arch/arm/include/asm/arch-rockchip/cru_rk3568.h Normal file
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@ -0,0 +1,504 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
* Author: Elaine Zhang <zhangqing@rock-chips.com>
*/
#ifndef _ASM_ARCH_CRU_RK3568_H
#define _ASM_ARCH_CRU_RK3568_H
#define MHz 1000000
#define KHz 1000
#define OSC_HZ (24 * MHz)
#define APLL_HZ (816 * MHz)
#define GPLL_HZ (1188 * MHz)
#define CPLL_HZ (1000 * MHz)
#define PPLL_HZ (100 * MHz)
/* RK3568 pll id */
enum rk3568_pll_id {
APLL,
DPLL,
CPLL,
GPLL,
NPLL,
VPLL,
PPLL,
HPLL,
PLL_COUNT,
};
struct rk3568_clk_info {
unsigned long id;
char *name;
bool is_cru;
};
/* Private data for the clock driver - used by rockchip_get_cru() */
struct rk3568_pmuclk_priv {
struct rk3568_pmucru *pmucru;
ulong ppll_hz;
ulong hpll_hz;
};
struct rk3568_clk_priv {
struct rk3568_cru *cru;
struct rk3568_grf *grf;
ulong ppll_hz;
ulong hpll_hz;
ulong gpll_hz;
ulong cpll_hz;
ulong npll_hz;
ulong vpll_hz;
ulong armclk_hz;
ulong armclk_enter_hz;
ulong armclk_init_hz;
bool sync_kernel;
bool set_armclk_rate;
};
struct rk3568_pll {
unsigned int con0;
unsigned int con1;
unsigned int con2;
unsigned int con3;
unsigned int con4;
unsigned int reserved0[3];
};
struct rk3568_pmucru {
struct rk3568_pll pll[2];/* Address Offset: 0x0000 */
unsigned int reserved0[16];/* Address Offset: 0x0040 */
unsigned int mode_con00;/* Address Offset: 0x0080 */
unsigned int reserved1[31];/* Address Offset: 0x0084 */
unsigned int pmu_clksel_con[10];/* Address Offset: 0x0100 */
unsigned int reserved2[22];/* Address Offset: 0x0128 */
unsigned int pmu_clkgate_con[3];/* Address Offset: 0x0180 */
unsigned int reserved3[29];/* Address Offset: 0x018C */
unsigned int pmu_softrst_con[1];/* Address Offset: 0x0200 */
};
check_member(rk3568_pmucru, mode_con00, 0x80);
check_member(rk3568_pmucru, pmu_softrst_con[0], 0x200);
struct rk3568_cru {
struct rk3568_pll pll[6];
unsigned int mode_con00;/* Address Offset: 0x00C0 */
unsigned int misc_con[3];/* Address Offset: 0x00C4 */
unsigned int glb_cnt_th;/* Address Offset: 0x00D0 */
unsigned int glb_srst_fst;/* Address Offset: 0x00D4 */
unsigned int glb_srsr_snd; /* Address Offset: 0x00D8 */
unsigned int glb_rst_con;/* Address Offset: 0x00DC */
unsigned int glb_rst_st;/* Address Offset: 0x00E0 */
unsigned int reserved0[7];/* Address Offset: 0x00E4 */
unsigned int clksel_con[85]; /* Address Offset: 0x0100 */
unsigned int reserved1[43];/* Address Offset: 0x0254 */
unsigned int clkgate_con[36];/* Address Offset: 0x0300 */
unsigned int reserved2[28]; /* Address Offset: 0x0390 */
unsigned int softrst_con[30];/* Address Offset: 0x0400 */
unsigned int reserved3[2];/* Address Offset: 0x0478 */
unsigned int ssgtbl[32];/* Address Offset: 0x0480 */
unsigned int reserved4[32];/* Address Offset: 0x0500 */
unsigned int sdmmc0_con[2];/* Address Offset: 0x0580 */
unsigned int sdmmc1_con[2];/* Address Offset: 0x058C */
unsigned int sdmmc2_con[2];/* Address Offset: 0x0590 */
unsigned int emmc_con[2];/* Address Offset: 0x0598 */
};
check_member(rk3568_cru, mode_con00, 0xc0);
check_member(rk3568_cru, softrst_con[0], 0x400);
struct pll_rate_table {
unsigned long rate;
unsigned int fbdiv;
unsigned int postdiv1;
unsigned int refdiv;
unsigned int postdiv2;
unsigned int dsmpd;
unsigned int frac;
};
#define RK3568_PMU_MODE 0x80
#define RK3568_PMU_PLL_CON(x) ((x) * 0x4)
#define RK3568_PLL_CON(x) ((x) * 0x4)
#define RK3568_MODE_CON 0xc0
enum {
/* CRU_PMU_CLK_SEL0_CON */
RTC32K_SEL_SHIFT = 6,
RTC32K_SEL_MASK = 0x3 << RTC32K_SEL_SHIFT,
RTC32K_SEL_PMUPVTM = 0,
RTC32K_SEL_OSC1_32K,
RTC32K_SEL_OSC0_DIV32K,
/* CRU_PMU_CLK_SEL1_CON */
RTC32K_FRAC_NUMERATOR_SHIFT = 16,
RTC32K_FRAC_NUMERATOR_MASK = 0xffff << 16,
RTC32K_FRAC_DENOMINATOR_SHIFT = 0,
RTC32K_FRAC_DENOMINATOR_MASK = 0xffff,
/* CRU_PMU_CLK_SEL2_CON */
PCLK_PDPMU_SEL_SHIFT = 15,
PCLK_PDPMU_SEL_MASK = 1 << PCLK_PDPMU_SEL_SHIFT,
PCLK_PDPMU_SEL_PPLL = 0,
PCLK_PDPMU_SEL_GPLL,
PCLK_PDPMU_DIV_SHIFT = 0,
PCLK_PDPMU_DIV_MASK = 0x1f,
/* CRU_PMU_CLK_SEL3_CON */
CLK_I2C0_DIV_SHIFT = 0,
CLK_I2C0_DIV_MASK = 0x7f,
/* CRU_PMU_CLK_SEL6_CON */
CLK_PWM0_SEL_SHIFT = 7,
CLK_PWM0_SEL_MASK = 1 << CLK_PWM0_SEL_SHIFT,
CLK_PWM0_SEL_XIN24M = 0,
CLK_PWM0_SEL_PPLL,
CLK_PWM0_DIV_SHIFT = 0,
CLK_PWM0_DIV_MASK = 0x7f,
/* CRU_CLK_SEL0_CON */
CLK_CORE_PRE_SEL_SHIFT = 7,
CLK_CORE_PRE_SEL_MASK = 1 << CLK_CORE_PRE_SEL_SHIFT,
CLK_CORE_PRE_SEL_SRC = 0,
CLK_CORE_PRE_SEL_APLL,
/* CRU_CLK_SEL2_CON */
SCLK_CORE_PRE_SEL_SHIFT = 15,
SCLK_CORE_PRE_SEL_MASK = 1 << SCLK_CORE_PRE_SEL_SHIFT,
SCLK_CORE_PRE_SEL_SRC = 0,
SCLK_CORE_PRE_SEL_NPLL,
SCLK_CORE_SRC_SEL_SHIFT = 8,
SCLK_CORE_SRC_SEL_MASK = 3 << SCLK_CORE_SRC_SEL_SHIFT,
SCLK_CORE_SRC_SEL_APLL = 0,
SCLK_CORE_SRC_SEL_GPLL,
SCLK_CORE_SRC_SEL_NPLL,
SCLK_CORE_SRC_DIV_SHIFT = 0,
SCLK_CORE_SRC_DIV_MASK = 0x1f << SCLK_CORE_SRC_DIV_SHIFT,
/* CRU_CLK_SEL3_CON */
GICCLK_CORE_DIV_SHIFT = 8,
GICCLK_CORE_DIV_MASK = 0x1f << GICCLK_CORE_DIV_SHIFT,
ATCLK_CORE_DIV_SHIFT = 0,
ATCLK_CORE_DIV_MASK = 0x1f << ATCLK_CORE_DIV_SHIFT,
/* CRU_CLK_SEL4_CON */
PERIPHCLK_CORE_PRE_DIV_SHIFT = 8,
PERIPHCLK_CORE_PRE_DIV_MASK = 0x1f << PERIPHCLK_CORE_PRE_DIV_SHIFT,
PCLK_CORE_PRE_DIV_SHIFT = 0,
PCLK_CORE_PRE_DIV_MASK = 0x1f << PCLK_CORE_PRE_DIV_SHIFT,
/* CRU_CLK_SEL5_CON */
ACLK_CORE_NIU2BUS_SEL_SHIFT = 14,
ACLK_CORE_NIU2BUS_SEL_MASK = 0x3 << ACLK_CORE_NIU2BUS_SEL_SHIFT,
ACLK_CORE_NDFT_DIV_SHIFT = 8,
ACLK_CORE_NDFT_DIV_MASK = 0x1f << ACLK_CORE_NDFT_DIV_SHIFT,
/* CRU_CLK_SEL10_CON */
HCLK_PERIMID_SEL_SHIFT = 6,
HCLK_PERIMID_SEL_MASK = 3 << HCLK_PERIMID_SEL_SHIFT,
HCLK_PERIMID_SEL_150M = 0,
HCLK_PERIMID_SEL_100M,
HCLK_PERIMID_SEL_75M,
HCLK_PERIMID_SEL_24M,
ACLK_PERIMID_SEL_SHIFT = 4,
ACLK_PERIMID_SEL_MASK = 3 << ACLK_PERIMID_SEL_SHIFT,
ACLK_PERIMID_SEL_300M = 0,
ACLK_PERIMID_SEL_200M,
ACLK_PERIMID_SEL_100M,
ACLK_PERIMID_SEL_24M,
/* CRU_CLK_SEL27_CON */
CLK_CRYPTO_PKA_SEL_SHIFT = 6,
CLK_CRYPTO_PKA_SEL_MASK = 3 << CLK_CRYPTO_PKA_SEL_SHIFT,
CLK_CRYPTO_PKA_SEL_300M = 0,
CLK_CRYPTO_PKA_SEL_200M,
CLK_CRYPTO_PKA_SEL_100M,
CLK_CRYPTO_CORE_SEL_SHIFT = 4,
CLK_CRYPTO_CORE_SEL_MASK = 3 << CLK_CRYPTO_CORE_SEL_SHIFT,
CLK_CRYPTO_CORE_SEL_200M = 0,
CLK_CRYPTO_CORE_SEL_150M,
CLK_CRYPTO_CORE_SEL_100M,
HCLK_SECURE_FLASH_SEL_SHIFT = 2,
HCLK_SECURE_FLASH_SEL_MASK = 3 << HCLK_SECURE_FLASH_SEL_SHIFT,
HCLK_SECURE_FLASH_SEL_150M = 0,
HCLK_SECURE_FLASH_SEL_100M,
HCLK_SECURE_FLASH_SEL_75M,
HCLK_SECURE_FLASH_SEL_24M,
ACLK_SECURE_FLASH_SEL_SHIFT = 0,
ACLK_SECURE_FLASH_SEL_MASK = 3 << ACLK_SECURE_FLASH_SEL_SHIFT,
ACLK_SECURE_FLASH_SEL_200M = 0,
ACLK_SECURE_FLASH_SEL_150M,
ACLK_SECURE_FLASH_SEL_100M,
ACLK_SECURE_FLASH_SEL_24M,
/* CRU_CLK_SEL28_CON */
CCLK_EMMC_SEL_SHIFT = 12,
CCLK_EMMC_SEL_MASK = 7 << CCLK_EMMC_SEL_SHIFT,
CCLK_EMMC_SEL_24M = 0,
CCLK_EMMC_SEL_200M,
CCLK_EMMC_SEL_150M,
CCLK_EMMC_SEL_100M,
CCLK_EMMC_SEL_50M,
CCLK_EMMC_SEL_375K,
BCLK_EMMC_SEL_SHIFT = 8,
BCLK_EMMC_SEL_MASK = 3 << BCLK_EMMC_SEL_SHIFT,
BCLK_EMMC_SEL_200M = 0,
BCLK_EMMC_SEL_150M,
BCLK_EMMC_SEL_125M,
SCLK_SFC_SEL_SHIFT = 4,
SCLK_SFC_SEL_MASK = 7 << SCLK_SFC_SEL_SHIFT,
SCLK_SFC_SEL_24M = 0,
SCLK_SFC_SEL_50M,
SCLK_SFC_SEL_75M,
SCLK_SFC_SEL_100M,
SCLK_SFC_SEL_125M,
SCLK_SFC_SEL_150M,
NCLK_NANDC_SEL_SHIFT = 0,
NCLK_NANDC_SEL_MASK = 3 << NCLK_NANDC_SEL_SHIFT,
NCLK_NANDC_SEL_200M = 0,
NCLK_NANDC_SEL_150M,
NCLK_NANDC_SEL_100M,
NCLK_NANDC_SEL_24M,
/* CRU_CLK_SEL30_CON */
CLK_SDMMC1_SEL_SHIFT = 12,
CLK_SDMMC1_SEL_MASK = 7 << CLK_SDMMC1_SEL_SHIFT,
CLK_SDMMC0_SEL_SHIFT = 8,
CLK_SDMMC0_SEL_MASK = 7 << CLK_SDMMC0_SEL_SHIFT,
CLK_SDMMC_SEL_24M = 0,
CLK_SDMMC_SEL_400M,
CLK_SDMMC_SEL_300M,
CLK_SDMMC_SEL_100M,
CLK_SDMMC_SEL_50M,
CLK_SDMMC_SEL_750K,
/* CRU_CLK_SEL31_CON */
CLK_MAC0_OUT_SEL_SHIFT = 14,
CLK_MAC0_OUT_SEL_MASK = 3 << CLK_MAC0_OUT_SEL_SHIFT,
CLK_MAC0_OUT_SEL_125M = 0,
CLK_MAC0_OUT_SEL_50M,
CLK_MAC0_OUT_SEL_25M,
CLK_MAC0_OUT_SEL_24M,
CLK_GMAC0_PTP_REF_SEL_SHIFT = 12,
CLK_GMAC0_PTP_REF_SEL_MASK = 3 << CLK_GMAC0_PTP_REF_SEL_SHIFT,
CLK_GMAC0_PTP_REF_SEL_62_5M = 0,
CLK_GMAC0_PTP_REF_SEL_100M,
CLK_GMAC0_PTP_REF_SEL_50M,
CLK_GMAC0_PTP_REF_SEL_24M,
CLK_MAC0_2TOP_SEL_SHIFT = 8,
CLK_MAC0_2TOP_SEL_MASK = 3 << CLK_MAC0_2TOP_SEL_SHIFT,
CLK_MAC0_2TOP_SEL_125M = 0,
CLK_MAC0_2TOP_SEL_50M,
CLK_MAC0_2TOP_SEL_25M,
CLK_MAC0_2TOP_SEL_PPLL,
RGMII0_CLK_SEL_SHIFT = 4,
RGMII0_CLK_SEL_MASK = 3 << RGMII0_CLK_SEL_SHIFT,
RGMII0_CLK_SEL_125M = 0,
RGMII0_CLK_SEL_125M_1,
RGMII0_CLK_SEL_2_5M,
RGMII0_CLK_SEL_25M,
RMII0_CLK_SEL_SHIFT = 3,
RMII0_CLK_SEL_MASK = 1 << RMII0_CLK_SEL_SHIFT,
RMII0_CLK_SEL_2_5M = 0,
RMII0_CLK_SEL_25M,
RMII0_EXTCLK_SEL_SHIFT = 2,
RMII0_EXTCLK_SEL_MASK = 1 << RMII0_EXTCLK_SEL_SHIFT,
RMII0_EXTCLK_SEL_MAC0_TOP = 0,
RMII0_EXTCLK_SEL_IO,
RMII0_MODE_SHIFT = 0,
RMII0_MODE_MASK = 3 << RMII0_MODE_SHIFT,
RMII0_MODE_SEL_RGMII = 0,
RMII0_MODE_SEL_RMII,
RMII0_MODE_SEL_GMII,
/* CRU_CLK_SEL32_CON */
CLK_SDMMC2_SEL_SHIFT = 8,
CLK_SDMMC2_SEL_MASK = 7 << CLK_SDMMC2_SEL_SHIFT,
/* CRU_CLK_SEL38_CON */
ACLK_VOP_PRE_SEL_SHIFT = 6,
ACLK_VOP_PRE_SEL_MASK = 3 << ACLK_VOP_PRE_SEL_SHIFT,
ACLK_VOP_PRE_SEL_CPLL = 0,
ACLK_VOP_PRE_SEL_GPLL,
ACLK_VOP_PRE_SEL_HPLL,
ACLK_VOP_PRE_SEL_VPLL,
ACLK_VOP_PRE_DIV_SHIFT = 0,
ACLK_VOP_PRE_DIV_MASK = 0x1f << ACLK_VOP_PRE_DIV_SHIFT,
/* CRU_CLK_SEL39_CON */
DCLK0_VOP_SEL_SHIFT = 10,
DCLK0_VOP_SEL_MASK = 3 << DCLK0_VOP_SEL_SHIFT,
DCLK_VOP_SEL_HPLL = 0,
DCLK_VOP_SEL_VPLL,
DCLK_VOP_SEL_GPLL,
DCLK_VOP_SEL_CPLL,
DCLK0_VOP_DIV_SHIFT = 0,
DCLK0_VOP_DIV_MASK = 0xff << DCLK0_VOP_DIV_SHIFT,
/* CRU_CLK_SEL40_CON */
DCLK1_VOP_SEL_SHIFT = 10,
DCLK1_VOP_SEL_MASK = 3 << DCLK1_VOP_SEL_SHIFT,
DCLK1_VOP_DIV_SHIFT = 0,
DCLK1_VOP_DIV_MASK = 0xff << DCLK1_VOP_DIV_SHIFT,
/* CRU_CLK_SEL41_CON */
DCLK2_VOP_SEL_SHIFT = 10,
DCLK2_VOP_SEL_MASK = 3 << DCLK2_VOP_SEL_SHIFT,
DCLK2_VOP_DIV_SHIFT = 0,
DCLK2_VOP_DIV_MASK = 0xff << DCLK2_VOP_DIV_SHIFT,
/* CRU_CLK_SEL43_CON */
DCLK_EBC_SEL_SHIFT = 6,
DCLK_EBC_SEL_MASK = 3 << DCLK_EBC_SEL_SHIFT,
DCLK_EBC_SEL_GPLL_400M = 0,
DCLK_EBC_SEL_CPLL_333M,
DCLK_EBC_SEL_GPLL_200M,
/* CRU_CLK_SEL47_CON */
ACLK_RKVDEC_SEL_SHIFT = 7,
ACLK_RKVDEC_SEL_MASK = 1 << ACLK_RKVDEC_SEL_SHIFT,
ACLK_RKVDEC_SEL_GPLL = 0,
ACLK_RKVDEC_SEL_CPLL,
ACLK_RKVDEC_DIV_SHIFT = 0,
ACLK_RKVDEC_DIV_MASK = 0x1f << ACLK_RKVDEC_DIV_SHIFT,
/* CRU_CLK_SEL49_CON */
CLK_RKVDEC_CORE_SEL_SHIFT = 14,
CLK_RKVDEC_CORE_SEL_MASK = 0x3 << CLK_RKVDEC_CORE_SEL_SHIFT,
CLK_RKVDEC_CORE_SEL_GPLL = 0,
CLK_RKVDEC_CORE_SEL_CPLL,
CLK_RKVDEC_CORE_SEL_NPLL,
CLK_RKVDEC_CORE_SEL_VPLL,
CLK_RKVDEC_CORE_DIV_SHIFT = 8,
CLK_RKVDEC_CORE_DIV_MASK = 0x1f << CLK_RKVDEC_CORE_DIV_SHIFT,
/* CRU_CLK_SEL50_CON */
PCLK_BUS_SEL_SHIFT = 4,
PCLK_BUS_SEL_MASK = 3 << PCLK_BUS_SEL_SHIFT,
PCLK_BUS_SEL_100M = 0,
PCLK_BUS_SEL_75M,
PCLK_BUS_SEL_50M,
PCLK_BUS_SEL_24M,
ACLK_BUS_SEL_SHIFT = 0,
ACLK_BUS_SEL_MASK = 3 << ACLK_BUS_SEL_SHIFT,
ACLK_BUS_SEL_200M = 0,
ACLK_BUS_SEL_150M,
ACLK_BUS_SEL_100M,
ACLK_BUS_SEL_24M,
/* CRU_CLK_SEL51_CON */
CLK_TSADC_DIV_SHIFT = 8,
CLK_TSADC_DIV_MASK = 0x7f << CLK_TSADC_DIV_SHIFT,
CLK_TSADC_TSEN_SEL_SHIFT = 4,
CLK_TSADC_TSEN_SEL_MASK = 0x3 << CLK_TSADC_TSEN_SEL_SHIFT,
CLK_TSADC_TSEN_SEL_24M = 0,
CLK_TSADC_TSEN_SEL_100M,
CLK_TSADC_TSEN_SEL_CPLL_100M,
CLK_TSADC_TSEN_DIV_SHIFT = 0,
CLK_TSADC_TSEN_DIV_MASK = 0x7 << CLK_TSADC_TSEN_DIV_SHIFT,
/* CRU_CLK_SEL52_CON */
CLK_UART_SEL_SHIFT = 12,
CLK_UART_SEL_MASK = 0x3 << CLK_UART_SEL_SHIFT,
CLK_UART_SEL_SRC = 0,
CLK_UART_SEL_FRAC,
CLK_UART_SEL_XIN24M,
CLK_UART_SRC_SEL_SHIFT = 8,
CLK_UART_SRC_SEL_MASK = 0x3 << CLK_UART_SRC_SEL_SHIFT,
CLK_UART_SRC_SEL_GPLL = 0,
CLK_UART_SRC_SEL_CPLL,
CLK_UART_SRC_SEL_480M,
CLK_UART_SRC_DIV_SHIFT = 0,
CLK_UART_SRC_DIV_MASK = 0x3f << CLK_UART_SRC_DIV_SHIFT,
/* CRU_CLK_SEL53_CON */
CLK_UART_FRAC_NUMERATOR_SHIFT = 16,
CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16,
CLK_UART_FRAC_DENOMINATOR_SHIFT = 0,
CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff,
/* CRU_CLK_SEL71_CON */
CLK_I2C_SEL_SHIFT = 8,
CLK_I2C_SEL_MASK = 3 << CLK_I2C_SEL_SHIFT,
CLK_I2C_SEL_200M = 0,
CLK_I2C_SEL_100M,
CLK_I2C_SEL_24M,
CLK_I2C_SEL_CPLL_100M,
/* CRU_CLK_SEL72_CON */
CLK_PWM3_SEL_SHIFT = 12,
CLK_PWM3_SEL_MASK = 3 << CLK_PWM3_SEL_SHIFT,
CLK_PWM2_SEL_SHIFT = 10,
CLK_PWM2_SEL_MASK = 3 << CLK_PWM2_SEL_SHIFT,
CLK_PWM1_SEL_SHIFT = 8,
CLK_PWM1_SEL_MASK = 3 << CLK_PWM1_SEL_SHIFT,
CLK_PWM_SEL_100M = 0,
CLK_PWM_SEL_24M,
CLK_PWM_SEL_CPLL_100M,
CLK_SPI3_SEL_SHIFT = 6,
CLK_SPI3_SEL_MASK = 3 << CLK_SPI3_SEL_SHIFT,
CLK_SPI2_SEL_SHIFT = 4,
CLK_SPI2_SEL_MASK = 3 << CLK_SPI2_SEL_SHIFT,
CLK_SPI1_SEL_SHIFT = 2,
CLK_SPI1_SEL_MASK = 3 << CLK_SPI1_SEL_SHIFT,
CLK_SPI0_SEL_SHIFT = 0,
CLK_SPI0_SEL_MASK = 3 << CLK_SPI0_SEL_SHIFT,
CLK_SPI_SEL_200M = 0,
CLK_SPI_SEL_24M,
CLK_SPI_SEL_CPLL_100M,
/* CRU_CLK_SEL73_CON */
PCLK_TOP_SEL_SHIFT = 12,
PCLK_TOP_SEL_MASK = 3 << PCLK_TOP_SEL_SHIFT,
PCLK_TOP_SEL_100M = 0,
PCLK_TOP_SEL_75M,
PCLK_TOP_SEL_50M,
PCLK_TOP_SEL_24M,
HCLK_TOP_SEL_SHIFT = 8,
HCLK_TOP_SEL_MASK = 3 << HCLK_TOP_SEL_SHIFT,
HCLK_TOP_SEL_150M = 0,
HCLK_TOP_SEL_100M,
HCLK_TOP_SEL_75M,
HCLK_TOP_SEL_24M,
ACLK_TOP_LOW_SEL_SHIFT = 4,
ACLK_TOP_LOW_SEL_MASK = 3 << ACLK_TOP_LOW_SEL_SHIFT,
ACLK_TOP_LOW_SEL_400M = 0,
ACLK_TOP_LOW_SEL_300M,
ACLK_TOP_LOW_SEL_200M,
ACLK_TOP_LOW_SEL_24M,
ACLK_TOP_HIGH_SEL_SHIFT = 0,
ACLK_TOP_HIGH_SEL_MASK = 3 << ACLK_TOP_HIGH_SEL_SHIFT,
ACLK_TOP_HIGH_SEL_500M = 0,
ACLK_TOP_HIGH_SEL_400M,
ACLK_TOP_HIGH_SEL_300M,
ACLK_TOP_HIGH_SEL_24M,
/* CRU_CLK_SEL78_CON */
CPLL_500M_DIV_SHIFT = 8,
CPLL_500M_DIV_MASK = 0x1f << CPLL_500M_DIV_SHIFT,
/* CRU_CLK_SEL79_CON */
CPLL_250M_DIV_SHIFT = 8,
CPLL_250M_DIV_MASK = 0x1f << CPLL_250M_DIV_SHIFT,
CPLL_333M_DIV_SHIFT = 0,
CPLL_333M_DIV_MASK = 0x1f << CPLL_333M_DIV_SHIFT,
/* CRU_CLK_SEL80_CON */
CPLL_62P5M_DIV_SHIFT = 8,
CPLL_62P5M_DIV_MASK = 0x1f << CPLL_62P5M_DIV_SHIFT,
CPLL_125M_DIV_SHIFT = 0,
CPLL_125M_DIV_MASK = 0x1f << CPLL_125M_DIV_SHIFT,
/* CRU_CLK_SEL81_CON */
CPLL_25M_DIV_SHIFT = 8,
CPLL_25M_DIV_MASK = 0x1f << CPLL_25M_DIV_SHIFT,
CPLL_50M_DIV_SHIFT = 0,
CPLL_50M_DIV_MASK = 0x1f << CPLL_50M_DIV_SHIFT,
/* CRU_CLK_SEL82_CON */
CPLL_100M_DIV_SHIFT = 0,
CPLL_100M_DIV_MASK = 0x1f << CPLL_100M_DIV_SHIFT,
};
#endif

369
arch/arm/include/asm/arch-rockchip/grf_rk3568.h Normal file
View file

@ -0,0 +1,369 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
*/
#ifndef __SOC_ROCKCHIP_RK3568_GRF_H__
#define __SOC_ROCKCHIP_RK3568_GRF_H__
struct rk3568_grf {
unsigned int gpio1a_iomux_l;
unsigned int gpio1a_iomux_h;
unsigned int gpio1b_iomux_l;
unsigned int gpio1b_iomux_h;
unsigned int gpio1c_iomux_l;
unsigned int gpio1c_iomux_h;
unsigned int gpio1d_iomux_l;
unsigned int gpio1d_iomux_h;
unsigned int gpio2a_iomux_l;
unsigned int gpio2a_iomux_h;
unsigned int gpio2b_iomux_l;
unsigned int gpio2b_iomux_h;
unsigned int gpio2c_iomux_l;
unsigned int gpio2c_iomux_h;
unsigned int gpio2d_iomux_l;
unsigned int gpio2d_iomux_h;
unsigned int gpio3a_iomux_l;
unsigned int gpio3a_iomux_h;
unsigned int gpio3b_iomux_l;
unsigned int gpio3b_iomux_h;
unsigned int gpio3c_iomux_l;
unsigned int gpio3c_iomux_h;
unsigned int gpio3d_iomux_l;
unsigned int gpio3d_iomux_h;
unsigned int gpio4a_iomux_l;
unsigned int gpio4a_iomux_h;
unsigned int gpio4b_iomux_l;
unsigned int gpio4b_iomux_h;
unsigned int gpio4c_iomux_l;
unsigned int gpio4c_iomux_h;
unsigned int gpio4d_iomux_l;
unsigned int reserved0[(0x0080 - 0x0078) / 4 - 1];
unsigned int gpio1a_p;
unsigned int gpio1b_p;
unsigned int gpio1c_p;
unsigned int gpio1d_p;
unsigned int gpio2a_p;
unsigned int gpio2b_p;
unsigned int gpio2c_p;
unsigned int gpio2d_p;
unsigned int gpio3a_p;
unsigned int gpio3b_p;
unsigned int gpio3c_p;
unsigned int gpio3d_p;
unsigned int gpio4a_p;
unsigned int gpio4b_p;
unsigned int gpio4c_p;
unsigned int gpio4d_p;
unsigned int gpio1a_ie;
unsigned int gpio1b_ie;
unsigned int gpio1c_ie;
unsigned int gpio1d_ie;
unsigned int gpio2a_ie;
unsigned int gpio2b_ie;
unsigned int gpio2c_ie;
unsigned int gpio2d_ie;
unsigned int gpio3a_ie;
unsigned int gpio3b_ie;
unsigned int gpio3c_ie;
unsigned int gpio3d_ie;
unsigned int gpio4a_ie;
unsigned int gpio4b_ie;
unsigned int gpio4c_ie;
unsigned int gpio4d_ie;
unsigned int gpio1a_opd;
unsigned int gpio1b_opd;
unsigned int gpio1c_opd;
unsigned int gpio1d_opd;
unsigned int gpio2a_opd;
unsigned int gpio2b_opd;
unsigned int gpio2c_opd;
unsigned int gpio2d_opd;
unsigned int gpio3a_opd;
unsigned int gpio3b_opd;
unsigned int gpio3c_opd;
unsigned int gpio3d_opd;
unsigned int gpio4a_opd;
unsigned int gpio4b_opd;
unsigned int gpio4c_opd;
unsigned int gpio4d_opd;
unsigned int gpio1a_sus;
unsigned int gpio1b_sus;
unsigned int gpio1c_sus;
unsigned int gpio1d_sus;
unsigned int gpio2a_sus;
unsigned int gpio2b_sus;
unsigned int gpio2c_sus;
unsigned int gpio2d_sus;
unsigned int gpio3a_sus;
unsigned int gpio3b_sus;
unsigned int gpio3c_sus;
unsigned int gpio3d_sus;
unsigned int gpio4a_sus;
unsigned int gpio4b_sus;
unsigned int gpio4c_sus;
unsigned int gpio4d_sus;
unsigned int gpio1a_sl;
unsigned int gpio1b_sl;
unsigned int gpio1c_sl;
unsigned int gpio1d_sl;
unsigned int gpio2a_sl;
unsigned int gpio2b_sl;
unsigned int gpio2c_sl;
unsigned int gpio2d_sl;
unsigned int gpio3a_sl;
unsigned int gpio3b_sl;
unsigned int gpio3c_sl;
unsigned int gpio3d_sl;
unsigned int gpio4a_sl;
unsigned int gpio4b_sl;
unsigned int gpio4c_sl;
unsigned int gpio4d_sl;
unsigned int reserved1[(0x0200 - 0x01bc) / 4 - 1];
unsigned int gpio1a_ds_0;
unsigned int gpio1a_ds_1;
unsigned int gpio1a_ds_2;
unsigned int gpio1a_ds_3;
unsigned int gpio1b_ds_0;
unsigned int gpio1b_ds_1;
unsigned int gpio1b_ds_2;
unsigned int gpio1b_ds_3;
unsigned int gpio1c_ds_0;
unsigned int gpio1c_ds_1;
unsigned int gpio1c_ds_2;
unsigned int gpio1c_ds_3;
unsigned int gpio1d_ds_0;
unsigned int gpio1d_ds_1;
unsigned int gpio1d_ds_2;
unsigned int gpio1d_ds_3;
unsigned int gpio2a_ds_0;
unsigned int gpio2a_ds_1;
unsigned int gpio2a_ds_2;
unsigned int gpio2a_ds_3;
unsigned int gpio2b_ds_0;
unsigned int gpio2b_ds_1;
unsigned int gpio2b_ds_2;
unsigned int gpio2b_ds_3;
unsigned int gpio2c_ds_0;
unsigned int gpio2c_ds_1;
unsigned int gpio2c_ds_2;
unsigned int gpio2c_ds_3;
unsigned int gpio2d_ds_0;
unsigned int gpio2d_ds_1;
unsigned int gpio2d_ds_2;
unsigned int gpio2d_ds_3;
unsigned int gpio3a_ds_0;
unsigned int gpio3a_ds_1;
unsigned int gpio3a_ds_2;
unsigned int gpio3a_ds_3;
unsigned int gpio3b_ds_0;
unsigned int gpio3b_ds_1;
unsigned int gpio3b_ds_2;
unsigned int gpio3b_ds_3;
unsigned int gpio3c_ds_0;
unsigned int gpio3c_ds_1;
unsigned int gpio3c_ds_2;
unsigned int gpio3c_ds_3;
unsigned int gpio3d_ds_0;
unsigned int gpio3d_ds_1;
unsigned int gpio3d_ds_2;
unsigned int gpio3d_ds_3;
unsigned int gpio4a_ds_0;
unsigned int gpio4a_ds_1;
unsigned int gpio4a_ds_2;
unsigned int gpio4a_ds_3;
unsigned int gpio4b_ds_0;
unsigned int gpio4b_ds_1;
unsigned int gpio4b_ds_2;
unsigned int gpio4b_ds_3;
unsigned int gpio4c_ds_0;
unsigned int gpio4c_ds_1;
unsigned int gpio4c_ds_2;
unsigned int gpio4c_ds_3;
unsigned int gpio4d_ds_0;
unsigned int gpio4d_ds_1;
unsigned int gpio4d_ds_2;
unsigned int gpio4d_ds_3;
unsigned int iofunc_sel0;
unsigned int iofunc_sel1;
unsigned int iofunc_sel2;
unsigned int iofunc_sel3;
unsigned int iofunc_sel4;
unsigned int iofunc_sel5;
unsigned int reserved2[(0x0340 - 0x0314) / 4 - 1];
unsigned int vi_con0;
unsigned int vi_con1;
unsigned int vi_status0;
unsigned int reserved3[(0x0360 - 0x0348) / 4 - 1];
unsigned int vo_con0;
unsigned int vo_con1;
unsigned int vo_con2;
unsigned int vo_con3;
unsigned int reserved4[(0x0380 - 0x036c) / 4 - 1];
unsigned int mac0_con0;
unsigned int mac0_con1;
unsigned int mac1_con0;
unsigned int mac1_con1;
unsigned int reserved5[(0x03a0 - 0x038c) / 4 - 1];
unsigned int biu_con0;
unsigned int biu_con1;
unsigned int biu_con2;
unsigned int reserved6[(0x03c0 - 0x03a8) / 4 - 1];
unsigned int gic_con0;
unsigned int gic_con1;
unsigned int gic_con2;
unsigned int reserved7[(0x03f0 - 0x03c8) / 4 - 1];
unsigned int gpu_con0;
unsigned int gpu_con1;
unsigned int reserved8[(0x0400 - 0x03f4) / 4 - 1];
unsigned int cpu_con0;
unsigned int reserved9[(0x0420 - 0x0400) / 4 - 1];
unsigned int cpu_status0;
unsigned int reserved10[(0x0500 - 0x0420) / 4 - 1];
unsigned int soc_con0;
unsigned int soc_con1;
unsigned int soc_con2;
unsigned int soc_con3;
unsigned int reserved11[(0x0514 - 0x050c) / 4 - 1];
unsigned int soc_con5;
unsigned int soc_con6;
unsigned int reserved12[(0x0580 - 0x0518) / 4 - 1];
unsigned int soc_status0;
unsigned int reserved13[(0x05c0 - 0x0580) / 4 - 1];
unsigned int ram_con;
unsigned int core_ram_con;
unsigned int reserved14[(0x0600 - 0x05c4) / 4 - 1];
unsigned int tsadc_con;
unsigned int reserved15[(0x0610 - 0x0600) / 4 - 1];
unsigned int saradc_con;
unsigned int reserved16[(0x0700 - 0x0610) / 4 - 1];
unsigned int gpupvtpll_con0;
unsigned int gpupvtpll_con1;
unsigned int gpupvtpll_con2;
unsigned int gpupvtpll_con3;
unsigned int reserved17[(0x0740 - 0x070c) / 4 - 1];
unsigned int npupvtpll_con0;
unsigned int npupvtpll_con1;
unsigned int npupvtpll_con2;
unsigned int npupvtpll_con3;
unsigned int reserved18[(0x0800 - 0x074c) / 4 - 1];
unsigned int chip_id;
unsigned int reserved19[(0x0840 - 0x0800) / 4 - 1];
unsigned int gpio1c5_ds;
unsigned int gpio2a2_ds;
unsigned int gpio2b0_ds;
unsigned int gpio3a0_ds;
unsigned int gpio3a6_ds;
unsigned int gpio4a0_ds;
unsigned int reserved20[(0x0900 - 0x0854) / 4 - 1];
unsigned int dmac0_con0;
unsigned int dmac0_con1;
unsigned int dmac0_con2;
unsigned int dmac0_con3;
unsigned int dmac0_con4;
unsigned int dmac0_con5;
unsigned int dmac0_con6;
unsigned int dmac0_con7;
unsigned int dmac0_con8;
unsigned int dmac0_con9;
unsigned int reserved21[(0x0940 - 0x0924) / 4 - 1];
unsigned int dmac1_con0;
unsigned int dmac1_con1;
unsigned int dmac1_con2;
unsigned int dmac1_con3;
unsigned int dmac1_con4;
unsigned int dmac1_con5;
unsigned int dmac1_con6;
unsigned int dmac1_con7;
unsigned int dmac1_con8;
unsigned int dmac1_con9;
};
check_member(rk3568_grf, dmac1_con9, 0x0964);
struct rk3568_pmugrf {
unsigned int pmu_gpio0a_iomux_l;
unsigned int pmu_gpio0a_iomux_h;
unsigned int pmu_gpio0b_iomux_l;
unsigned int pmu_gpio0b_iomux_h;
unsigned int pmu_gpio0c_iomux_l;
unsigned int pmu_gpio0c_iomux_h;
unsigned int pmu_gpio0d_iomux_l;
unsigned int reserved0[(0x0020 - 0x0018) / 4 - 1];
unsigned int pmu_gpio0a_p;
unsigned int pmu_gpio0b_p;
unsigned int pmu_gpio0c_p;
unsigned int pmu_gpio0d_p;
unsigned int pmu_gpio0a_ie;
unsigned int pmu_gpio0b_ie;
unsigned int pmu_gpio0c_ie;
unsigned int pmu_gpio0d_ie;
unsigned int pmu_gpio0a_opd;
unsigned int pmu_gpio0b_opd;
unsigned int pmu_gpio0c_opd;
unsigned int pmu_gpio0d_opd;
unsigned int pmu_gpio0a_sus;
unsigned int pmu_gpio0b_sus;
unsigned int pmu_gpio0c_sus;
unsigned int pmu_gpio0d_sus;
unsigned int pmu_gpio0a_sl;
unsigned int pmu_gpio0b_sl;
unsigned int pmu_gpio0c_sl;
unsigned int pmu_gpio0d_sl;
unsigned int pmu_gpio0a_ds_0;
unsigned int pmu_gpio0a_ds_1;
unsigned int pmu_gpio0a_ds_2;
unsigned int pmu_gpio0a_ds_3;
unsigned int pmu_gpio0b_ds_0;
unsigned int pmu_gpio0b_ds_1;
unsigned int pmu_gpio0b_ds_2;
unsigned int pmu_gpio0b_ds_3;
unsigned int pmu_gpio0c_ds_0;
unsigned int pmu_gpio0c_ds_1;
unsigned int pmu_gpio0c_ds_2;
unsigned int pmu_gpio0c_ds_3;
unsigned int pmu_gpio0d_ds_0;
unsigned int pmu_gpio0d_ds_1;
unsigned int pmu_gpio0d_ds_2;
unsigned int pmu_gpio0d_ds_3;
unsigned int reserved1[(0x0100 - 0x00ac) / 4 - 1];
unsigned int pmu_soc_con0;
unsigned int pmu_soc_con1;
unsigned int pmu_soc_con2;
unsigned int pmu_soc_con3;
unsigned int pmu_soc_con4;
unsigned int pmu_soc_con5;
unsigned int reserved2[(0x0124 - 0x0114) / 4 - 1];
unsigned int pmu_io_vsel0;
unsigned int pmu_io_vsel1;
unsigned int pmu_io_vsel2;
unsigned int reserved3[(0x0180 - 0x012c) / 4 - 1];
unsigned int pmu_dll_con0;
unsigned int reserved4[(0x0200 - 0x0180) / 4 - 1];
unsigned int pmu_os_reg0;
unsigned int pmu_os_reg1;
unsigned int pmu_os_reg2;
unsigned int pmu_os_reg3;
unsigned int pmu_os_reg4;
unsigned int pmu_os_reg5;
unsigned int pmu_os_reg6;
unsigned int pmu_os_reg7;
unsigned int pmu_os_reg8;
unsigned int pmu_os_reg9;
unsigned int pmu_os_reg10;
unsigned int pmu_os_reg11;
unsigned int pmu_reset_function_status;
unsigned int pmu_reset_function_clr;
unsigned int reserved5[(0x0380 - 0x0234) / 4 - 1];
unsigned int pmu_sig_detect_con;
unsigned int reserved6[(0x0390 - 0x0380) / 4 - 1];
unsigned int pmu_sig_detect_status;
unsigned int reserved7[(0x03a0 - 0x0390) / 4 - 1];
unsigned int pmu_sig_detect_status_clear;
unsigned int reserved8[(0x03b0 - 0x03a0) / 4 - 1];
unsigned int pmu_sdmmc_det_counter;
};
check_member(rk3568_pmugrf, pmu_sdmmc_det_counter, 0x03b0);
#endif

4
arch/arm/mach-at91/include/mach/sama5d3.h
View file

@ -190,8 +190,8 @@
/*
* PMECC table in ROM
*/
#define ATMEL_PMECC_INDEX_OFFSET_512 0x8000
#define ATMEL_PMECC_INDEX_OFFSET_1024 0x10000
#define ATMEL_PMECC_INDEX_OFFSET_512 0x10000
#define ATMEL_PMECC_INDEX_OFFSET_1024 0x18000
/*
* SAMA5D3 specific prototypes

18
arch/arm/mach-k3/Kconfig
View file

@ -147,6 +147,24 @@ config SYS_K3_SPL_ATF
Enabling this will try to start Cortex-A (typically with ATF)
after SPL from R5.
config K3_ATF_LOAD_ADDR
hex "Load address of ATF image"
default 0x70000000
help
The load address for the ATF image. This value defaults to 0x70000000
if not provided in the board defconfig file.
config K3_DM_FW
bool "Separate DM firmware image"
depends on SPL && CPU_V7R && SOC_K3_J721E && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
default y
help
Enabling this will indicate that the system has separate DM
and TIFS firmware images in place, instead of a single SYSFW
firmware. Due to DM being executed on the same core as R5 SPL
bootloader, it makes RM and PM services not being available
during R5 SPL execution time.
source "board/ti/am65x/Kconfig"
source "board/ti/am64x/Kconfig"
source "board/ti/j721e/Kconfig"

2
arch/arm/mach-k3/Makefile
View file

@ -4,7 +4,7 @@
# Lokesh Vutla <lokeshvutla@ti.com>
obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o
obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o j721e/ j7200/
obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
obj-$(CONFIG_ARM64) += arm64-mmu.o
obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o

46
arch/arm/mach-k3/am642_init.c
View file

@ -8,6 +8,7 @@
*/
#include <common.h>
#include <fdt_support.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
@ -106,6 +107,38 @@ void do_dt_magic(void)
}
#endif
#if CONFIG_IS_ENABLED(USB_STORAGE)
static int fixup_usb_boot(const void *fdt_blob)
{
int ret = 0;
switch (spl_boot_device()) {
case BOOT_DEVICE_USB:
/*
* If the boot mode is host, fixup the dr_mode to host
* before cdns3 bind takes place
*/
ret = fdt_find_and_setprop((void *)fdt_blob,
"/bus@f4000/cdns-usb@f900000/usb@f400000",
"dr_mode", "host", 5, 0);
if (ret)
printf("%s: fdt_find_and_setprop() failed:%d\n",
__func__, ret);
fallthrough;
default:
break;
}
return ret;
}
int fdtdec_board_setup(const void *fdt_blob)
{
/* Can use the pointer from the function parameters */
return fixup_usb_boot(fdt_blob);
}
#endif
void board_init_f(ulong dummy)
{
#if defined(CONFIG_K3_LOAD_SYSFW)
@ -192,8 +225,11 @@ static u32 __get_backup_bootmedia(u32 main_devstat)
case BACKUP_BOOT_DEVICE_UART:
return BOOT_DEVICE_UART;
case BACKUP_BOOT_DEVICE_USB:
return BOOT_DEVICE_USB;
case BACKUP_BOOT_DEVICE_DFU:
if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK)
return BOOT_DEVICE_USB;
return BOOT_DEVICE_DFU;
case BACKUP_BOOT_DEVICE_ETHERNET:
return BOOT_DEVICE_ETHERNET;
@ -245,6 +281,12 @@ static u32 __get_primary_bootmedia(u32 main_devstat)
return BOOT_DEVICE_MMC2;
return BOOT_DEVICE_MMC1;
case BOOT_DEVICE_DFU:
if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >>
MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT)
return BOOT_DEVICE_USB;
return BOOT_DEVICE_DFU;
case BOOT_DEVICE_NOBOOT:
return BOOT_DEVICE_RAM;
}

87
arch/arm/mach-k3/common.c
View file

@ -28,6 +28,27 @@
#include <elf.h>
#include <soc.h>
#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
enum {
IMAGE_ID_ATF,
IMAGE_ID_OPTEE,
IMAGE_ID_SPL,
IMAGE_ID_DM_FW,
IMAGE_AMT,
};
#if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS)
static const char *image_os_match[IMAGE_AMT] = {
"arm-trusted-firmware",
"tee",
"U-Boot",
"DM",
};
#endif
static struct image_info fit_image_info[IMAGE_AMT];
#endif
struct ti_sci_handle *get_ti_sci_handle(void)
{
struct udevice *dev;
@ -107,7 +128,7 @@ int early_console_init(void)
}
#endif
#ifdef CONFIG_SYS_K3_SPL_ATF
#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
void init_env(void)
{
@ -181,7 +202,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
typedef void __noreturn (*image_entry_noargs_t)(void);
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
u32 loadaddr = 0;
int ret, size;
int ret, size = 0;
/* Release all the exclusive devices held by SPL before starting ATF */
ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
@ -191,16 +212,22 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
panic("rproc failed to be initialized (%d)\n", ret);
init_env();
start_non_linux_remote_cores();
size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
&loadaddr);
if (!fit_image_info[IMAGE_ID_DM_FW].image_start) {
start_non_linux_remote_cores();
size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
&loadaddr);
}
/*
* It is assumed that remoteproc device 1 is the corresponding
* Cortex-A core which runs ATF. Make sure DT reflects the same.
*/
ret = rproc_load(1, spl_image->entry_point, 0x200);
if (!fit_image_info[IMAGE_ID_ATF].image_start)
fit_image_info[IMAGE_ID_ATF].image_start =
spl_image->entry_point;
ret = rproc_load(1, fit_image_info[IMAGE_ID_ATF].image_start, 0x200);
if (ret)
panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);
@ -210,7 +237,8 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
ret = rproc_start(1);
if (ret)
panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);
if (!(size > 0 && valid_elf_image(loadaddr))) {
if (!fit_image_info[IMAGE_ID_DM_FW].image_len &&
!(size > 0 && valid_elf_image(loadaddr))) {
debug("Shutting down...\n");
release_resources_for_core_shutdown();
@ -218,13 +246,54 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
asm volatile("wfe");
}
image_entry_noargs_t image_entry =
(image_entry_noargs_t)load_elf_image_phdr(loadaddr);
if (!fit_image_info[IMAGE_ID_DM_FW].image_start) {
loadaddr = load_elf_image_phdr(loadaddr);
} else {
loadaddr = fit_image_info[IMAGE_ID_DM_FW].image_start;
if (valid_elf_image(loadaddr))
loadaddr = load_elf_image_phdr(loadaddr);
}
debug("%s: jumping to address %x\n", __func__, loadaddr);
image_entry_noargs_t image_entry = (image_entry_noargs_t)loadaddr;
image_entry();
}
#endif
#if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS)
void board_fit_image_post_process(const void *fit, int node, void **p_image,
size_t *p_size)
{
#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
int len;
int i;
const char *os;
u32 addr;
os = fdt_getprop(fit, node, "os", &len);
addr = fdt_getprop_u32_default_node(fit, node, 0, "entry", -1);
debug("%s: processing image: addr=%x, size=%d, os=%s\n", __func__,
addr, *p_size, os);
for (i = 0; i < IMAGE_AMT; i++) {
if (!strcmp(os, image_os_match[i])) {
fit_image_info[i].image_start = addr;
fit_image_info[i].image_len = *p_size;
debug("%s: matched image for ID %d\n", __func__, i);
break;
}
}
#endif
#if IS_ENABLED(CONFIG_TI_SECURE_DEVICE)
ti_secure_image_post_process(p_image, p_size);
#endif
}
#endif
#if defined(CONFIG_OF_LIBFDT)
int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name)
{

1
arch/arm/mach-k3/common.h
View file

@ -28,3 +28,4 @@ void k3_sysfw_print_ver(void);
void spl_enable_dcache(void);
void mmr_unlock(phys_addr_t base, u32 partition);
bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data);
void ti_secure_image_post_process(void **p_image, size_t *p_size);

5
arch/arm/mach-k3/config.mk
View file

@ -49,6 +49,10 @@ endif
ifdef CONFIG_ARM64
ifeq ($(CONFIG_SOC_K3_J721E),)
export DM := /dev/null
endif
ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
SPL_ITS := u-boot-spl-k3_HS.its
$(SPL_ITS): export IS_HS=1
@ -67,6 +71,7 @@ endif
quiet_cmd_k3_mkits = MKITS $@
cmd_k3_mkits = \
$(srctree)/tools/k3_fit_atf.sh \
$(CONFIG_K3_ATF_LOAD_ADDR) \
$(patsubst %,$(obj)/dts/%.dtb,$(subst ",,$(LIST_OF_DTB))) > $@
$(SPL_ITS): FORCE

11
arch/arm/mach-k3/include/mach/am64_hardware.h
View file

@ -7,8 +7,6 @@
#ifndef __ASM_ARCH_AM64_HARDWARE_H
#define __ASM_ARCH_AM64_HARDWARE_H
#include <config.h>
#define CTRL_MMR0_BASE 0x43000000
#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
@ -30,6 +28,11 @@
#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2
#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x04
#define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT 1
#define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK 0x02
#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01
/*
* The CTRL_MMR and PADCFG_MMR memory space is divided into several
* equally-spaced partitions, so defining the partition size allows us to
@ -49,7 +52,7 @@
#define ROM_ENTENDED_BOOT_DATA_INFO 0x701beb00
/* Use Last 1K as Scratch pad */
#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x701bfc00
/* Use Last 2K as Scratch pad */
#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x7019f800
#endif /* __ASM_ARCH_DRA8_HARDWARE_H */

6
arch/arm/mach-k3/include/mach/am64_spl.h
View file

@ -19,7 +19,8 @@
#define BOOT_DEVICE_MMC 0x08
#define BOOT_DEVICE_EMMC 0x09
#define BOOT_DEVICE_USB 0x0A
#define BOOT_DEVICE_USB 0x2A
#define BOOT_DEVICE_DFU 0x0A
#define BOOT_DEVICE_GPMC_NOR 0x0C
#define BOOT_DEVICE_PCIE 0x0D
#define BOOT_DEVICE_XSPI 0x0E
@ -32,12 +33,13 @@
#define BOOT_DEVICE_MMC2_2 0x1F
/* Backup BootMode devices */
#define BACKUP_BOOT_DEVICE_USB 0x01
#define BACKUP_BOOT_DEVICE_DFU 0x01
#define BACKUP_BOOT_DEVICE_UART 0x03
#define BACKUP_BOOT_DEVICE_ETHERNET 0x04
#define BACKUP_BOOT_DEVICE_MMC 0x05
#define BACKUP_BOOT_DEVICE_SPI 0x06
#define BACKUP_BOOT_DEVICE_I2C 0x07
#define BACKUP_BOOT_DEVICE_USB 0x09
#define K3_PRIMARY_BOOTMODE 0x0

5
arch/arm/mach-k3/j7200/Makefile Normal file
View file

@ -0,0 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
obj-y += clk-data.o
obj-y += dev-data.o

547
arch/arm/mach-k3/j7200/clk-data.c Normal file
View file

@ -0,0 +1,547 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* J7200 specific clock platform data
*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
*/
#include "k3-clk.h"
static const char * const gluelogic_hfosc0_clkout_parents[] = {
"osc_19_2_mhz",
"osc_20_mhz",
"osc_24_mhz",
"osc_25_mhz",
"osc_26_mhz",
"osc_27_mhz",
};
static const char * const mcu_ospi0_iclk_sel_out0_parents[] = {
"board_0_mcu_ospi0_dqs_out",
"fss_mcu_0_ospi_0_ospi_oclk_clk",
};
static const char * const wkup_fref_clksel_out0_parents[] = {
"gluelogic_hfosc0_clkout",
"j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
};
static const char * const main_pll_hfosc_sel_out1_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = {
"wkup_fref_clksel_out0",
"hsdiv1_16fft_mcu_0_hsdivout0_clk",
};
static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = {
"hsdiv4_16fft_mcu_1_hsdivout4_clk",
"hsdiv4_16fft_mcu_2_hsdivout4_clk",
};
static const char * const mcuusart_clk_sel_out0_parents[] = {
"hsdiv4_16fft_mcu_1_hsdivout3_clk",
"postdiv2_16fft_main_1_hsdivout5_clk",
};
static const char * const wkup_gpio0_clksel_out0_parents[] = {
"k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
"k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
"j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
"j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
};
static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = {
"hsdiv4_16fft_mcu_1_hsdivout3_clk",
"gluelogic_hfosc0_clkout",
};
static const char * const main_pll_hfosc_sel_out0_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out12_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out14_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out2_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out3_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out4_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out7_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out8_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const usb0_refclk_sel_out0_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const wkup_obsclk_mux_out0_parents[] = {
"j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
NULL,
"hsdiv1_16fft_mcu_0_hsdivout0_clk",
"hsdiv1_16fft_mcu_0_hsdivout0_clk",
"hsdiv4_16fft_mcu_1_hsdivout1_clk",
"hsdiv4_16fft_mcu_1_hsdivout2_clk",
"hsdiv4_16fft_mcu_1_hsdivout3_clk",
"hsdiv4_16fft_mcu_1_hsdivout4_clk",
"hsdiv4_16fft_mcu_2_hsdivout0_clk",
"j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
"hsdiv4_16fft_mcu_2_hsdivout1_clk",
"hsdiv4_16fft_mcu_2_hsdivout2_clk",
"hsdiv4_16fft_mcu_2_hsdivout3_clk",
"hsdiv4_16fft_mcu_2_hsdivout4_clk",
"gluelogic_hfosc0_clkout",
"board_0_wkup_lf_clkin_out",
};
static const char * const main_pll4_xref_sel_out0_parents[] = {
"main_pll_hfosc_sel_out4",
"board_0_ext_refclk1_out",
};
static const char * const mcu_clkout_mux_out0_parents[] = {
"hsdiv4_16fft_mcu_2_hsdivout0_clk",
"hsdiv4_16fft_mcu_2_hsdivout0_clk",
};
static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
"main_pll_hfosc_sel_out0",
"hsdiv4_16fft_main_0_hsdivout0_clk",
};
static const char * const mcu_obsclk_outmux_out0_parents[] = {
"mcu_obsclk_div_out0",
"gluelogic_hfosc0_clkout",
};
static const char * const clkout_mux_out0_parents[] = {
"hsdiv4_16fft_main_3_hsdivout0_clk",
"hsdiv4_16fft_main_3_hsdivout0_clk",
};
static const char * const emmcsd_refclk_sel_out0_parents[] = {
"hsdiv4_16fft_main_0_hsdivout2_clk",
"hsdiv4_16fft_main_1_hsdivout2_clk",
"hsdiv4_16fft_main_3_hsdivout2_clk",
"hsdiv4_16fft_main_3_hsdivout2_clk",
};
static const char * const emmcsd_refclk_sel_out1_parents[] = {
"hsdiv4_16fft_main_0_hsdivout2_clk",
"hsdiv4_16fft_main_1_hsdivout2_clk",
"hsdiv4_16fft_main_3_hsdivout2_clk",
"hsdiv4_16fft_main_3_hsdivout2_clk",
};
static const char * const gtc_clk_mux_out0_parents[] = {
"hsdiv4_16fft_main_3_hsdivout1_clk",
"postdiv2_16fft_main_0_hsdivout6_clk",
"board_0_mcu_cpts0_rft_clk_out",
"board_0_cpts0_rft_clk_out",
"board_0_mcu_ext_refclk0_out",
"board_0_ext_refclk1_out",
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
"hsdiv4_16fft_mcu_2_hsdivout1_clk",
"k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
};
static const char * const obsclk1_mux_out0_parents[] = {
NULL,
"hsdiv0_16fft_main_8_hsdivout0_clk",
NULL,
NULL,
};
static const char * const gpmc_fclk_sel_out0_parents[] = {
"hsdiv4_16fft_main_0_hsdivout3_clk",
"hsdiv4_16fft_main_2_hsdivout1_clk",
"hsdiv4_16fft_main_2_hsdivout1_clk",
"k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
};
static const char * const audio_refclko_mux_out0_parents[] = {
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
"hsdiv2_16fft_main_4_hsdivout2_clk",
NULL,
NULL,
NULL,
};
static const char * const audio_refclko_mux_out1_parents[] = {
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
"hsdiv2_16fft_main_4_hsdivout2_clk",
NULL,
NULL,
NULL,
};
static const char * const obsclk0_mux_out0_parents[] = {
"hsdiv4_16fft_main_0_hsdivout0_clk",
"hsdiv4_16fft_main_1_hsdivout0_clk",
"hsdiv4_16fft_main_2_hsdivout0_clk",
"hsdiv4_16fft_main_3_hsdivout0_clk",
"hsdiv2_16fft_main_4_hsdivout0_clk",
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
"hsdiv0_16fft_main_12_hsdivout0_clk",
"obsclk1_mux_out0",
"hsdiv1_16fft_main_14_hsdivout0_clk",
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
"j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
"board_0_wkup_lf_clkin_out",
"hsdiv4_16fft_main_0_hsdivout0_clk",
"board_0_hfosc1_clk_out",
"gluelogic_hfosc0_clkout",
};
static const struct clk_data clk_list[] = {
CLK_FIXED_RATE("osc_27_mhz", 27000000, 0),
CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
CLK_FIXED_RATE("osc_20_mhz", 20000000, 0),
CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0),
CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
CLK_FIXED_RATE("j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", 12500000, 0),
CLK_FIXED_RATE("j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", 32550, 0),
CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 2, 0x40f08030, 4, 1, 0),
CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0),
CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000),
CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x680038, 24, 3, 0),
CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0),
CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0),
CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000),
CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000),
CLK_DIV("postdiv2_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0),
CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0),
CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 166666666),
CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0),
CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0),
CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
CLK_MUX("mcuusart_clk_sel_out0", mcuusart_clk_sel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0),
CLK_MUX("wkup_i2c0_mcupll_bypass_clksel_out0", wkup_i2c0_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out14", main_pll_hfosc_sel_out14_parents, 2, 0x430080b8, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 2, 0x43008088, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 2, 0x4300808c, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out4", main_pll_hfosc_sel_out4_parents, 2, 0x43008090, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 2, 0x4300809c, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 2, 0x430080a0, 0, 1, 0),
CLK_MUX("usb0_refclk_sel_out0", usb0_refclk_sel_out0_parents, 2, 0x1080e0, 0, 1, 0),
CLK_FIXED_RATE("board_0_cpts0_rft_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
CLK_FIXED_RATE("board_0_mcu_cpts0_rft_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
CLK_FIXED_RATE("board_0_mcu_i2c0_scl_out", 0, 0),
CLK_FIXED_RATE("board_0_wkup_lf_clkin_out", 0, 0),
CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 192000000),
CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01084, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout2_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01088, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout2_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02088, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout3_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d0208c, 0, 7, 0),
CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0),
CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 24, 3, 0),
CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0),
CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0),
CLK_PLL("pllfracf_ssmod_16fft_main_14_foutvcop_clk", "main_pll_hfosc_sel_out14", 0x68e000, 0),
CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0),
CLK_PLL("pllfracf_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0),
CLK_PLL("pllfracf_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0),
CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0),
CLK_DIV("postdiv2_16fft_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0),
CLK_DIV("postdiv2_16fft_main_1_hsdivout7_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0),
CLK_MUX("wkup_obsclk_mux_out0", wkup_obsclk_mux_out0_parents, 16, 0x43008000, 0, 4, 0),
CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0),
CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0),
CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 48000000),
CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0),
CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0),
CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0),
CLK_DIV("hsdiv1_16fft_main_14_hsdivout0_clk", "pllfracf_ssmod_16fft_main_14_foutvcop_clk", 0x68e080, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_main_2_hsdivout0_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682080, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_main_3_hsdivout0_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683080, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0),
CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0),
CLK_DIV("mcu_obsclk_div_out0", "wkup_obsclk_mux_out0", 0x43008000, 8, 4, 0),
CLK_MUX("mcu_obsclk_outmux_out0", mcu_obsclk_outmux_out0_parents, 2, 0x43008000, 24, 1, 0),
CLK_PLL("pllfracf_ssmod_16fft_main_4_foutvcop_clk", "main_pll4_xref_sel_out0", 0x684000, 0),
CLK_MUX("clkout_mux_out0", clkout_mux_out0_parents, 2, 0x108010, 0, 1, 0),
CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0),
CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0),
CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0),
CLK_MUX("obsclk1_mux_out0", obsclk1_mux_out0_parents, 4, 0x108004, 0, 2, 0),
CLK_MUX("gpmc_fclk_sel_out0", gpmc_fclk_sel_out0_parents, 4, 0x1080d0, 0, 2, 0),
CLK_DIV("hsdiv2_16fft_main_4_hsdivout0_clk", "pllfracf_ssmod_16fft_main_4_foutvcop_clk", 0x684080, 0, 7, 0),
CLK_DIV("hsdiv2_16fft_main_4_hsdivout2_clk", "pllfracf_ssmod_16fft_main_4_foutvcop_clk", 0x684088, 0, 7, 0),
CLK_MUX("audio_refclko_mux_out0", audio_refclko_mux_out0_parents, 32, 0x1082e0, 0, 5, 0),
CLK_MUX("audio_refclko_mux_out1", audio_refclko_mux_out1_parents, 32, 0x1082e4, 0, 5, 0),
CLK_MUX("obsclk0_mux_out0", obsclk0_mux_out0_parents, 32, 0x108000, 0, 5, 0),
CLK_DIV("osbclk0_div_out0", "obsclk0_mux_out0", 0x108000, 8, 8, 0),
CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0),
CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0),
};
static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(8, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(8, 5, "hsdiv0_16fft_main_12_hsdivout0_clk"),
DEV_CLK(30, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(30, 1, "board_0_hfosc1_clk_out"),
DEV_CLK(30, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
DEV_CLK(30, 4, "hsdiv4_16fft_main_0_hsdivout1_clk"),
DEV_CLK(30, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(30, 6, "gluelogic_hfosc0_clkout"),
DEV_CLK(30, 7, "hsdiv4_16fft_main_0_hsdivout2_clk"),
DEV_CLK(30, 8, "hsdiv4_16fft_main_0_hsdivout4_clk"),
DEV_CLK(30, 9, "gluelogic_hfosc0_clkout"),
DEV_CLK(30, 10, "board_0_hfosc1_clk_out"),
DEV_CLK(30, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(30, 12, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(61, 1, "gtc_clk_mux_out0"),
DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"),
DEV_CLK(61, 3, "postdiv2_16fft_main_0_hsdivout6_clk"),
DEV_CLK(61, 4, "board_0_mcu_cpts0_rft_clk_out"),
DEV_CLK(61, 5, "board_0_cpts0_rft_clk_out"),
DEV_CLK(61, 6, "board_0_mcu_ext_refclk0_out"),
DEV_CLK(61, 7, "board_0_ext_refclk1_out"),
DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(91, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(91, 3, "emmcsd_refclk_sel_out0"),
DEV_CLK(91, 4, "hsdiv4_16fft_main_0_hsdivout2_clk"),
DEV_CLK(91, 5, "hsdiv4_16fft_main_1_hsdivout2_clk"),
DEV_CLK(91, 6, "hsdiv4_16fft_main_3_hsdivout2_clk"),
DEV_CLK(91, 7, "hsdiv4_16fft_main_3_hsdivout2_clk"),
DEV_CLK(92, 0, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(92, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(92, 2, "emmcsd_refclk_sel_out1"),
DEV_CLK(92, 3, "hsdiv4_16fft_main_0_hsdivout2_clk"),
DEV_CLK(92, 4, "hsdiv4_16fft_main_1_hsdivout2_clk"),
DEV_CLK(92, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"),
DEV_CLK(92, 6, "hsdiv4_16fft_main_3_hsdivout2_clk"),
DEV_CLK(102, 1, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
DEV_CLK(102, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
DEV_CLK(102, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(102, 5, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
DEV_CLK(102, 7, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
DEV_CLK(103, 0, "mcu_ospi_ref_clk_sel_out0"),
DEV_CLK(103, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
DEV_CLK(103, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
DEV_CLK(103, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(103, 4, "board_0_mcu_ospi0_dqs_out"),
DEV_CLK(103, 5, "mcu_ospi0_iclk_sel_out0"),
DEV_CLK(103, 6, "board_0_mcu_ospi0_dqs_out"),
DEV_CLK(103, 7, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
DEV_CLK(103, 8, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(104, 0, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
DEV_CLK(104, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(104, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(113, 0, "wkup_gpio0_clksel_out0"),
DEV_CLK(113, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(113, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(113, 3, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk"),
DEV_CLK(113, 4, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
DEV_CLK(133, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(133, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(138, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(138, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(146, 2, "usart_programmable_clock_divider_out0"),
DEV_CLK(146, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(149, 2, "mcuusart_clk_sel_out0"),
DEV_CLK(149, 3, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
DEV_CLK(149, 4, "postdiv2_16fft_main_1_hsdivout5_clk"),
DEV_CLK(149, 5, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(154, 0, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
DEV_CLK(154, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(154, 2, "gluelogic_hfosc0_clkout"),
DEV_CLK(157, 5, "osbclk0_div_out0"),
DEV_CLK(157, 7, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
DEV_CLK(157, 14, "mcu_obsclk_outmux_out0"),
DEV_CLK(157, 15, "mcu_obsclk_div_out0"),
DEV_CLK(157, 16, "gluelogic_hfosc0_clkout"),
DEV_CLK(157, 35, "clkout_mux_out0"),
DEV_CLK(157, 36, "hsdiv4_16fft_main_3_hsdivout0_clk"),
DEV_CLK(157, 37, "hsdiv4_16fft_main_3_hsdivout0_clk"),
DEV_CLK(157, 38, "osbclk0_div_out0"),
DEV_CLK(157, 57, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
DEV_CLK(157, 65, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(157, 69, "mcu_clkout_mux_out0"),
DEV_CLK(157, 70, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
DEV_CLK(157, 71, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
DEV_CLK(157, 77, "audio_refclko_mux_out1"),
DEV_CLK(157, 106, "hsdiv2_16fft_main_4_hsdivout2_clk"),
DEV_CLK(157, 110, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
DEV_CLK(157, 114, "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk"),
DEV_CLK(157, 123, "mshsi2c_wkup_0_porscl"),
DEV_CLK(157, 131, "audio_refclko_mux_out0"),
DEV_CLK(157, 160, "hsdiv2_16fft_main_4_hsdivout2_clk"),
DEV_CLK(157, 169, "board_0_mcu_i2c0_scl_out"),
DEV_CLK(157, 177, "k3_pll_ctrl_wrap_main_0_sysclkout_clk"),
DEV_CLK(157, 184, "gpmc_fclk_sel_out0"),
DEV_CLK(157, 187, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
DEV_CLK(157, 192, "osbclk0_div_out0"),
DEV_CLK(157, 193, "hsdiv4_16fft_main_0_hsdivout0_clk"),
DEV_CLK(157, 194, "hsdiv4_16fft_main_1_hsdivout0_clk"),
DEV_CLK(157, 195, "hsdiv4_16fft_main_2_hsdivout0_clk"),
DEV_CLK(157, 196, "hsdiv4_16fft_main_3_hsdivout0_clk"),
DEV_CLK(157, 197, "hsdiv2_16fft_main_4_hsdivout0_clk"),
DEV_CLK(157, 205, "hsdiv0_16fft_main_12_hsdivout0_clk"),
DEV_CLK(157, 206, "obsclk1_mux_out0"),
DEV_CLK(157, 207, "hsdiv1_16fft_main_14_hsdivout0_clk"),
DEV_CLK(157, 220, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
DEV_CLK(157, 221, "board_0_wkup_lf_clkin_out"),
DEV_CLK(157, 222, "hsdiv4_16fft_main_0_hsdivout0_clk"),
DEV_CLK(157, 223, "board_0_hfosc1_clk_out"),
DEV_CLK(157, 224, "gluelogic_hfosc0_clkout"),
DEV_CLK(197, 0, "board_0_wkup_i2c0_scl_out"),
DEV_CLK(197, 1, "wkup_i2c0_mcupll_bypass_clksel_out0"),
DEV_CLK(197, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"),
DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
DEV_CLK(288, 3, "postdiv2_16fft_main_1_hsdivout7_clk"),
DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(288, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(288, 12, "usb0_refclk_sel_out0"),
DEV_CLK(288, 13, "gluelogic_hfosc0_clkout"),
DEV_CLK(288, 14, "board_0_hfosc1_clk_out"),
DEV_CLK(288, 15, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(288, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
};
const struct ti_k3_clk_platdata j7200_clk_platdata = {
.clk_list = clk_list,
.clk_list_cnt = 108,
.soc_dev_clk_data = soc_dev_clk_data,
.soc_dev_clk_data_cnt = 127,
};

77
arch/arm/mach-k3/j7200/dev-data.c Normal file
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@ -0,0 +1,77 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* J7200 specific device platform data
*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
*/
#include "k3-dev.h"
static struct ti_psc soc_psc_list[] = {
[0] = PSC(0, 0x00400000),
[1] = PSC(1, 0x42000000),
};
static struct ti_pd soc_pd_list[] = {
[0] = PSC_PD(0, &soc_psc_list[0], NULL),
[1] = PSC_PD(2, &soc_psc_list[0], &soc_pd_list[5]),
[2] = PSC_PD(14, &soc_psc_list[0], NULL),
[3] = PSC_PD(15, &soc_psc_list[0], &soc_pd_list[2]),
[4] = PSC_PD(16, &soc_psc_list[0], &soc_pd_list[2]),
[5] = PSC_PD(0, &soc_psc_list[1], NULL),
};
static struct ti_lpsc soc_lpsc_list[] = {
[0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL),
[1] = PSC_LPSC(9, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[14]),
[2] = PSC_LPSC(14, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[3]),
[3] = PSC_LPSC(15, &soc_psc_list[0], &soc_pd_list[0], NULL),
[4] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], NULL),
[5] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], NULL),
[6] = PSC_LPSC(25, &soc_psc_list[0], &soc_pd_list[0], NULL),
[7] = PSC_LPSC(54, &soc_psc_list[0], &soc_pd_list[1], NULL),
[8] = PSC_LPSC(78, &soc_psc_list[0], &soc_pd_list[2], NULL),
[9] = PSC_LPSC(79, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]),
[10] = PSC_LPSC(80, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]),
[11] = PSC_LPSC(81, &soc_psc_list[0], &soc_pd_list[4], &soc_lpsc_list[8]),
[12] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[5], NULL),
[13] = PSC_LPSC(3, &soc_psc_list[1], &soc_pd_list[5], NULL),
[14] = PSC_LPSC(10, &soc_psc_list[1], &soc_pd_list[5], NULL),
[15] = PSC_LPSC(11, &soc_psc_list[1], &soc_pd_list[5], NULL),
[16] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[5], NULL),
};
static struct ti_dev soc_dev_list[] = {
PSC_DEV(30, &soc_lpsc_list[0]),
PSC_DEV(61, &soc_lpsc_list[1]),
PSC_DEV(90, &soc_lpsc_list[2]),
PSC_DEV(8, &soc_lpsc_list[3]),
PSC_DEV(288, &soc_lpsc_list[4]),
PSC_DEV(92, &soc_lpsc_list[5]),
PSC_DEV(91, &soc_lpsc_list[6]),
PSC_DEV(146, &soc_lpsc_list[7]),
PSC_DEV(4, &soc_lpsc_list[8]),
PSC_DEV(4, &soc_lpsc_list[9]),
PSC_DEV(202, &soc_lpsc_list[10]),
PSC_DEV(203, &soc_lpsc_list[11]),
PSC_DEV(102, &soc_lpsc_list[12]),
PSC_DEV(103, &soc_lpsc_list[12]),
PSC_DEV(104, &soc_lpsc_list[12]),
PSC_DEV(154, &soc_lpsc_list[12]),
PSC_DEV(149, &soc_lpsc_list[12]),
PSC_DEV(113, &soc_lpsc_list[13]),
PSC_DEV(197, &soc_lpsc_list[13]),
PSC_DEV(103, &soc_lpsc_list[14]),
PSC_DEV(104, &soc_lpsc_list[15]),
PSC_DEV(102, &soc_lpsc_list[16]),
};
const struct ti_k3_pd_platdata j7200_pd_platdata = {
.psc = soc_psc_list,
.pd = soc_pd_list,
.lpsc = soc_lpsc_list,
.devs = soc_dev_list,
.num_psc = 2,
.num_pd = 6,
.num_lpsc = 17,
.num_devs = 22,
};

5
arch/arm/mach-k3/j721e/Makefile Normal file
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@ -0,0 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
obj-y += clk-data.o
obj-y += dev-data.o

781
arch/arm/mach-k3/j721e/clk-data.c Normal file
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@ -0,0 +1,781 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* J721E specific clock platform data
*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
*/
#include "k3-clk.h"
static const char * const gluelogic_hfosc0_clkout_parents[] = {
"osc_19_2_mhz",
"osc_20_mhz",
"osc_24_mhz",
"osc_25_mhz",
"osc_26_mhz",
"osc_27_mhz",
};
static const char * const mcu_ospi0_iclk_sel_out0_parents[] = {
"board_0_mcu_ospi0_dqs_out",
"fss_mcu_0_ospi_0_ospi_oclk_clk",
};
static const char * const mcu_ospi1_iclk_sel_out0_parents[] = {
"board_0_mcu_ospi1_dqs_out",
"fss_mcu_0_ospi_1_ospi_oclk_clk",
};
static const char * const wkup_fref_clksel_out0_parents[] = {
"gluelogic_hfosc0_clkout",
"j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
};
static const char * const main_pll_hfosc_sel_out1_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = {
"wkup_fref_clksel_out0",
"hsdiv1_16fft_mcu_0_hsdivout0_clk",
};
static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = {
"hsdiv4_16fft_mcu_1_hsdivout4_clk",
"hsdiv4_16fft_mcu_2_hsdivout4_clk",
};
static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = {
"hsdiv4_16fft_mcu_1_hsdivout4_clk",
"hsdiv4_16fft_mcu_2_hsdivout4_clk",
};
static const char * const mcuusart_clk_sel_out0_parents[] = {
"hsdiv4_16fft_mcu_1_hsdivout3_clk",
"postdiv3_16fft_main_1_hsdivout5_clk",
};
static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = {
"hsdiv4_16fft_mcu_1_hsdivout3_clk",
"gluelogic_hfosc0_clkout",
};
static const char * const main_pll25_hfosc_sel_out0_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out0_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out12_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out13_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out14_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out15_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out16_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out17_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out18_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out19_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out2_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out23_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out3_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out4_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out5_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out6_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out7_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const main_pll_hfosc_sel_out8_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const usb0_refclk_sel_out0_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const usb1_refclk_sel_out0_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
};
static const char * const wkup_obsclk_mux_out0_parents[] = {
"j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
NULL,
"hsdiv1_16fft_mcu_0_hsdivout0_clk",
"hsdiv1_16fft_mcu_0_hsdivout0_clk",
"hsdiv4_16fft_mcu_1_hsdivout1_clk",
"hsdiv4_16fft_mcu_1_hsdivout2_clk",
"hsdiv4_16fft_mcu_1_hsdivout3_clk",
"hsdiv4_16fft_mcu_1_hsdivout4_clk",
"hsdiv4_16fft_mcu_2_hsdivout0_clk",
"j7_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
"hsdiv4_16fft_mcu_2_hsdivout1_clk",
"hsdiv4_16fft_mcu_2_hsdivout2_clk",
"hsdiv4_16fft_mcu_2_hsdivout3_clk",
"hsdiv4_16fft_mcu_2_hsdivout4_clk",
"gluelogic_hfosc0_clkout",
"gluelogic_lpxosc_clkout",
};
static const char * const main_pll15_xref_sel_out0_parents[] = {
"main_pll_hfosc_sel_out15",
"board_0_ext_refclk1_out",
};
static const char * const main_pll24_hfosc_sel_out0_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_mlb0_mlbcp_out",
};
static const char * const main_pll4_xref_sel_out0_parents[] = {
"main_pll_hfosc_sel_out4",
"board_0_ext_refclk1_out",
};
static const char * const mcu_clkout_mux_out0_parents[] = {
"hsdiv4_16fft_mcu_2_hsdivout0_clk",
"hsdiv4_16fft_mcu_2_hsdivout0_clk",
};
static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
"main_pll_hfosc_sel_out0",
"hsdiv4_16fft_main_0_hsdivout0_clk",
};
static const char * const mcu_obsclk_outmux_out0_parents[] = {
"mcu_obsclk_div_out0",
"gluelogic_hfosc0_clkout",
};
static const char * const obsclk1_mux_out0_parents[] = {
"hsdiv0_16fft_main_7_hsdivout0_clk",
"hsdiv0_16fft_main_8_hsdivout0_clk",
"hsdiv3_16fft_main_13_hsdivout0_clk",
NULL,
};
static const char * const clkout_mux_out0_parents[] = {
"hsdiv4_16fft_main_3_hsdivout0_clk",
"hsdiv4_16fft_main_3_hsdivout0_clk",
};
static const char * const emmcsd_refclk_sel_out0_parents[] = {
"hsdiv4_16fft_main_0_hsdivout2_clk",
"hsdiv4_16fft_main_1_hsdivout2_clk",
"hsdiv4_16fft_main_2_hsdivout2_clk",
"hsdiv4_16fft_main_3_hsdivout2_clk",
};
static const char * const emmcsd_refclk_sel_out1_parents[] = {
"hsdiv4_16fft_main_0_hsdivout2_clk",
"hsdiv4_16fft_main_1_hsdivout2_clk",
"hsdiv4_16fft_main_2_hsdivout2_clk",
"hsdiv4_16fft_main_3_hsdivout2_clk",
};
static const char * const gtc_clk_mux_out0_parents[] = {
"hsdiv4_16fft_main_3_hsdivout1_clk",
"postdiv3_16fft_main_0_hsdivout6_clk",
"board_0_mcu_cpts0_rft_clk_out",
"board_0_cpts0_rft_clk_out",
"board_0_mcu_ext_refclk0_out",
"board_0_ext_refclk1_out",
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
"hsdiv4_16fft_mcu_2_hsdivout1_clk",
"k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
};
static const char * const gpmc_fclk_sel_out0_parents[] = {
"hsdiv4_16fft_main_0_hsdivout3_clk",
"hsdiv4_16fft_main_2_hsdivout1_clk",
"hsdiv4_16fft_main_2_hsdivout1_clk",
"k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
};
static const char * const mcasp_ahclko_mux_out0_parents[] = {
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
"hsdiv3_16fft_main_4_hsdivout2_clk",
"hsdiv3_16fft_main_15_hsdivout2_clk",
NULL,
NULL,
"board_0_audio_ext_refclk0_out",
};
static const char * const mcasp_ahclko_mux_out1_parents[] = {
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
"hsdiv3_16fft_main_4_hsdivout2_clk",
"hsdiv3_16fft_main_15_hsdivout2_clk",
NULL,
NULL,
"board_0_audio_ext_refclk1_out",
};
static const char * const mcasp_ahclko_mux_out2_parents[] = {
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
"hsdiv3_16fft_main_4_hsdivout2_clk",
"hsdiv3_16fft_main_15_hsdivout2_clk",
NULL,
NULL,
"board_0_audio_ext_refclk2_out",
};
static const char * const mcasp_ahclko_mux_out3_parents[] = {
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
"hsdiv3_16fft_main_4_hsdivout2_clk",
"hsdiv3_16fft_main_15_hsdivout2_clk",
NULL,
NULL,
"board_0_audio_ext_refclk3_out",
};
static const char * const obsclk0_mux_out0_parents[] = {
"hsdiv4_16fft_main_0_hsdivout0_clk",
"hsdiv4_16fft_main_1_hsdivout0_clk",
"hsdiv4_16fft_main_2_hsdivout0_clk",
"hsdiv4_16fft_main_3_hsdivout0_clk",
"hsdiv3_16fft_main_4_hsdivout0_clk",
"hsdiv3_16fft_main_5_hsdivout0_clk",
"hsdiv0_16fft_main_6_hsdivout0_clk",
NULL,
NULL,
NULL,
NULL,
NULL,
"hsdiv0_16fft_main_12_hsdivout0_clk",
"obsclk1_mux_out0",
"hsdiv1_16fft_main_14_hsdivout0_clk",
"hsdiv3_16fft_main_15_hsdivout0_clk",
"hsdiv1_16fft_main_16_hsdivout0_clk",
"hsdiv1_16fft_main_17_hsdivout0_clk",
"hsdiv1_16fft_main_18_hsdivout0_clk",
"hsdiv1_16fft_main_19_hsdivout0_clk",
NULL,
NULL,
NULL,
"hsdiv1_16fft_main_23_hsdivout0_clk",
"hsdiv0_16fft_main_24_hsdivout0_clk",
"hsdiv1_16fft_main_25_hsdivout0_clk",
NULL,
"j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
"gluelogic_lpxosc_clkout",
"hsdiv4_16fft_main_0_hsdivout0_clk",
"board_0_hfosc1_clk_out",
"gluelogic_hfosc0_clkout",
};
static const struct clk_data clk_list[] = {
CLK_FIXED_RATE("osc_27_mhz", 27000000, 0),
CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
CLK_FIXED_RATE("osc_20_mhz", 20000000, 0),
CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0),
CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0),
CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
CLK_FIXED_RATE("fss_mcu_0_ospi_1_ospi_oclk_clk", 0, 0),
CLK_FIXED_RATE("j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", 12500000, 0),
CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 2, 0x40f08030, 4, 1, 0),
CLK_MUX("mcu_ospi1_iclk_sel_out0", mcu_ospi1_iclk_sel_out0_parents, 2, 0x40f08034, 4, 1, 0),
CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0),
CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000),
CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x680038, 24, 3, 0),
CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0),
CLK_PLL("pllfrac2_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0),
CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000),
CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000),
CLK_DIV("postdiv3_16fft_main_1_hsdivout5_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0),
CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfrac2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0),
CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 166666666),
CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0),
CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0),
CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0),
CLK_MUX("mcuusart_clk_sel_out0", mcuusart_clk_sel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
CLK_MUX("wkup_i2c0_mcupll_bypass_clksel_out0", wkup_i2c0_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0),
CLK_FIXED_RATE("gluelogic_lpxosc_clkout", 32768, 0),
CLK_MUX("main_pll25_hfosc_sel_out0", main_pll25_hfosc_sel_out0_parents, 2, 0x430080e4, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out13", main_pll_hfosc_sel_out13_parents, 2, 0x430080b4, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out14", main_pll_hfosc_sel_out14_parents, 2, 0x430080b8, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out15", main_pll_hfosc_sel_out15_parents, 2, 0x430080bc, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out16", main_pll_hfosc_sel_out16_parents, 2, 0x430080c0, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out17", main_pll_hfosc_sel_out17_parents, 2, 0x430080c4, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out18", main_pll_hfosc_sel_out18_parents, 2, 0x430080c8, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out19", main_pll_hfosc_sel_out19_parents, 2, 0x430080cc, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 2, 0x43008088, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out23", main_pll_hfosc_sel_out23_parents, 2, 0x430080dc, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 2, 0x4300808c, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out4", main_pll_hfosc_sel_out4_parents, 2, 0x43008090, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out5", main_pll_hfosc_sel_out5_parents, 2, 0x43008094, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out6", main_pll_hfosc_sel_out6_parents, 2, 0x43008098, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 2, 0x4300809c, 0, 1, 0),
CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 2, 0x430080a0, 0, 1, 0),
CLK_MUX("usb0_refclk_sel_out0", usb0_refclk_sel_out0_parents, 2, 0x1080e0, 0, 1, 0),
CLK_MUX("usb1_refclk_sel_out0", usb1_refclk_sel_out0_parents, 2, 0x1080e4, 0, 1, 0),
CLK_FIXED_RATE("board_0_audio_ext_refclk0_out", 0, 0),
CLK_FIXED_RATE("board_0_audio_ext_refclk1_out", 0, 0),
CLK_FIXED_RATE("board_0_audio_ext_refclk2_out", 0, 0),
CLK_FIXED_RATE("board_0_audio_ext_refclk3_out", 0, 0),
CLK_FIXED_RATE("board_0_cpts0_rft_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
CLK_FIXED_RATE("board_0_mcu_cpts0_rft_clk_out", 0, 0),
CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
CLK_FIXED_RATE("board_0_mlb0_mlbcp_out", 0, 0),
CLK_FIXED_RATE("ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck", 0, 0),
CLK_FIXED_RATE("ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck_n", 0, 0),
CLK_FIXED_RATE("emmc8ss_16ffc_main_0_emmcss_io_clk", 0, 0),
CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 192000000),
CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout1_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01084, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout2_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01088, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout2_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02088, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout3_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d0208c, 0, 7, 0),
CLK_FIXED_RATE("j7_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", 32000, 0),
CLK_PLL("pllfrac2_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0),
CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 24, 3, 0),
CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0),
CLK_PLL("pllfrac2_ssmod_16fft_main_13_foutvcop_clk", "main_pll_hfosc_sel_out13", 0x68d000, 0),
CLK_PLL("pllfrac2_ssmod_16fft_main_14_foutvcop_clk", "main_pll_hfosc_sel_out14", 0x68e000, 0),
CLK_PLL("pllfrac2_ssmod_16fft_main_16_foutvcop_clk", "main_pll_hfosc_sel_out16", 0x690000, 0),
CLK_PLL("pllfrac2_ssmod_16fft_main_17_foutvcop_clk", "main_pll_hfosc_sel_out17", 0x691000, 0),
CLK_PLL("pllfrac2_ssmod_16fft_main_18_foutvcop_clk", "main_pll_hfosc_sel_out18", 0x692000, 0),
CLK_PLL("pllfrac2_ssmod_16fft_main_19_foutvcop_clk", "main_pll_hfosc_sel_out19", 0x693000, 0),
CLK_PLL("pllfrac2_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0),
CLK_PLL("pllfrac2_ssmod_16fft_main_23_foutvcop_clk", "main_pll_hfosc_sel_out23", 0x697000, 0),
CLK_PLL("pllfrac2_ssmod_16fft_main_25_foutvcop_clk", "main_pll25_hfosc_sel_out0", 0x699000, 0),
CLK_PLL("pllfrac2_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0),
CLK_PLL("pllfrac2_ssmod_16fft_main_5_foutvcop_clk", "main_pll_hfosc_sel_out5", 0x685000, 0),
CLK_PLL("pllfrac2_ssmod_16fft_main_6_foutvcop_clk", "main_pll_hfosc_sel_out6", 0x686000, 0),
CLK_PLL("pllfrac2_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0),
CLK_PLL("pllfrac2_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0),
CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0),
CLK_DIV("postdiv3_16fft_main_0_hsdivout6_clk", "pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0),
CLK_DIV("postdiv3_16fft_main_1_hsdivout7_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0),
CLK_MUX("wkup_obsclk_mux_out0", wkup_obsclk_mux_out0_parents, 16, 0x43008000, 0, 4, 0),
CLK_MUX("main_pll15_xref_sel_out0", main_pll15_xref_sel_out0_parents, 2, 0x430080bc, 4, 1, 0),
CLK_MUX("main_pll24_hfosc_sel_out0", main_pll24_hfosc_sel_out0_parents, 2, 0x430080e0, 0, 1, 0),
CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0),
CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0),
CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 48000000),
CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0),
CLK_DIV("hsdiv0_16fft_main_6_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_6_foutvcop_clk", 0x686080, 0, 7, 0),
CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0),
CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0),
CLK_DIV("hsdiv1_16fft_main_14_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_14_foutvcop_clk", 0x68e080, 0, 7, 0),
CLK_DIV("hsdiv1_16fft_main_16_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_16_foutvcop_clk", 0x690080, 0, 7, 0),
CLK_DIV("hsdiv1_16fft_main_17_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_17_foutvcop_clk", 0x691080, 0, 7, 0),
CLK_DIV("hsdiv1_16fft_main_18_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_18_foutvcop_clk", 0x692080, 0, 7, 0),
CLK_DIV("hsdiv1_16fft_main_19_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_19_foutvcop_clk", 0x693080, 0, 7, 0),
CLK_DIV("hsdiv1_16fft_main_23_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_23_foutvcop_clk", 0x697080, 0, 7, 0),
CLK_DIV("hsdiv1_16fft_main_25_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_25_foutvcop_clk", 0x699080, 0, 7, 0),
CLK_DIV("hsdiv3_16fft_main_13_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_13_foutvcop_clk", 0x68d080, 0, 7, 0),
CLK_DIV("hsdiv3_16fft_main_5_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_5_foutvcop_clk", 0x685080, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_main_2_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682080, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_main_3_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683080, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0),
CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0),
CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0),
CLK_DIV("mcu_obsclk_div_out0", "wkup_obsclk_mux_out0", 0x43008000, 8, 4, 0),
CLK_MUX("mcu_obsclk_outmux_out0", mcu_obsclk_outmux_out0_parents, 2, 0x43008000, 24, 1, 0),
CLK_MUX("obsclk1_mux_out0", obsclk1_mux_out0_parents, 4, 0x108004, 0, 2, 0),
CLK_PLL("pllfrac2_ssmod_16fft_main_15_foutvcop_clk", "main_pll15_xref_sel_out0", 0x68f000, 0),
CLK_PLL("pllfrac2_ssmod_16fft_main_4_foutvcop_clk", "main_pll4_xref_sel_out0", 0x684000, 0),
CLK_MUX("clkout_mux_out0", clkout_mux_out0_parents, 2, 0x108010, 0, 1, 0),
CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0),
CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0),
CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0),
CLK_MUX("gpmc_fclk_sel_out0", gpmc_fclk_sel_out0_parents, 4, 0x1080d0, 0, 2, 0),
CLK_DIV("hsdiv0_16fft_main_24_hsdivout0_clk", "plldeskew_16fft_main_24_foutp_clk", 0x698080, 0, 0, 0),
CLK_DIV("hsdiv3_16fft_main_15_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0),
CLK_DIV("hsdiv3_16fft_main_15_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_15_foutvcop_clk", 0x68f088, 0, 7, 0),
CLK_DIV("hsdiv3_16fft_main_4_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_4_foutvcop_clk", 0x684080, 0, 7, 0),
CLK_DIV("hsdiv3_16fft_main_4_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_4_foutvcop_clk", 0x684088, 0, 7, 0),
CLK_MUX("mcasp_ahclko_mux_out0", mcasp_ahclko_mux_out0_parents, 33, 0x1082e0, 0, 5, 0),
CLK_MUX("mcasp_ahclko_mux_out1", mcasp_ahclko_mux_out1_parents, 33, 0x1082e4, 0, 5, 0),
CLK_MUX("mcasp_ahclko_mux_out2", mcasp_ahclko_mux_out2_parents, 33, 0x1082e8, 0, 5, 0),
CLK_MUX("mcasp_ahclko_mux_out3", mcasp_ahclko_mux_out3_parents, 33, 0x1082ec, 0, 5, 0),
CLK_MUX("obsclk0_mux_out0", obsclk0_mux_out0_parents, 32, 0x108000, 0, 5, 0),
CLK_DIV("osbclk0_div_out0", "obsclk0_mux_out0", 0x108000, 8, 8, 0),
CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0),
CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0),
};
static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(4, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
DEV_CLK(4, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"),
DEV_CLK(30, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(30, 1, "board_0_hfosc1_clk_out"),
DEV_CLK(30, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
DEV_CLK(30, 4, "hsdiv4_16fft_main_0_hsdivout1_clk"),
DEV_CLK(30, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(30, 6, "gluelogic_hfosc0_clkout"),
DEV_CLK(30, 7, "hsdiv4_16fft_main_0_hsdivout2_clk"),
DEV_CLK(30, 8, "hsdiv4_16fft_main_0_hsdivout4_clk"),
DEV_CLK(30, 9, "gluelogic_hfosc0_clkout"),
DEV_CLK(30, 10, "board_0_hfosc1_clk_out"),
DEV_CLK(30, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(30, 12, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
DEV_CLK(47, 0, "hsdiv0_16fft_main_7_hsdivout0_clk"),
DEV_CLK(47, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(47, 2, "hsdiv0_16fft_main_12_hsdivout0_clk"),
DEV_CLK(47, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(61, 1, "gtc_clk_mux_out0"),
DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"),
DEV_CLK(61, 3, "postdiv3_16fft_main_0_hsdivout6_clk"),
DEV_CLK(61, 4, "board_0_mcu_cpts0_rft_clk_out"),
DEV_CLK(61, 5, "board_0_cpts0_rft_clk_out"),
DEV_CLK(61, 6, "board_0_mcu_ext_refclk0_out"),
DEV_CLK(61, 7, "board_0_ext_refclk1_out"),
DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(91, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(91, 1, "emmcsd_refclk_sel_out0"),
DEV_CLK(91, 2, "hsdiv4_16fft_main_0_hsdivout2_clk"),
DEV_CLK(91, 3, "hsdiv4_16fft_main_1_hsdivout2_clk"),
DEV_CLK(91, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"),
DEV_CLK(91, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"),
DEV_CLK(92, 0, "emmcsd_refclk_sel_out1"),
DEV_CLK(92, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
DEV_CLK(92, 2, "hsdiv4_16fft_main_1_hsdivout2_clk"),
DEV_CLK(92, 3, "hsdiv4_16fft_main_2_hsdivout2_clk"),
DEV_CLK(92, 4, "hsdiv4_16fft_main_3_hsdivout2_clk"),
DEV_CLK(92, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(92, 6, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(102, 0, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
DEV_CLK(102, 1, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
DEV_CLK(102, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(102, 3, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
DEV_CLK(102, 4, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
DEV_CLK(103, 0, "mcu_ospi_ref_clk_sel_out0"),
DEV_CLK(103, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
DEV_CLK(103, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
DEV_CLK(103, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(103, 4, "mcu_ospi0_iclk_sel_out0"),
DEV_CLK(103, 5, "board_0_mcu_ospi0_dqs_out"),
DEV_CLK(103, 6, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
DEV_CLK(103, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(103, 8, "board_0_mcu_ospi0_dqs_out"),
DEV_CLK(104, 0, "mcu_ospi_ref_clk_sel_out1"),
DEV_CLK(104, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
DEV_CLK(104, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
DEV_CLK(104, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(104, 4, "mcu_ospi1_iclk_sel_out0"),
DEV_CLK(104, 5, "board_0_mcu_ospi1_dqs_out"),
DEV_CLK(104, 6, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
DEV_CLK(104, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(104, 8, "board_0_mcu_ospi1_dqs_out"),
DEV_CLK(113, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(133, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(133, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(138, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(138, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(146, 0, "usart_programmable_clock_divider_out0"),
DEV_CLK(146, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(149, 0, "mcuusart_clk_sel_out0"),
DEV_CLK(149, 1, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
DEV_CLK(149, 2, "postdiv3_16fft_main_1_hsdivout5_clk"),
DEV_CLK(149, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(154, 0, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
DEV_CLK(154, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(154, 2, "gluelogic_hfosc0_clkout"),
DEV_CLK(157, 18, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
DEV_CLK(157, 19, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
DEV_CLK(157, 21, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
DEV_CLK(157, 22, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
DEV_CLK(157, 42, "mshsi2c_wkup_0_porscl"),
DEV_CLK(157, 50, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
DEV_CLK(157, 51, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
DEV_CLK(157, 91, "ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck"),
DEV_CLK(157, 92, "ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck_n"),
DEV_CLK(157, 99, "emmc8ss_16ffc_main_0_emmcss_io_clk"),
DEV_CLK(157, 100, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
DEV_CLK(157, 104, "gpmc_fclk_sel_out0"),
DEV_CLK(157, 109, "hsdiv1_16fft_main_19_hsdivout0_clk"),
DEV_CLK(157, 111, "hsdiv1_16fft_main_23_hsdivout0_clk"),
DEV_CLK(157, 113, "osbclk0_div_out0"),
DEV_CLK(157, 114, "hsdiv4_16fft_main_0_hsdivout0_clk"),
DEV_CLK(157, 115, "hsdiv4_16fft_main_1_hsdivout0_clk"),
DEV_CLK(157, 116, "hsdiv4_16fft_main_2_hsdivout0_clk"),
DEV_CLK(157, 117, "hsdiv4_16fft_main_3_hsdivout0_clk"),
DEV_CLK(157, 118, "hsdiv3_16fft_main_4_hsdivout0_clk"),
DEV_CLK(157, 119, "hsdiv3_16fft_main_5_hsdivout0_clk"),
DEV_CLK(157, 120, "hsdiv0_16fft_main_6_hsdivout0_clk"),
DEV_CLK(157, 126, "hsdiv0_16fft_main_12_hsdivout0_clk"),
DEV_CLK(157, 127, "obsclk1_mux_out0"),
DEV_CLK(157, 128, "hsdiv1_16fft_main_14_hsdivout0_clk"),
DEV_CLK(157, 129, "hsdiv3_16fft_main_15_hsdivout0_clk"),
DEV_CLK(157, 130, "hsdiv1_16fft_main_16_hsdivout0_clk"),
DEV_CLK(157, 131, "hsdiv1_16fft_main_17_hsdivout0_clk"),
DEV_CLK(157, 132, "hsdiv1_16fft_main_18_hsdivout0_clk"),
DEV_CLK(157, 133, "hsdiv1_16fft_main_19_hsdivout0_clk"),
DEV_CLK(157, 137, "hsdiv1_16fft_main_23_hsdivout0_clk"),
DEV_CLK(157, 138, "hsdiv0_16fft_main_24_hsdivout0_clk"),
DEV_CLK(157, 139, "hsdiv1_16fft_main_25_hsdivout0_clk"),
DEV_CLK(157, 141, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
DEV_CLK(157, 142, "gluelogic_lpxosc_clkout"),
DEV_CLK(157, 143, "hsdiv4_16fft_main_0_hsdivout0_clk"),
DEV_CLK(157, 144, "board_0_hfosc1_clk_out"),
DEV_CLK(157, 145, "gluelogic_hfosc0_clkout"),
DEV_CLK(157, 146, "obsclk1_mux_out0"),
DEV_CLK(157, 147, "hsdiv0_16fft_main_7_hsdivout0_clk"),
DEV_CLK(157, 148, "hsdiv0_16fft_main_8_hsdivout0_clk"),
DEV_CLK(157, 149, "hsdiv3_16fft_main_13_hsdivout0_clk"),
DEV_CLK(157, 152, "mcu_obsclk_outmux_out0"),
DEV_CLK(157, 153, "mcu_obsclk_div_out0"),
DEV_CLK(157, 154, "gluelogic_hfosc0_clkout"),
DEV_CLK(157, 169, "k3_pll_ctrl_wrap_main_0_sysclkout_clk"),
DEV_CLK(157, 170, "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk"),
DEV_CLK(157, 172, "clkout_mux_out0"),
DEV_CLK(157, 173, "hsdiv4_16fft_main_3_hsdivout0_clk"),
DEV_CLK(157, 174, "hsdiv4_16fft_main_3_hsdivout0_clk"),
DEV_CLK(157, 175, "mcu_clkout_mux_out0"),
DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
DEV_CLK(157, 177, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
DEV_CLK(157, 301, "mcasp_ahclko_mux_out0"),
DEV_CLK(157, 330, "hsdiv3_16fft_main_4_hsdivout2_clk"),
DEV_CLK(157, 331, "hsdiv3_16fft_main_15_hsdivout2_clk"),
DEV_CLK(157, 334, "board_0_audio_ext_refclk0_out"),
DEV_CLK(157, 336, "mcasp_ahclko_mux_out1"),
DEV_CLK(157, 365, "hsdiv3_16fft_main_4_hsdivout2_clk"),
DEV_CLK(157, 366, "hsdiv3_16fft_main_15_hsdivout2_clk"),
DEV_CLK(157, 369, "board_0_audio_ext_refclk1_out"),
DEV_CLK(157, 371, "mcasp_ahclko_mux_out2"),
DEV_CLK(157, 400, "hsdiv3_16fft_main_4_hsdivout2_clk"),
DEV_CLK(157, 401, "hsdiv3_16fft_main_15_hsdivout2_clk"),
DEV_CLK(157, 404, "board_0_audio_ext_refclk2_out"),
DEV_CLK(157, 406, "mcasp_ahclko_mux_out3"),
DEV_CLK(157, 435, "hsdiv3_16fft_main_4_hsdivout2_clk"),
DEV_CLK(157, 436, "hsdiv3_16fft_main_15_hsdivout2_clk"),
DEV_CLK(157, 439, "board_0_audio_ext_refclk3_out"),
DEV_CLK(197, 0, "wkup_i2c0_mcupll_bypass_clksel_out0"),
DEV_CLK(197, 1, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
DEV_CLK(197, 2, "gluelogic_hfosc0_clkout"),
DEV_CLK(197, 3, "board_0_wkup_i2c0_scl_out"),
DEV_CLK(197, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"),
DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
DEV_CLK(288, 3, "postdiv3_16fft_main_1_hsdivout7_clk"),
DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(288, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(288, 15, "usb0_refclk_sel_out0"),
DEV_CLK(288, 16, "gluelogic_hfosc0_clkout"),
DEV_CLK(288, 17, "board_0_hfosc1_clk_out"),
DEV_CLK(288, 18, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(288, 19, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(289, 3, "postdiv3_16fft_main_1_hsdivout7_clk"),
DEV_CLK(289, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(289, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(289, 15, "usb1_refclk_sel_out0"),
DEV_CLK(289, 16, "gluelogic_hfosc0_clkout"),
DEV_CLK(289, 17, "board_0_hfosc1_clk_out"),
DEV_CLK(289, 18, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(289, 19, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
};
const struct ti_k3_clk_platdata j721e_clk_platdata = {
.clk_list = clk_list,
.clk_list_cnt = 156,
.soc_dev_clk_data = soc_dev_clk_data,
.soc_dev_clk_data_cnt = 171,
};

75
arch/arm/mach-k3/j721e/dev-data.c Normal file
View file

@ -0,0 +1,75 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* J721E specific device platform data
*
* Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
*/
#include "k3-dev.h"
static struct ti_psc soc_psc_list[] = {
[0] = PSC(0, 0x00400000),
[1] = PSC(1, 0x42000000),
};
static struct ti_pd soc_pd_list[] = {
[0] = PSC_PD(0, &soc_psc_list[0], NULL),
[1] = PSC_PD(14, &soc_psc_list[0], NULL),
[2] = PSC_PD(15, &soc_psc_list[0], &soc_pd_list[1]),
[3] = PSC_PD(16, &soc_psc_list[0], &soc_pd_list[1]),
[4] = PSC_PD(0, &soc_psc_list[1], NULL),
};
static struct ti_lpsc soc_lpsc_list[] = {
[0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL),
[1] = PSC_LPSC(7, &soc_psc_list[0], &soc_pd_list[0], NULL),
[2] = PSC_LPSC(14, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[3]),
[3] = PSC_LPSC(15, &soc_psc_list[0], &soc_pd_list[0], NULL),
[4] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], NULL),
[5] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], NULL),
[6] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], NULL),
[7] = PSC_LPSC(25, &soc_psc_list[0], &soc_pd_list[0], NULL),
[8] = PSC_LPSC(78, &soc_psc_list[0], &soc_pd_list[1], NULL),
[9] = PSC_LPSC(80, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]),
[10] = PSC_LPSC(81, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]),
[11] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[4], NULL),
[12] = PSC_LPSC(3, &soc_psc_list[1], &soc_pd_list[4], NULL),
[13] = PSC_LPSC(10, &soc_psc_list[1], &soc_pd_list[4], NULL),
[14] = PSC_LPSC(11, &soc_psc_list[1], &soc_pd_list[4], NULL),
[15] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[4], NULL),
};
static struct ti_dev soc_dev_list[] = {
PSC_DEV(30, &soc_lpsc_list[0]),
PSC_DEV(61, &soc_lpsc_list[0]),
PSC_DEV(146, &soc_lpsc_list[1]),
PSC_DEV(90, &soc_lpsc_list[2]),
PSC_DEV(47, &soc_lpsc_list[3]),
PSC_DEV(288, &soc_lpsc_list[4]),
PSC_DEV(289, &soc_lpsc_list[5]),
PSC_DEV(92, &soc_lpsc_list[6]),
PSC_DEV(91, &soc_lpsc_list[7]),
PSC_DEV(4, &soc_lpsc_list[8]),
PSC_DEV(202, &soc_lpsc_list[9]),
PSC_DEV(203, &soc_lpsc_list[10]),
PSC_DEV(102, &soc_lpsc_list[11]),
PSC_DEV(103, &soc_lpsc_list[11]),
PSC_DEV(104, &soc_lpsc_list[11]),
PSC_DEV(154, &soc_lpsc_list[11]),
PSC_DEV(149, &soc_lpsc_list[11]),
PSC_DEV(113, &soc_lpsc_list[12]),
PSC_DEV(197, &soc_lpsc_list[12]),
PSC_DEV(103, &soc_lpsc_list[13]),
PSC_DEV(104, &soc_lpsc_list[14]),
PSC_DEV(102, &soc_lpsc_list[15]),
};
const struct ti_k3_pd_platdata j721e_pd_platdata = {
.psc = soc_psc_list,
.pd = soc_pd_list,
.lpsc = soc_lpsc_list,
.devs = soc_dev_list,
.num_psc = 2,
.num_pd = 5,
.num_lpsc = 16,
.num_devs = 22,
};

12
arch/arm/mach-k3/j721e_init.c
View file

@ -180,6 +180,18 @@ void board_init_f(ulong dummy)
k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata),
k3_mmc_stop_clock, k3_mmc_restart_clock);
/*
* Force probe of clk_k3 driver here to ensure basic default clock
* configuration is always done.
*/
if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
ret = uclass_get_device_by_driver(UCLASS_CLK,
DM_DRIVER_GET(ti_clk),
&dev);
if (ret)
panic("Failed to initialize clk-k3!\n");
}
/* Prepare console output */
preloader_console_init();

2
arch/arm/mach-k3/security.c
View file

@ -18,7 +18,7 @@
#include <spl.h>
#include <asm/arch/sys_proto.h>
void board_fit_image_post_process(void **p_image, size_t *p_size)
void ti_secure_image_post_process(void **p_image, size_t *p_size)
{
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;

111
arch/arm/mach-k3/sysfw-loader.c
View file

@ -40,6 +40,46 @@ DECLARE_GLOBAL_DATA_PTR;
*/
#define K3_SYSTEM_CONTROLLER_RPROC_ID 0
#define COMMON_HEADER_ADDRESS 0x41cffb00
#define BOARDCFG_ADDRESS 0x41c80000
#define COMP_TYPE_SBL_DATA 0x11
#define DESC_TYPE_BOARDCFG_PM_INDEX 0x2
#define DESC_TYPE_BOARDCFG_RM_INDEX 0x3
#define BOARD_CONFIG_RM_DESC_TYPE 0x000c
#define BOARD_CONFIG_PM_DESC_TYPE 0x000e
struct extboot_comp {
u32 comp_type;
u32 boot_core;
u32 comp_opts;
u64 dest_addr;
u32 comp_size;
};
struct extboot_header {
u8 magic[8];
u32 num_comps;
struct extboot_comp comps[5];
u32 reserved;
};
struct bcfg_desc {
u16 type;
u16 offset;
u16 size;
u8 devgrp;
u8 reserved;
} __packed;
struct bcfg_header {
u8 num_elems;
u8 sw_rev;
struct bcfg_desc descs[4];
u16 reserved;
} __packed;
static bool sysfw_loaded;
static void *sysfw_load_address;
@ -131,6 +171,13 @@ static void k3_sysfw_configure_using_fit(void *fit,
const void *cfg_fragment_addr;
size_t cfg_fragment_size;
int ret;
u8 *buf;
struct extboot_header *common_header;
struct bcfg_header *bcfg_header;
struct extboot_comp *comp;
struct bcfg_desc *desc;
u32 addr;
bool copy_bcfg = false;
/* Find the node holding the images information */
images = fdt_path_offset(fit, FIT_IMAGES_PATH);
@ -159,11 +206,53 @@ static void k3_sysfw_configure_using_fit(void *fit,
ret);
/* Apply power/clock (PM) specific configuration to SYSFW */
ret = board_ops->board_config_pm(ti_sci,
(u64)(u32)cfg_fragment_addr,
(u32)cfg_fragment_size);
if (ret)
panic("Failed to set board PM configuration (%d)\n", ret);
if (!IS_ENABLED(CONFIG_K3_DM_FW)) {
ret = board_ops->board_config_pm(ti_sci,
(u64)(u32)cfg_fragment_addr,
(u32)cfg_fragment_size);
if (ret)
panic("Failed to set board PM configuration (%d)\n", ret);
} else {
/* Initialize shared memory boardconfig buffer */
buf = (u8 *)COMMON_HEADER_ADDRESS;
common_header = (struct extboot_header *)buf;
/* Check if we have a struct populated by ROM in memory already */
if (strcmp((char *)common_header->magic, "EXTBOOT"))
copy_bcfg = true;
if (copy_bcfg) {
strcpy((char *)common_header->magic, "EXTBOOT");
common_header->num_comps = 1;
comp = &common_header->comps[0];
comp->comp_type = COMP_TYPE_SBL_DATA;
comp->boot_core = 0x10;
comp->comp_opts = 0;
addr = (u32)BOARDCFG_ADDRESS;
comp->dest_addr = addr;
comp->comp_size = sizeof(*bcfg_header);
bcfg_header = (struct bcfg_header *)addr;
bcfg_header->num_elems = 2;
bcfg_header->sw_rev = 0;
desc = &bcfg_header->descs[0];
desc->type = BOARD_CONFIG_PM_DESC_TYPE;
desc->offset = sizeof(*bcfg_header);
desc->size = cfg_fragment_size;
comp->comp_size += desc->size;
desc->devgrp = 0;
desc->reserved = 0;
memcpy((u8 *)bcfg_header + desc->offset,
cfg_fragment_addr, cfg_fragment_size);
bcfg_header->descs[1].offset = desc->offset + desc->size;
}
}
/* Extract resource management (RM) specific configuration from FIT */
ret = fit_get_data_by_name(fit, images, SYSFW_CFG_RM,
@ -172,6 +261,18 @@ static void k3_sysfw_configure_using_fit(void *fit,
panic("Error accessing %s node in FIT (%d)\n", SYSFW_CFG_RM,
ret);
if (copy_bcfg) {
desc = &bcfg_header->descs[1];
desc->type = BOARD_CONFIG_RM_DESC_TYPE;
desc->size = cfg_fragment_size;
comp->comp_size += desc->size;
desc->devgrp = 0;
desc->reserved = 0;
memcpy((u8 *)bcfg_header + desc->offset, cfg_fragment_addr,
cfg_fragment_size);
}
/* Apply resource management (RM) configuration to SYSFW */
ret = board_ops->board_config_rm(ti_sci,
(u64)(u32)cfg_fragment_addr,

3
arch/arm/mach-keystone/mon.c
View file

@ -103,7 +103,8 @@ static int k2_hs_bm_auth(int cmd, void *arg1)
return result;
}
void board_fit_image_post_process(void **p_image, size_t *p_size)
void board_fit_image_post_process(const void *fit, int node, void **p_image,
size_t *p_size)
{
int result = 0;
void *image = *p_image;

12
arch/arm/mach-rmobile/Kconfig.64
View file

@ -57,6 +57,11 @@ config R8A77995
imply CLK_R8A77995
imply PINCTRL_PFC_R8A77995
config R8A779A0
bool "Renesas SoC R8A779A0"
imply CLK_R8A779A0
imply PINCTRL_PFC_R8A779A0
config RZ_G2
bool "Renesas ARM SoCs RZ/G2 (64bit)"
@ -108,6 +113,12 @@ config TARGET_EBISU
help
Support for Renesas R-Car Gen3 Ebisu platform
config TARGET_FALCON
bool "Falcon board"
imply R8A779A0
help
Support for Renesas R-Car Gen3 Falcon platform
config TARGET_HIHOPE_RZG2
bool "HiHope RZ/G2 board"
imply R8A774A1
@ -158,6 +169,7 @@ source "board/renesas/condor/Kconfig"
source "board/renesas/draak/Kconfig"
source "board/renesas/eagle/Kconfig"
source "board/renesas/ebisu/Kconfig"
source "board/renesas/falcon/Kconfig"
source "board/renesas/salvator-x/Kconfig"
source "board/renesas/ulcb/Kconfig"
source "board/beacon/beacon-rzg2m/Kconfig"

4
arch/arm/mach-rmobile/Makefile
View file

@ -15,6 +15,10 @@ obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
obj-$(CONFIG_RCAR_GEN3) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
obj-$(CONFIG_RZ_G2) += cpu_info-rzg.o
ifneq ($(CONFIG_R8A779A0),)
obj-$(CONFIG_ARMV8_PSCI) += psci-r8a779a0.o
endif
OBJCOPYFLAGS_u-boot-spl.srec := -O srec
quiet_cmd_objcopy = OBJCOPY $@
cmd_objcopy = $(OBJCOPY) --gap-fill=0x00 $(OBJCOPYFLAGS) \

1
arch/arm/mach-rmobile/cpu_info.c
View file

@ -76,6 +76,7 @@ static const struct {
{ RMOBILE_CPU_TYPE_R8A77980, "R8A77980" },
{ RMOBILE_CPU_TYPE_R8A77990, "R8A77990" },
{ RMOBILE_CPU_TYPE_R8A77995, "R8A77995" },
{ RMOBILE_CPU_TYPE_R8A779A0, "R8A779A0" },
{ 0x0, "CPU" },
};

1
arch/arm/mach-rmobile/include/mach/rmobile.h
View file

@ -39,6 +39,7 @@
#define RMOBILE_CPU_TYPE_R8A77980 0x56
#define RMOBILE_CPU_TYPE_R8A77990 0x57
#define RMOBILE_CPU_TYPE_R8A77995 0x58
#define RMOBILE_CPU_TYPE_R8A779A0 0x59
#ifndef __ASSEMBLY__
const u8 *rzg_get_cpu_name(void);

49
arch/arm/mach-rmobile/psci-r8a779a0.c Normal file
View file

@ -0,0 +1,49 @@
// SPDX-License-Identifier: GPL-2.0
/*
* This file implements basic PSCI support for Renesas r8a779a0 SoC
*
* Copyright (C) 2020 Renesas Electronics Corp.
*
*/
#include <common.h>
#include <asm/io.h>
#include <asm/psci.h>
#include <asm/secure.h>
int __secure psci_features(u32 function_id, u32 psci_fid)
{
switch (psci_fid) {
case ARM_PSCI_0_2_FN_PSCI_VERSION:
case ARM_PSCI_0_2_FN_SYSTEM_RESET:
return 0x0;
}
/* case ARM_PSCI_0_2_FN_CPU_ON: */
/* case ARM_PSCI_0_2_FN_CPU_OFF: */
/* case ARM_PSCI_0_2_FN_AFFINITY_INFO: */
/* case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE: */
/* case ARM_PSCI_0_2_FN_SYSTEM_OFF: */
return ARM_PSCI_RET_NI;
}
u32 __secure psci_version(void)
{
return ARM_PSCI_VER_0_2;
}
#define RST_BASE 0xE6160000 /* Domain0 */
#define RST_SRESCR0 (RST_BASE + 0x18)
#define RST_SPRES 0x5AA58000
void __secure __noreturn psci_system_reset(void)
{
writel(RST_SPRES, RST_SRESCR0);
while (1)
;
}
int psci_update_dt(void *fdt)
{
return 0;
}

18
arch/arm/mach-rockchip/Kconfig
View file

@ -257,6 +257,23 @@ config ROCKCHIP_RK3399
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
config ROCKCHIP_RK3568
bool "Support Rockchip RK3568"
select ARM64
select CLK
select PINCTRL
select RAM
select REGMAP
select SYSCON
select BOARD_LATE_INIT
imply ROCKCHIP_COMMON_BOARD
help
The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55,
including NEON and GPU, 512K L3 cache, Mali-G52 based graphics,
two video interfaces supporting HDMI and eDP, several DDR3 options
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
config ROCKCHIP_RV1108
bool "Support Rockchip RV1108"
select CPU_V7A
@ -386,5 +403,6 @@ source "arch/arm/mach-rockchip/rk3308/Kconfig"
source "arch/arm/mach-rockchip/rk3328/Kconfig"
source "arch/arm/mach-rockchip/rk3368/Kconfig"
source "arch/arm/mach-rockchip/rk3399/Kconfig"
source "arch/arm/mach-rockchip/rk3568/Kconfig"
source "arch/arm/mach-rockchip/rv1108/Kconfig"
endif

1
arch/arm/mach-rockchip/Makefile
View file

@ -42,6 +42,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += rk3308/
obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/
obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
# Clear out SPL objects, in case this is a TPL build

20
arch/arm/mach-rockchip/rk3568/Kconfig Normal file
View file

@ -0,0 +1,20 @@
if ROCKCHIP_RK3568
config TARGET_EVB_RK3568
bool "RK3568 evaluation board"
select BOARD_LATE_INIT
help
RK3568 EVB is a evaluation board for Rockchp RK3568.
config ROCKCHIP_BOOT_MODE_REG
default 0xfdc20200
config SYS_SOC
default "rk3568"
config SYS_MALLOC_F_LEN
default 0x2000
source "board/rockchip/evb_rk3568/Kconfig"
endif

9
arch/arm/mach-rockchip/rk3568/Makefile Normal file
View file

@ -0,0 +1,9 @@
#
# (C) Copyright 2021 Rockchip Electronics Co., Ltd
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += clk_rk3568.o
obj-y += rk3568.o
obj-y += syscon_rk3568.o

53
arch/arm/mach-rockchip/rk3568/clk_rk3568.c Normal file
View file

@ -0,0 +1,53 @@
// SPDX-License-Identifier: GPL-2.0
/*
* (C) Copyright 2021 Rockchip Electronics Co., Ltd
*/
#include <common.h>
#include <dm.h>
#include <syscon.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/cru_rk3568.h>
#include <linux/err.h>
int rockchip_get_clk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
DM_DRIVER_GET(rockchip_rk3568_cru), devp);
}
void *rockchip_get_cru(void)
{
struct rk3568_clk_priv *priv;
struct udevice *dev;
int ret;
ret = rockchip_get_clk(&dev);
if (ret)
return ERR_PTR(ret);
priv = dev_get_priv(dev);
return priv->cru;
}
static int rockchip_get_pmucruclk(struct udevice **devp)
{
return uclass_get_device_by_driver(UCLASS_CLK,
DM_DRIVER_GET(rockchip_rk3568_pmucru), devp);
}
void *rockchip_get_pmucru(void)
{
struct rk3568_pmuclk_priv *priv;
struct udevice *dev;
int ret;
ret = rockchip_get_pmucruclk(&dev);
if (ret)
return ERR_PTR(ret);
priv = dev_get_priv(dev);
return priv->pmucru;
}

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