Merge branch '2023-09-08-assorted-TI-platform-updates' into next

- Add TI BeaglePlay support, verdin-am62 cleanups, K3-J7 DDR timing
  updates, IOT2050 DTS update for watchdog
This commit is contained in:
Tom Rini 2023-09-08 22:44:00 -04:00
commit 615471c643
37 changed files with 4725 additions and 340 deletions

View file

@ -1337,6 +1337,8 @@ dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \
k3-am625-r5-sk.dtb \
k3-am625-beagleplay.dtb \
k3-am625-r5-beagleplay.dtb \
k3-am625-verdin-wifi-dev.dtb \
k3-am625-verdin-r5.dtb

File diff suppressed because it is too large Load diff

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@ -0,0 +1,195 @@
// SPDX-License-Identifier: GPL-2.0
/*
* https://beagleboard.org/play
*
* Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
*/
#include "k3-am625-sk-binman.dtsi"
/ {
chosen {
tick-timer = &main_timer0;
};
memory@80000000 {
bootph-pre-ram;
};
/* Keep the LEDs on by default to indicate life */
leds {
bootph-pre-ram;
led-0 {
default-state = "on";
bootph-pre-ram;
};
led-1 {
default-state = "on";
bootph-pre-ram;
};
led-2 {
default-state = "on";
bootph-pre-ram;
};
led-3 {
default-state = "on";
bootph-pre-ram;
};
led-4 {
default-state = "on";
bootph-pre-ram;
};
};
};
&cbass_main {
bootph-pre-ram;
};
&main_timer0 {
clock-frequency = <25000000>;
bootph-pre-ram;
};
&dmss {
bootph-pre-ram;
};
&secure_proxy_main {
bootph-pre-ram;
};
&dmsc {
bootph-pre-ram;
};
&k3_pds {
bootph-pre-ram;
};
&k3_clks {
bootph-pre-ram;
};
&k3_reset {
bootph-pre-ram;
};
&dmsc {
bootph-pre-ram;
k3_sysreset: sysreset-controller {
compatible = "ti,sci-sysreset";
bootph-pre-ram;
};
};
&wkup_conf {
bootph-pre-ram;
};
&chipid {
bootph-pre-ram;
};
&main_pmx0 {
bootph-pre-ram;
};
&main_uart0 {
bootph-pre-ram;
};
&console_pins_default {
bootph-pre-ram;
};
&cbass_mcu {
bootph-pre-ram;
};
&cbass_wakeup {
bootph-pre-ram;
};
&mcu_pmx0 {
bootph-pre-ram;
};
&main_i2c0 {
bootph-pre-ram;
};
&local_i2c_pins_default {
bootph-pre-ram;
};
&gpio0_pins_default {
bootph-pre-ram;
};
&main_gpio0 {
bootph-pre-ram;
};
&main_gpio1 {
bootph-pre-ram;
};
&sdhci0 {
/* EMMC */
bootph-pre-ram;
};
&emmc_pins_default {
bootph-pre-ram;
};
&sd_pins_default {
bootph-pre-ram;
/* Force to use SDCD card detect pin */
pinctrl-single,pins = <
AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
AM62X_IOPAD(0x0234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
AM62X_IOPAD(0x0230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
AM62X_IOPAD(0x022c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
AM62X_IOPAD(0x0228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
AM62X_IOPAD(0x0224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
AM62X_IOPAD(0x0240, PIN_INPUT, 0) /* (D17) MMC1_SDCD.MMC1_SDCD */
>;
};
&tps65219 {
bootph-pre-ram;
};
&sdhci1 {
bootph-pre-ram;
};
#ifdef CONFIG_TARGET_AM625_A53_EVM
#define SPL_AM625_BEAGLEPLAY_DTB "spl/dts/k3-am625-beagleplay.dtb"
#define AM625_BEAGLEPLAY_DTB "arch/arm/dts/k3-am625-beagleplay.dtb"
&spl_am625_sk_dtb {
filename = SPL_AM625_BEAGLEPLAY_DTB;
};
&am625_sk_dtb {
filename = AM625_BEAGLEPLAY_DTB;
};
&spl_am625_sk_dtb_unsigned {
filename = SPL_AM625_BEAGLEPLAY_DTB;
};
&am625_sk_dtb_unsigned {
filename = AM625_BEAGLEPLAY_DTB;
};
#endif

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@ -0,0 +1,758 @@
// SPDX-License-Identifier: GPL-2.0
/*
* https://beagleplay.org/
*
* Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "k3-am625.dtsi"
/ {
compatible = "beagle,am625-beagleplay", "ti,am625";
model = "BeagleBoard.org BeaglePlay";
aliases {
ethernet0 = &cpsw_port1;
ethernet1 = &cpsw_port2;
gpio0 = &main_gpio0;
gpio1 = &main_gpio1;
gpio2 = &mcu_gpio0;
i2c0 = &main_i2c0;
i2c1 = &main_i2c1;
i2c2 = &main_i2c2;
i2c3 = &main_i2c3;
i2c4 = &wkup_i2c0;
i2c5 = &mcu_i2c0;
mdio-gpio0 = &mdio0;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
mmc2 = &sdhci2;
rtc0 = &rtc;
serial0 = &main_uart5;
serial1 = &main_uart6;
serial2 = &main_uart0;
usb0 = &usb0;
usb1 = &usb1;
};
chosen {
stdout-path = "serial2:115200n8";
};
memory@80000000 {
device_type = "memory";
/* 2G RAM */
reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
ramoops: ramoops@9ca00000 {
compatible = "ramoops";
reg = <0x00 0x9c700000 0x00 0x00100000>;
record-size = <0x8000>;
console-size = <0x8000>;
ftrace-size = <0x00>;
pmsg-size = <0x8000>;
};
secure_tfa_ddr: tfa@9e780000 {
reg = <0x00 0x9e780000 0x00 0x80000>;
no-map;
};
secure_ddr: optee@9e800000 {
reg = <0x00 0x9e800000 0x00 0x01800000>;
no-map;
};
wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 {
compatible = "shared-dma-pool";
reg = <0x00 0x9db00000 0x00 0xc00000>;
no-map;
};
};
vsys_5v0: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "vsys_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
vdd_3v3: regulator-2 {
/* output of TLV62595DMQR-U12 */
compatible = "regulator-fixed";
regulator-name = "vdd_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vsys_5v0>;
regulator-always-on;
regulator-boot-on;
};
wlan_en: regulator-3 {
/* OUTPUT of SN74AVC2T244DQMR */
compatible = "regulator-fixed";
regulator-name = "wlan_en";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
enable-active-high;
regulator-always-on;
vin-supply = <&vdd_3v3>;
gpio = <&main_gpio0 38 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&wifi_en_pins_default>;
};
vdd_3v3_sd: regulator-4 {
/* output of TPS22918DBVR-U21 */
pinctrl-names = "default";
pinctrl-0 = <&vdd_3v3_sd_pins_default>;
compatible = "regulator-fixed";
regulator-name = "vdd_3v3_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
regulator-always-on;
vin-supply = <&vdd_3v3>;
gpio = <&main_gpio1 19 GPIO_ACTIVE_HIGH>;
};
vdd_sd_dv: regulator-5 {
compatible = "regulator-gpio";
regulator-name = "sd_hs200_switch";
pinctrl-names = "default";
pinctrl-0 = <&vdd_sd_dv_pins_default>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
vin-supply = <&ldo1_reg>;
gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>;
states = <1800000 0x0>,
<3300000 0x1>;
};
leds {
compatible = "gpio-leds";
led-0 {
gpios = <&main_gpio0 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
function = LED_FUNCTION_HEARTBEAT;
default-state = "off";
};
led-1 {
gpios = <&main_gpio0 4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "disk-activity";
function = LED_FUNCTION_DISK_ACTIVITY;
default-state = "keep";
};
led-2 {
gpios = <&main_gpio0 5 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_CPU;
};
led-3 {
gpios = <&main_gpio0 6 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_LAN;
};
led-4 {
gpios = <&main_gpio0 9 GPIO_ACTIVE_HIGH>;
function = LED_FUNCTION_WLAN;
};
};
gpio_keys: gpio-keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&usr_button_pins_default>;
usr: button-usr {
label = "User Key";
linux,code = <BTN_0>;
gpios = <&main_gpio0 18 GPIO_ACTIVE_LOW>;
};
};
/* Workaround for errata i2329 - just use mdio bitbang */
mdio0: mdio {
compatible = "virtual,mdio-gpio";
pinctrl-names = "default";
pinctrl-0 = <&mdio0_pins_default>;
gpios = <&main_gpio0 86 GPIO_ACTIVE_HIGH>, /* MDC */
<&main_gpio0 85 GPIO_ACTIVE_HIGH>; /* MDIO */
#address-cells = <1>;
#size-cells = <0>;
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
};
cpsw3g_phy1: ethernet-phy@1 {
reg = <1>;
reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>;
reset-assert-us = <25>;
reset-deassert-us = <60000>; /* T2 */
};
};
};
&main_pmx0 {
gpio0_pins_default: gpio0-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x0004, PIN_INPUT, 7) /* (G25) OSPI0_LBCLKO.GPIO0_1 */
AM62X_IOPAD(0x0008, PIN_INPUT, 7) /* (J24) OSPI0_DQS.GPIO0_2 */
AM62X_IOPAD(0x000c, PIN_INPUT, 7) /* (E25) OSPI0_D0.GPIO0_3 */
AM62X_IOPAD(0x0010, PIN_INPUT, 7) /* (G24) OSPI0_D1.GPIO0_4 */
AM62X_IOPAD(0x0014, PIN_INPUT, 7) /* (F25) OSPI0_D2.GPIO0_5 */
AM62X_IOPAD(0x0018, PIN_INPUT, 7) /* (F24) OSPI0_D3.GPIO0_6 */
AM62X_IOPAD(0x0024, PIN_INPUT, 7) /* (H25) OSPI0_D6.GPIO0_9 */
AM62X_IOPAD(0x0028, PIN_INPUT, 7) /* (J22) OSPI0_D7.GPIO0_10 */
AM62X_IOPAD(0x002c, PIN_INPUT, 7) /* (F23) OSPI0_CSn0.GPIO0_11 */
AM62X_IOPAD(0x0030, PIN_INPUT, 7) /* (G21) OSPI0_CSn1.GPIO0_12 */
AM62X_IOPAD(0x0034, PIN_INPUT, 7) /* (H21) OSPI0_CSn2.GPIO0_13 */
AM62X_IOPAD(0x0038, PIN_INPUT, 7) /* (E24) OSPI0_CSn3.GPIO0_14 */
AM62X_IOPAD(0x00a4, PIN_INPUT, 7) /* (M22) GPMC0_DIR.GPIO0_40 */
AM62X_IOPAD(0x00ac, PIN_INPUT, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */
>;
};
vdd_sd_dv_pins_default: vdd-sd-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x0244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */
>;
};
usr_button_pins_default: usr-button-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x0048, PIN_INPUT, 7) /* (N25) GPMC0_AD3.GPIO0_18 */
>;
};
grove_pins_default: grove-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */
AM62X_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */
>;
};
local_i2c_pins_default: local-i2c-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */
AM62X_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */
>;
};
i2c2_1v8_pins_default: i2c2-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */
AM62X_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */
>;
};
mdio0_pins_default: mdio0-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x0160, PIN_OUTPUT, 7) /* (AD24) MDIO0_MDC.GPIO0_86 */
AM62X_IOPAD(0x015c, PIN_INPUT, 7) /* (AB22) MDIO0_MDIO.GPIO0_85 */
>;
};
rgmii1_pins_default: rgmii1-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x014c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */
AM62X_IOPAD(0x0150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */
AM62X_IOPAD(0x0154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */
AM62X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */
AM62X_IOPAD(0x0148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */
AM62X_IOPAD(0x0144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */
AM62X_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */
AM62X_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */
AM62X_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */
AM62X_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */
AM62X_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */
AM62X_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */
>;
};
emmc_pins_default: emmc-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x0220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */
AM62X_IOPAD(0x0218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */
AM62X_IOPAD(0x0214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */
AM62X_IOPAD(0x0210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */
AM62X_IOPAD(0x020c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */
AM62X_IOPAD(0x0208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */
AM62X_IOPAD(0x0204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */
AM62X_IOPAD(0x0200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */
AM62X_IOPAD(0x01fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */
AM62X_IOPAD(0x01f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */
>;
};
vdd_3v3_sd_pins_default: vdd-3v3-sd-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1_GPIO1_19 */
>;
};
sd_pins_default: sd-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */
AM62X_IOPAD(0x0234, PIN_INPUT, 0) /* (B22) MMC1_CLK */
AM62X_IOPAD(0x0230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */
AM62X_IOPAD(0x022c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */
AM62X_IOPAD(0x0228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */
AM62X_IOPAD(0x0224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */
AM62X_IOPAD(0x0240, PIN_INPUT, 7) /* (D17) MMC1_SDCD.GPIO1_48 */
>;
};
wifi_pins_default: wifi-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x0120, PIN_INPUT, 0) /* (C24) MMC2_CMD */
AM62X_IOPAD(0x0118, PIN_INPUT, 0) /* (D25) MMC2_CLK */
AM62X_IOPAD(0x0114, PIN_INPUT, 0) /* (B24) MMC2_DAT0 */
AM62X_IOPAD(0x0110, PIN_INPUT, 0) /* (C25) MMC2_DAT1 */
AM62X_IOPAD(0x010c, PIN_INPUT, 0) /* (E23) MMC2_DAT2 */
AM62X_IOPAD(0x0108, PIN_INPUT, 0) /* (D24) MMC2_DAT3 */
AM62X_IOPAD(0x0124, PIN_INPUT, 0) /* (A23) MMC2_SDCD */
AM62X_IOPAD(0x11c, PIN_INPUT, 0) /* (#N/A) MMC2_CLKB */
>;
};
wifi_en_pins_default: wifi-en-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x009c, PIN_OUTPUT, 7) /* (V25) GPMC0_WAIT1.GPIO0_38 */
>;
};
wifi_wlirq_pins_default: wifi-wlirq-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x00a8, PIN_INPUT, 7) /* (M21) GPMC0_CSn0.GPIO0_41 */
>;
};
spe_pins_default: spe-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x0168, PIN_INPUT, 1) /* (AE21) RGMII2_TXC.RMII2_CRS_DV */
AM62X_IOPAD(0x0180, PIN_INPUT, 1) /* (AD23) RGMII2_RXC.RMII2_REF_CLK */
AM62X_IOPAD(0x0184, PIN_INPUT, 1) /* (AE23) RGMII2_RD0.RMII2_RXD0 */
AM62X_IOPAD(0x0188, PIN_INPUT, 1) /* (AB20) RGMII2_RD1.RMII2_RXD1 */
AM62X_IOPAD(0x017c, PIN_INPUT, 1) /* (AD22) RGMII2_RX_CTL.RMII2_RX_ER */
AM62X_IOPAD(0x016c, PIN_INPUT, 1) /* (Y18) RGMII2_TD0.RMII2_TXD0 */
AM62X_IOPAD(0x0170, PIN_INPUT, 1) /* (AA18) RGMII2_TD1.RMII2_TXD1 */
AM62X_IOPAD(0x0164, PIN_INPUT, 1) /* (AA19) RGMII2_TX_CTL.RMII2_TX_EN */
AM62X_IOPAD(0x018c, PIN_OUTPUT, 7) /* (AC21) RGMII2_RD2.GPIO1_5 */
AM62X_IOPAD(0x0190, PIN_INPUT, 7) /* (AE22) RGMII2_RD3.GPIO1_6 */
AM62X_IOPAD(0x01f0, PIN_OUTPUT, 5) /* (A18) EXT_REFCLK1.CLKOUT0 */
>;
};
mikrobus_i2c_pins_default: mikrobus-i2c-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A15) UART0_CTSn.I2C3_SCL */
AM62X_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (B15) UART0_RTSn.I2C3_SDA */
>;
};
mikrobus_uart_pins_default: mikrobus-uart-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x01d8, PIN_INPUT, 1) /* (C15) MCAN0_TX.UART5_RXD */
AM62X_IOPAD(0x01dc, PIN_OUTPUT, 1) /* (E15) MCAN0_RX.UART5_TXD */
>;
};
mikrobus_spi_pins_default: mikrobus-spi-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x01b0, PIN_INPUT, 1) /* (A20) MCASP0_ACLKR.SPI2_CLK */
AM62X_IOPAD(0x01ac, PIN_INPUT, 1) /* (E19) MCASP0_AFSR.SPI2_CS0 */
AM62X_IOPAD(0x0194, PIN_INPUT, 1) /* (B19) MCASP0_AXR3.SPI2_D0 */
AM62X_IOPAD(0x0198, PIN_INPUT, 1) /* (A19) MCASP0_AXR2.SPI2_D1 */
>;
};
mikrobus_gpio_pins_default: mikrobus-gpio-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x019c, PIN_INPUT, 7) /* (B18) MCASP0_AXR1.GPIO1_9 */
AM62X_IOPAD(0x01a0, PIN_INPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10 */
AM62X_IOPAD(0x01a8, PIN_INPUT, 7) /* (D20) MCASP0_AFSX.GPIO1_12 */
>;
};
console_pins_default: console-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x01c8, PIN_INPUT, 0) /* (D14) UART0_RXD */
AM62X_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */
>;
};
wifi_debug_uart_pins_default: wifi-debug-uart-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x001c, PIN_INPUT, 3) /* (J23) OSPI0_D4.UART6_RXD */
AM62X_IOPAD(0x0020, PIN_OUTPUT, 3) /* (J25) OSPI0_D5.UART6_TXD */
>;
};
usb1_pins_default: usb1-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x0258, PIN_INPUT, 0) /* (F18) USB1_DRVVBUS */
>;
};
pmic_irq_pins_default: pmic-irq-default-pins {
pinctrl-single,pins = <
AM62X_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (D16) EXTINTn */
>;
};
};
&mcu_pmx0 {
i2c_qwiic_pins_default: i2c-qwiic-default-pins {
pinctrl-single,pins = <
AM62X_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (A8) MCU_I2C0_SCL */
AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */
>;
};
gbe_pmx_obsclk: gbe-pmx-clk-default {
pinctrl-single,pins = <
AM62X_MCU_IOPAD(0x0004, PIN_OUTPUT, 1) /* (B8) MCU_SPI0_CS1.MCU_OBSCLK0 */
>;
};
i2c_csi_pins_default: i2c-csi-default-pins {
pinctrl-single,pins = <
AM62X_MCU_IOPAD(0x004c, PIN_INPUT_PULLUP, 0) /* (B9) WKUP_I2C0_SCL */
AM62X_MCU_IOPAD(0x0050, PIN_INPUT_PULLUP, 0) /* (A9) WKUP_I2C0_SDA */
>;
};
wifi_32k_clk: mcu-clk-out-default-pins {
pinctrl-single,pins = <
AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (A12) WKUP_CLKOUT0 */
>;
};
};
&a53_opp_table {
/* Requires VDD_CORE to be at 0.85V */
opp-1400000000 {
opp-hz = /bits/ 64 <1400000000>;
opp-supported-hw = <0x01 0x0004>;
};
};
&wkup_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c_csi_pins_default>;
clock-frequency = <400000>;
/* Enable with overlay for camera sensor */
};
&mcu_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c_qwiic_pins_default>;
clock-frequency = <100000>;
status = "okay";
};
&usbss0 {
ti,vbus-divider;
status = "okay";
};
&usb0 {
dr_mode = "peripheral";
};
&usbss1 {
ti,vbus-divider;
status = "okay";
};
&usb1 {
dr_mode = "host";
pinctrl-names = "default";
pinctrl-0 = <&usb1_pins_default>;
};
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_pins_default>, <&spe_pins_default>,
<&gbe_pmx_obsclk>;
assigned-clocks = <&k3_clks 157 70>, <&k3_clks 157 20>;
assigned-clock-parents = <&k3_clks 157 72>, <&k3_clks 157 22>;
};
&cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&cpsw3g_phy0>;
};
&cpsw_port2 {
phy-mode = "rmii";
phy-handle = <&cpsw3g_phy1>;
};
&cpsw3g_mdio {
/* Workaround for errata i2329 - Use mdio bitbang */
status = "disabled";
};
&main_gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&gpio0_pins_default>;
gpio-line-names = "BL_EN_3V3", "SPE_PO_EN", "RTC_INT", /* 0-2 */
"USR0", "USR1", "USR2", "USR3", "", "", "USR4", /* 3-9 */
"EEPROM_WP", /* 10 */
"CSI2_CAMERA_GPIO1", "CSI2_CAMERA_GPIO2", /* 11-12 */
"CC1352P7_BOOT", "CC1352P7_RSTN", "", "", "", /* 13-17 */
"USR_BUTTON", "", "", "", "", "", "", "", "", /* 18-26 */
"", "", "", "", "", "", "", "", "", "HDMI_INT", /* 27-36 */
"", "VDD_WLAN_EN", "", "", "WL_IRQ", "GBE_INTN",/* 37-42 */
"", "", "", "", "", "", "", "", "", "", "", "", /* 43-54 */
"", "", "", "", "", "", "", "", "", "", "", "", /* 55-66 */
"", "", "", "", "", "", "", "", "", "", "", "", /* 67-78 */
"", "", "", "", "", "", /* 79-84 */
"BITBANG_MDIO_DATA", "BITBANG_MDIO_CLK", /* 85-86 */
"", "", "", "", ""; /* 87-91 */
};
&main_gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&mikrobus_gpio_pins_default>;
gpio-line-names = "", "", "", "", "", /* 0-4 */
"SPE_RSTN", "SPE_INTN", "MIKROBUS_GPIO1_7", /* 5-7 */
"MIKROBUS_GPIO1_8", "MIKROBUS_GPIO1_9", /* 8-9 */
"MIKROBUS_GPIO1_10", "MIKROBUS_GPIO1_11", /* 10-11 */
"MIKROBUS_GPIO1_12", "MIKROBUS_W1_GPIO0", /* 12-13 */
"MIKROBUS_GPIO1_14", /* 14 */
"", "", "", "", "VDD_3V3_SD", "", "", /* 15-21 */
"MIKROBUS_GPIO1_22", "MIKROBUS_GPIO1_23", /* 22-23 */
"MIKROBUS_GPIO1_24", "MIKROBUS_GPIO1_25", /* 24-25 */
"", "", "", "", "", "", "", "", "", "", "", "", /* 26-37 */
"", "", "", "", "", "", "", "", "", "", /* 38-47 */
"SD_CD", "SD_VOLT_SEL", "", ""; /* 48-51 */
};
&main_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&local_i2c_pins_default>;
clock-frequency = <400000>;
status = "okay";
eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
};
rtc: rtc@68 {
compatible = "ti,bq32000";
reg = <0x68>;
interrupt-parent = <&main_gpio0>;
interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
};
tps65219: pmic@30 {
compatible = "ti,tps65219";
reg = <0x30>;
buck1-supply = <&vsys_5v0>;
buck2-supply = <&vsys_5v0>;
buck3-supply = <&vsys_5v0>;
ldo1-supply = <&vdd_3v3>;
ldo2-supply = <&buck2_reg>;
ldo3-supply = <&vdd_3v3>;
ldo4-supply = <&vdd_3v3>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_irq_pins_default>;
interrupt-parent = <&gic500>;
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
system-power-controller;
ti,power-button;
regulators {
buck1_reg: buck1 {
regulator-name = "VDD_CORE";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
};
buck2_reg: buck2 {
regulator-name = "VDD_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
buck3_reg: buck3 {
regulator-name = "VDD_1V2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: ldo1 {
/*
* Regulator is left as is unused, vdd_sd
* is controlled via GPIO with bypass config
* as per the NVM configuration
*/
regulator-name = "VDD_SD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-allow-bypass;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: ldo2 {
regulator-name = "VDDA_0V85";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
};
ldo3_reg: ldo3 {
regulator-name = "VDDA_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo4_reg: ldo4 {
regulator-name = "VDD_2V5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&main_i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&grove_pins_default>;
clock-frequency = <100000>;
status = "okay";
};
&main_i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_1v8_pins_default>;
clock-frequency = <100000>;
status = "okay";
};
&main_i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&mikrobus_i2c_pins_default>;
clock-frequency = <400000>;
status = "okay";
};
&main_spi2 {
pinctrl-names = "default";
pinctrl-0 = <&mikrobus_spi_pins_default>;
status = "okay";
};
&sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&emmc_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
status = "okay";
};
&sdhci1 {
/* SD/MMC */
pinctrl-names = "default";
pinctrl-0 = <&sd_pins_default>;
vmmc-supply = <&vdd_3v3_sd>;
vqmmc-supply = <&vdd_sd_dv>;
ti,driver-strength-ohm = <50>;
disable-wp;
cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>;
cd-debounce-delay-ms = <100>;
ti,fails-without-test-cd;
status = "okay";
};
&sdhci2 {
vmmc-supply = <&wlan_en>;
pinctrl-names = "default";
pinctrl-0 = <&wifi_pins_default>, <&wifi_32k_clk>;
bus-width = <4>;
non-removable;
ti,fails-without-test-cd;
cap-power-off-card;
keep-power-in-suspend;
ti,driver-strength-ohm = <50>;
assigned-clocks = <&k3_clks 157 158>;
assigned-clock-parents = <&k3_clks 157 160>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
wlcore: wlcore@2 {
compatible = "ti,wl1807";
reg = <2>;
pinctrl-names = "default";
pinctrl-0 = <&wifi_wlirq_pins_default>;
interrupt-parent = <&main_gpio0>;
interrupts = <41 IRQ_TYPE_EDGE_FALLING>;
};
};
&main_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&console_pins_default>;
status = "okay";
};
&main_uart1 {
/* Main UART1 is used by TIFS firmware */
status = "reserved";
};
&main_uart5 {
pinctrl-names = "default";
pinctrl-0 = <&mikrobus_uart_pins_default>;
status = "okay";
};
&main_uart6 {
pinctrl-names = "default";
pinctrl-0 = <&wifi_debug_uart_pins_default>;
status = "okay";
};

View file

@ -0,0 +1,86 @@
// SPDX-License-Identifier: GPL-2.0
/*
* https://beagleboard.org/play
*
* Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
* Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation
*/
#include "k3-am625-beagleplay.dts"
#include "k3-am625-beagleplay-ddr4-1600MTs.dtsi"
#include "k3-am62-ddr.dtsi"
#include "k3-am625-beagleplay-u-boot.dtsi"
/ {
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a53_0;
};
a53_0: a53@0 {
compatible = "ti,am654-rproc";
reg = <0x00 0x00a90000 0x00 0x10>;
power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
resets = <&k3_reset 135 0>;
clocks = <&k3_clks 61 0>;
assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
assigned-clock-parents = <&k3_clks 61 2>;
assigned-clock-rates = <200000000>, <1250000000>;
ti,sci = <&dmsc>;
ti,sci-proc-id = <32>;
ti,sci-host-id = <10>;
bootph-pre-ram;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <36>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 22>,
<&secure_proxy_main 23>;
bootph-pre-ram;
};
};
&dmsc {
mboxes= <&secure_proxy_main 0>,
<&secure_proxy_main 1>,
<&secure_proxy_main 0>;
mbox-names = "rx", "tx", "notify";
ti,host-id = <35>;
ti,secure-host;
};
&mcu_esm {
bootph-pre-ram;
};
&secure_proxy_sa3 {
bootph-pre-ram;
/* We require this for boot handshake */
status = "okay";
};
&cbass_main {
sysctrler: sysctrler {
compatible = "ti,am654-system-controller";
mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>, <&secure_proxy_sa3 0>;
mbox-names = "tx", "rx", "boot_notify";
bootph-pre-ram;
};
};
&main_esm {
bootph-pre-ram;
};
&main_pktdma {
ti,sci = <&dm_tifs>;
};
&main_bcdma {
ti,sci = <&dm_tifs>;
};

View file

@ -389,7 +389,7 @@
type = "flat_dt";
arch = "arm";
compression = "none";
blob {
spl_am625_sk_dtb_unsigned: blob {
filename = SPL_AM625_SK_DTB;
};
};
@ -438,7 +438,7 @@
type = "flat_dt";
arch = "arm";
compression = "none";
blob {
am625_sk_dtb_unsigned: blob {
filename = AM625_SK_DTB;
};
hash {

View file

@ -64,6 +64,12 @@
alignment = <0x1000>;
no-map;
};
/* To reserve the power-on(PON) reason for watchdog reset */
wdt_reset_memory_region: wdt-memory@a2200000 {
reg = <0x00 0xa2200000 0x00 0x00001000>;
no-map;
};
};
leds {
@ -720,6 +726,11 @@
mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
};
&mcu_rti1 {
memory-region = <&wdt_reset_memory_region>;
};
&icssg0_mdio {
status = "disabled";
};

View file

@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.9.1
* This file was generated on 07/17/2022
* Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
* This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.10.0
* This file was generated on 04/12/2023
*/
#define DDRSS_PLL_FHS_CNT 10
@ -54,11 +54,11 @@
#define DDRSS_CTL_41_DATA 0x1B60008B
#define DDRSS_CTL_42_DATA 0x2000422B
#define DDRSS_CTL_43_DATA 0x000A0A09
#define DDRSS_CTL_44_DATA 0x0400078A
#define DDRSS_CTL_44_DATA 0x040003C5
#define DDRSS_CTL_45_DATA 0x1E161104
#define DDRSS_CTL_46_DATA 0x10012458
#define DDRSS_CTL_46_DATA 0x1000922C
#define DDRSS_CTL_47_DATA 0x1E161110
#define DDRSS_CTL_48_DATA 0x10012458
#define DDRSS_CTL_48_DATA 0x1000922C
#define DDRSS_CTL_49_DATA 0x02030410
#define DDRSS_CTL_50_DATA 0x2C040500
#define DDRSS_CTL_51_DATA 0x082D2C2D
@ -71,11 +71,11 @@
#define DDRSS_CTL_58_DATA 0x00010100
#define DDRSS_CTL_59_DATA 0x03010000
#define DDRSS_CTL_60_DATA 0x00001008
#define DDRSS_CTL_61_DATA 0x000000CE
#define DDRSS_CTL_61_DATA 0x00000063
#define DDRSS_CTL_62_DATA 0x00000256
#define DDRSS_CTL_63_DATA 0x00002073
#define DDRSS_CTL_63_DATA 0x00001035
#define DDRSS_CTL_64_DATA 0x00000256
#define DDRSS_CTL_65_DATA 0x00002073
#define DDRSS_CTL_65_DATA 0x00001035
#define DDRSS_CTL_66_DATA 0x00000005
#define DDRSS_CTL_67_DATA 0x00040000
#define DDRSS_CTL_68_DATA 0x00950012
@ -112,27 +112,27 @@
#define DDRSS_CTL_99_DATA 0x00000000
#define DDRSS_CTL_100_DATA 0x00040005
#define DDRSS_CTL_101_DATA 0x00000000
#define DDRSS_CTL_102_DATA 0x00003380
#define DDRSS_CTL_103_DATA 0x00003380
#define DDRSS_CTL_104_DATA 0x00003380
#define DDRSS_CTL_105_DATA 0x00003380
#define DDRSS_CTL_106_DATA 0x00003380
#define DDRSS_CTL_102_DATA 0x000018C0
#define DDRSS_CTL_103_DATA 0x000018C0
#define DDRSS_CTL_104_DATA 0x000018C0
#define DDRSS_CTL_105_DATA 0x000018C0
#define DDRSS_CTL_106_DATA 0x000018C0
#define DDRSS_CTL_107_DATA 0x00000000
#define DDRSS_CTL_108_DATA 0x000005A2
#define DDRSS_CTL_109_DATA 0x00081CC0
#define DDRSS_CTL_110_DATA 0x00081CC0
#define DDRSS_CTL_111_DATA 0x00081CC0
#define DDRSS_CTL_112_DATA 0x00081CC0
#define DDRSS_CTL_113_DATA 0x00081CC0
#define DDRSS_CTL_108_DATA 0x000002B5
#define DDRSS_CTL_109_DATA 0x00040D40
#define DDRSS_CTL_110_DATA 0x00040D40
#define DDRSS_CTL_111_DATA 0x00040D40
#define DDRSS_CTL_112_DATA 0x00040D40
#define DDRSS_CTL_113_DATA 0x00040D40
#define DDRSS_CTL_114_DATA 0x00000000
#define DDRSS_CTL_115_DATA 0x0000E325
#define DDRSS_CTL_116_DATA 0x00081CC0
#define DDRSS_CTL_117_DATA 0x00081CC0
#define DDRSS_CTL_118_DATA 0x00081CC0
#define DDRSS_CTL_119_DATA 0x00081CC0
#define DDRSS_CTL_120_DATA 0x00081CC0
#define DDRSS_CTL_115_DATA 0x00007173
#define DDRSS_CTL_116_DATA 0x00040D40
#define DDRSS_CTL_117_DATA 0x00040D40
#define DDRSS_CTL_118_DATA 0x00040D40
#define DDRSS_CTL_119_DATA 0x00040D40
#define DDRSS_CTL_120_DATA 0x00040D40
#define DDRSS_CTL_121_DATA 0x00000000
#define DDRSS_CTL_122_DATA 0x0000E325
#define DDRSS_CTL_122_DATA 0x00007173
#define DDRSS_CTL_123_DATA 0x00000000
#define DDRSS_CTL_124_DATA 0x00000000
#define DDRSS_CTL_125_DATA 0x00000000
@ -399,29 +399,29 @@
#define DDRSS_CTL_386_DATA 0x00000000
#define DDRSS_CTL_387_DATA 0x3A3A1B00
#define DDRSS_CTL_388_DATA 0x000A0000
#define DDRSS_CTL_389_DATA 0x0000019C
#define DDRSS_CTL_389_DATA 0x000000C6
#define DDRSS_CTL_390_DATA 0x00000200
#define DDRSS_CTL_391_DATA 0x00000200
#define DDRSS_CTL_392_DATA 0x00000200
#define DDRSS_CTL_393_DATA 0x00000200
#define DDRSS_CTL_394_DATA 0x000004D4
#define DDRSS_CTL_395_DATA 0x00001018
#define DDRSS_CTL_394_DATA 0x00000252
#define DDRSS_CTL_395_DATA 0x000007BC
#define DDRSS_CTL_396_DATA 0x00000204
#define DDRSS_CTL_397_DATA 0x000040E6
#define DDRSS_CTL_397_DATA 0x0000206A
#define DDRSS_CTL_398_DATA 0x00000200
#define DDRSS_CTL_399_DATA 0x00000200
#define DDRSS_CTL_400_DATA 0x00000200
#define DDRSS_CTL_401_DATA 0x00000200
#define DDRSS_CTL_402_DATA 0x0000C2B2
#define DDRSS_CTL_403_DATA 0x000288FC
#define DDRSS_CTL_402_DATA 0x0000613E
#define DDRSS_CTL_403_DATA 0x00014424
#define DDRSS_CTL_404_DATA 0x00000E15
#define DDRSS_CTL_405_DATA 0x000040E6
#define DDRSS_CTL_405_DATA 0x0000206A
#define DDRSS_CTL_406_DATA 0x00000200
#define DDRSS_CTL_407_DATA 0x00000200
#define DDRSS_CTL_408_DATA 0x00000200
#define DDRSS_CTL_409_DATA 0x00000200
#define DDRSS_CTL_410_DATA 0x0000C2B2
#define DDRSS_CTL_411_DATA 0x000288FC
#define DDRSS_CTL_410_DATA 0x0000613E
#define DDRSS_CTL_411_DATA 0x00014424
#define DDRSS_CTL_412_DATA 0x02020E15
#define DDRSS_CTL_413_DATA 0x03030202
#define DDRSS_CTL_414_DATA 0x00000022
@ -640,11 +640,11 @@
#define DDRSS_PI_167_DATA 0x02000200
#define DDRSS_PI_168_DATA 0x48120C04
#define DDRSS_PI_169_DATA 0x00104812
#define DDRSS_PI_170_DATA 0x000000CE
#define DDRSS_PI_170_DATA 0x00000063
#define DDRSS_PI_171_DATA 0x00000256
#define DDRSS_PI_172_DATA 0x00002073
#define DDRSS_PI_172_DATA 0x00001035
#define DDRSS_PI_173_DATA 0x00000256
#define DDRSS_PI_174_DATA 0x04002073
#define DDRSS_PI_174_DATA 0x04001035
#define DDRSS_PI_175_DATA 0x01010404
#define DDRSS_PI_176_DATA 0x00001501
#define DDRSS_PI_177_DATA 0x00150015
@ -689,22 +689,22 @@
#define DDRSS_PI_216_DATA 0x3212005B
#define DDRSS_PI_217_DATA 0x09000301
#define DDRSS_PI_218_DATA 0x04010504
#define DDRSS_PI_219_DATA 0x040006C9
#define DDRSS_PI_219_DATA 0x04000364
#define DDRSS_PI_220_DATA 0x0A032001
#define DDRSS_PI_221_DATA 0x2C31110A
#define DDRSS_PI_222_DATA 0x00002D1C
#define DDRSS_PI_223_DATA 0x6001071C
#define DDRSS_PI_223_DATA 0x6000838E
#define DDRSS_PI_224_DATA 0x1E202008
#define DDRSS_PI_225_DATA 0x2C311116
#define DDRSS_PI_226_DATA 0x00002D1C
#define DDRSS_PI_227_DATA 0x6001071C
#define DDRSS_PI_227_DATA 0x6000838E
#define DDRSS_PI_228_DATA 0x1E202008
#define DDRSS_PI_229_DATA 0x00019C16
#define DDRSS_PI_230_DATA 0x00001018
#define DDRSS_PI_231_DATA 0x000040E6
#define DDRSS_PI_232_DATA 0x000288FC
#define DDRSS_PI_233_DATA 0x000040E6
#define DDRSS_PI_234_DATA 0x000288FC
#define DDRSS_PI_229_DATA 0x0000C616
#define DDRSS_PI_230_DATA 0x000007BC
#define DDRSS_PI_231_DATA 0x0000206A
#define DDRSS_PI_232_DATA 0x00014424
#define DDRSS_PI_233_DATA 0x0000206A
#define DDRSS_PI_234_DATA 0x00014424
#define DDRSS_PI_235_DATA 0x02660010
#define DDRSS_PI_236_DATA 0x03030266
#define DDRSS_PI_237_DATA 0x002AF803

File diff suppressed because it is too large Load diff

View file

@ -80,8 +80,6 @@ static __maybe_unused void enable_mcu_esm_reset(void)
writel(stat, CTRLMMR_MCU_RST_CTRL);
}
#if defined(CONFIG_CPU_V7R)
/*
* RTC Erratum i2327 Workaround for Silicon Revision 1
*
@ -94,7 +92,7 @@ static __maybe_unused void enable_mcu_esm_reset(void)
*
* https://www.ti.com/lit/er/sprz487c/sprz487c.pdf
*/
void rtc_erratumi2327_init(void)
static __maybe_unused void rtc_erratumi2327_init(void)
{
u32 counter;
@ -112,19 +110,17 @@ void rtc_erratumi2327_init(void)
*/
writel(K3RTC_KICK0_UNLOCK_VALUE, REG_K3RTC_KICK0);
writel(K3RTC_KICK1_UNLOCK_VALUE, REG_K3RTC_KICK1);
return;
}
#endif
void board_init_f(ulong dummy)
{
struct udevice *dev;
int ret;
#if defined(CONFIG_CPU_V7R)
if (IS_ENABLED(CONFIG_CPU_V7R)) {
setup_k3_mpu_regions();
rtc_erratumi2327_init();
#endif
}
/*
* Cannot delay this further as there is a chance that
@ -156,29 +152,28 @@ void board_init_f(ulong dummy)
preloader_console_init();
#ifdef CONFIG_K3_EARLY_CONS
/*
* Allow establishing an early console as required for example when
* doing a UART-based boot. Note that this console may not "survive"
* through a SYSFW PM-init step and will need a re-init in some way
* due to changing module clock frequencies.
*/
if (IS_ENABLED(CONFIG_K3_EARLY_CONS))
early_console_init();
#endif
#if defined(CONFIG_K3_LOAD_SYSFW)
/*
* Configure and start up system controller firmware. Provide
* the U-Boot console init function to the SYSFW post-PM configuration
* callback hook, effectively switching on (or over) the console
* output.
*/
if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
ret = is_rom_loaded_sysfw(&bootdata);
if (!ret)
panic("ROM has not loaded TIFS firmware\n");
k3_sysfw_loader(true, NULL, NULL);
#endif
}
/*
* Force probe of clk_k3 driver here to ensure basic default clock
@ -209,11 +204,11 @@ void board_init_f(ulong dummy)
enable_mcu_esm_reset();
}
#if defined(CONFIG_K3_AM64_DDRSS)
if (IS_ENABLED(CONFIG_K3_AM64_DDRSS)) {
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret)
panic("DRAM init failed: %d\n", ret);
#endif
}
spl_enable_dcache();
}
@ -225,9 +220,15 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
u32 bootmode_cfg = (devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
switch (bootmode) {
case BOOT_DEVICE_EMMC:
if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) {
if (spl_mmc_emmc_boot_partition(mmc))
return MMCSD_MODE_EMMCBOOT;
return MMCSD_MODE_FS;
}
if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4))
return MMCSD_MODE_FS;
return MMCSD_MODE_EMMCBOOT;
case BOOT_DEVICE_MMC:
if (bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_FS_RAW_MASK)

View file

@ -6,7 +6,7 @@
* Jan Kiszka <jan.kiszka@siemens.com>
*/
#include <env/ti/ti_armv7_common.env>
#include <env/ti/ti_common.env>
usb_pgood_delay=900

View file

@ -1,4 +1,4 @@
#include <env/ti/ti_armv7_common.env>
#include <env/ti/ti_common.env>
#include <env/ti/mmc.env>
default_device_tree=ti/k3-am62a7-sk.dtb

View file

@ -6,3 +6,10 @@ F: board/ti/am62x/
F: include/configs/am62x_evm.h
F: configs/am62x_evm_r5_defconfig
F: configs/am62x_evm_a53_defconfig
BEAGLEPLAY BOARD
M: Nishanth Menon <nm@ti.com>
M: Robert Nelson <robertcnelson@gmail.com>
M: Tom Rini <trini@konsulko.com>
S: Maintained
N: beagleplay

View file

@ -1,16 +1,14 @@
#include <env/ti/ti_armv7_common.env>
#include <env/ti/ti_common.env>
#include <env/ti/default_findfdt.env>
#include <env/ti/mmc.env>
default_device_tree=ti/k3-am625-sk.dtb
findfdt=
setenv name_fdt ${default_device_tree};
setenv fdtfile ${name_fdt}
name_kern=Image
console=ttyS2,115200n8
args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000
${mtdparts}
run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
boot_targets=ti_mmc mmc0 mmc1 usb pxe dhcp
boot=mmc
mmcdev=1
bootpart=1:2

View file

@ -0,0 +1,19 @@
#include <env/ti/ti_common.env>
#include <env/ti/default_findfdt.env>
#include <env/ti/mmc.env>
name_kern=Image
console=ttyS2,115200n8
args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000
run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
set_led_state_fail_load= led led-0 off; led led-1 on;
led led-2 off; led led-3 on; led led-4 off
set_led_state_start_load=led led-0 on; led led-1 off;
led led-2 on; led led-3 off; led led-4 on
boot=mmc
mmcdev=1
bootpart=1:1
bootdir=/boot
boot_targets=mmc1 mmc0 usb pxe
bootmeths=script extlinux efi pxe
rd_spec=-

View file

@ -0,0 +1,55 @@
# Defconfig fragment to apply on top of am62x_evm_a53_defconfig
CONFIG_DEFAULT_DEVICE_TREE="k3-am625-beagleplay"
CONFIG_OF_LIST="k3-am625-beagleplay"
CONFIG_SPL_OF_LIST="k3-am625-beagleplay"
CONFIG_BOOTCOMMAND="run set_led_state_start_load;run findfdt; run envboot; bootflow scan -lb;run set_led_state_fail_load"
CONFIG_EXT4_WRITE=y
CONFIG_LZO=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
# Use the Beagleplay env file
CONFIG_ENV_SOURCE_FILE="beagleplay"
# Do not use emmc boot - we will use FS only
CONFIG_SUPPORT_EMMC_BOOT=n
CONFIG_MMC_IO_VOLTAGE=y
# CONFIG_SPL_MMC_IO_VOLTAGE is not set
CONFIG_MMC_UHS_SUPPORT=y
# CONFIG_SPL_MMC_UHS_SUPPORT is not set
CONFIG_MMC_HS200_SUPPORT=y
# CONFIG_SPL_MMC_HS200_SUPPORT is not set
# Enable GPIO control
CONFIG_DM_GPIO=y
CONFIG_SPL_GPIO=y
CONFIG_DA8XX_GPIO=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPIO_READ=y
# Enable LEDs
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_SPL_LED=y
CONFIG_SPL_LED_GPIO=y
# Enable I2C bus
CONFIG_SPL_I2C=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_CMD_I2C=y
# Regulator
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_CMD_REGULATOR=y
CONFIG_DM_REGULATOR_TPS65219=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_TPS65219=y
CONFIG_CMD_PMIC=y
# Uses Realtek phy rather than TI phy
CONFIG_PHY_TI_DP83867=n
CONFIG_PHY_REALTEK=y
# No SPI flash on Beagleplay
CONFIG_SPI=n
CONFIG_SPI_FLASH=n
CONFIG_SPL_DM_SPI_FLASH=n
CONFIG_SPL_SPI_FLASH_SUPPORT=n

View file

@ -0,0 +1,15 @@
# Defconfig fragment to apply on top of:
# am62x_evm_r5_defconfig
#
CONFIG_DEFAULT_DEVICE_TREE="k3-am625-r5-beagleplay"
CONFIG_OF_LIST="k3-am625-r5-beagleplay"
CONFIG_SPL_OF_LIST="k3-am625-r5-beagleplay"
# Do spl board init
CONFIG_SPL_BOARD_INIT=y
# Do not use emmc boot - we will use FS only
CONFIG_SUPPORT_EMMC_BOOT=n
# No SPI flash on Beagleplay
CONFIG_SPI=n
CONFIG_SPI_FLASH=n
CONFIG_SPL_DM_SPI_FLASH=n
CONFIG_SPL_SPI_FLASH_SUPPORT=n

View file

@ -1,4 +1,4 @@
#include <env/ti/ti_armv7_common.env>
#include <env/ti/ti_common.env>
#include <env/ti/mmc.env>
#include <env/ti/k3_dfu.env>

View file

@ -1,4 +1,4 @@
#include <env/ti/ti_armv7_common.env>
#include <env/ti/ti_common.env>
#include <env/ti/mmc.env>
#include <env/ti/k3_dfu.env>
#if CONFIG_CMD_REMOTEPROC

View file

@ -1,4 +1,4 @@
#include <env/ti/ti_armv7_common.env>
#include <env/ti/ti_common.env>
#include <env/ti/mmc.env>
#include <env/ti/ufs.env>
#include <env/ti/k3_dfu.env>

View file

@ -1,4 +1,4 @@
#include <env/ti/ti_armv7_common.env>
#include <env/ti/ti_common.env>
#include <env/ti/mmc.env>
#include <env/ti/ufs.env>
#include <env/ti/k3_dfu.env>

View file

@ -1,4 +1,4 @@
#include <env/ti/ti_armv7_common.env>
#include <env/ti/ti_common.env>
#include <env/ti/ti_armv7_keystone2.env>
findfdt=setenv fdtfile ${name_fdt}

View file

@ -1,4 +1,4 @@
#include <env/ti/ti_armv7_common.env>
#include <env/ti/ti_common.env>
#include <env/ti/ti_armv7_keystone2.env>
#include <env/ti/mmc.env>

View file

@ -1,4 +1,4 @@
#include <env/ti/ti_armv7_common.env>
#include <env/ti/ti_common.env>
#include <env/ti/ti_armv7_keystone2.env>
findfdt=setenv fdtfile ${name_fdt}

View file

@ -1,4 +1,4 @@
#include <env/ti/ti_armv7_common.env>
#include <env/ti/ti_common.env>
#include <env/ti/ti_armv7_keystone2.env>
findfdt=setenv fdtfile ${name_fdt}

View file

@ -28,8 +28,8 @@ int dram_init(void)
{
gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE);
if (gd->ram_size < SZ_64M)
puts("## WARNING: Less than 64MB RAM detected\n");
if (gd->ram_size < SZ_512M)
puts("## WARNING: Less than 512MB RAM detected\n");
return 0;
}

View file

@ -25,11 +25,13 @@ CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="run envboot; run distro_bootcmd;"
CONFIG_BOOTSTD_FULL=y
CONFIG_BOOTSTD_DEFAULTS=y
CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb"
CONFIG_SPL_MAX_SIZE=0x58000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x80c80000
@ -69,6 +71,7 @@ CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_SPL_MMC_SDHCI_ADMA=y

View file

@ -92,6 +92,7 @@ CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_SPL_MISC=y
CONFIG_ESM_K3=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_SPL_MMC_SDHCI_ADMA=y

View file

@ -0,0 +1,322 @@
.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
.. sectionauthor:: Nishanth Menon <nm@ti.com>
AM62x Beagleboard.org Beagleplay
================================
Introduction:
-------------
BeagleBoard.org BeaglePlay is an easy to use, affordable open source
hardware single board computer based on the Texas Instruments AM625
SoC that allows you to create connected devices that work even at long
distances using IEEE 802.15.4g LR-WPAN and IEEE 802.3cg 10Base-T1L.
Expansion is provided over open standards based mikroBUS, Grove and
QWIIC headers among other interfaces.
Further information can be found at:
* Product Page: https://beagleplay.org/
* Hardware documentation: https://git.beagleboard.org/beagleplay/beagleplay
Boot Flow:
----------
Below is the pictorial representation of boot flow:
.. image:: img/boot_diagram_k3_current.svg
:alt: Boot flow diagram
- On this platform, 'TI Foundational Security' (TIFS) functions as the
security enclave master while 'Device Manager' (DM), also known as the
'TISCI server' in "TI terminology", offers all the essential services.
The A53 or M4F (Aux core) sends requests to TIFS/DM to accomplish these
services, as illustrated in the diagram above.
Sources:
--------
.. include:: k3.rst
:start-after: .. k3_rst_include_start_boot_sources
:end-before: .. k3_rst_include_end_boot_sources
Build procedure:
----------------
0. Setup the environment variables:
.. include:: k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_desc
:end-before: .. k3_rst_include_end_common_env_vars_desc
.. include:: k3.rst
:start-after: .. k3_rst_include_start_board_env_vars_desc
:end-before: .. k3_rst_include_end_board_env_vars_desc
Set the variables corresponding to this platform:
.. include:: k3.rst
:start-after: .. k3_rst_include_start_common_env_vars_defn
:end-before: .. k3_rst_include_end_common_env_vars_defn
.. code-block:: bash
$ export UBOOT_CFG_CORTEXR="am62x_evm_r5_defconfig beagleplay_r5.config"
$ export UBOOT_CFG_CORTEXA="am62x_evm_a53_defconfig beagleplay_a53.config"
$ export TFA_BOARD=lite
$ # we dont use any extra TFA parameters
$ unset TFA_EXTRA_ARGS
$ export OPTEE_PLATFORM=k3-am62x
$ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y"
.. include:: am62x_sk.rst
:start-after: .. am62x_evm_rst_include_start_build_steps
:end-before: .. am62x_evm_rst_include_end_build_steps
Target Images
--------------
Copy the below images to an SD card and boot:
* tiboot3-am62x-gp-evm.bin from R5 build as tiboot3.bin
* tispl.bin_unsigned from Cortex-A build as tispl.bin
* u-boot.img_unsigned from Cortex-A build as u-boot.img
Image formats
-------------
- tiboot3.bin
.. image:: img/multi_cert_tiboot3.bin.svg
:alt: tiboot3.bin image format
- tispl.bin
.. image:: img/dm_tispl.bin.svg
:alt: tispl.bin image format
Additional hardware for U-Boot development
------------------------------------------
* Serial Console is critical for U-Boot development on BeaglePlay. See
`BeaglePlay serial console documentation
<https://docs.beagleboard.org/latest/boards/beagleplay/demos-and-tutorials/using-serial-console.html>`_.
* uSD is preferred option over eMMC, and a SD/MMC reader will be needed.
* (optionally) JTAG is useful when working with very early stages of boot.
Default storage options
-----------------------
There are multiple storage media options on BeaglePlay, but primarily:
* Onboard eMMC (default) - reliable, fast and meant for deployment use.
* SD/MMC card interface (hold 'USR' switch and power on) - Entirely
depends on the SD card quality.
Flash to uSD card or how to deal with "bricked" Board
--------------------------------------------------------
When deploying or working on Linux, it's common to use the onboard
eMMC. However, avoiding the eMMC and using the uSD card is safer when
working with U-Boot.
If you choose to hand format your own bootable uSD card, be
aware that it can be difficult. The following information
may be helpful, but remember that it is only sometimes
reliable, and partition options can cause issues. These
can potentially help:
* https://git.ti.com/cgit/arago-project/tisdk-setup-scripts/tree/create-sdcard.sh
* https://elinux.org/Beagleboard:Expanding_File_System_Partition_On_A_microSD
The simplest option is to start with a standard distribution
image like those in `BeagleBoard.org Distros Page
<https://www.beagleboard.org/distros>`_ and download a disk image for
BeaglePlay. Pick a 16GB+ uSD card to be on the safer side.
With an SD/MMC Card reader and `Balena Etcher
<https://etcher.balena.io/>`_, having a functional setup in minutes is
a trivial matter, and it works on almost all Host Operating Systems.
Yes Windows users, Windows Subsystem for Linux(WSL) based development
with U-Boot and update uSD card is practical.
Updating U-Boot is a matter of copying the tiboot3.bin, tispl.bin and
u-boot.img to the "BOOT" partition of the uSD card. Remember to sync
and unmount (or Eject - depending on the Operating System) the uSD
card prior to physically removing from SD card reader.
Also see following section on switch setting used for booting using
uSD card.
.. note::
Great news! If the board has not been damaged physically, there's no
need to worry about it being "bricked" on this platform. You only have
to flash an uSD card, plug it in, and reinstall the image on eMMC. This
means that even if you make a mistake, you can quickly fix it and rest
easy.
If you are frequently working with uSD cards, you might find the
following useful:
* `USB-SD-Mux <https://www.linux-automation.com/en/products/usb-sd-mux.html>`_
* `SD-Wire <https://wiki.tizen.org/SDWire>`_
Flash to eMMC
-------------
The eMMC layout selected is user-friendly for developers. The
boot hardware partition of the eMMC only contains the fixed-size
tiboot3.bin image. This is because the contents of the boot partitions
need to run from the SoC's internal SRAM, which remains a fixed size
constant. The other components of the boot sequence, such as tispl.bin
and u-boot.img, are located in the /BOOT partition in the User Defined
Area (UDA) hardware partition of the eMMC. These components can vary
significantly in size. The choice of keeping tiboot3.bin in boot0 or
boot1 partition depends on A/B update requirements.
.. image:: img/beagleplay_emmc.svg
:alt: eMMC partitions and boot file organization for BeaglePlay
The following are the steps from Linux shell to program eMMC:
.. code-block:: bash
# # Enable Boot0 boot
# mmc bootpart enable 1 2 /dev/mmcblk0
# mmc bootbus set single_backward x1 x8 /dev/mmcblk0
# mmc hwreset enable /dev/mmcblk0
# # Clear eMMC boot0
# echo '0' >> /sys/class/block/mmcblk0boot0/force_ro
# dd if=/dev/zero of=/dev/mmcblk0boot0 count=32 bs=128k
# # Write tiboot3.bin
# dd if=tiboot3.bin of=/dev/mmcblk0boot0 bs=128k
# # Copy the rest of the boot binaries
# mount /dev/mmcblk0p1 /boot/firmware
# cp tispl.bin /boot/firmware
# cp u-boot.img /boot/firmware
# sync
.. warning ::
U-Boot is configured to prioritize booting from an SD card if it
detects a valid boot partition and boot files on it, even if the
system initially booted from eMMC. The boot order is set as follows:
* SD/MMC
* eMMC
* USB
* PXE
LED patterns during boot
------------------------
.. list-table:: USR LED status indication
:widths: 16 16
:header-rows: 1
* - USR LEDs (012345)
- Indicates
* - 00000
- Boot failure or R5 image not started up
* - 11111
- A53 SPL/U-boot has started up
* - 10101
- OS boot process has been initiated
* - 01010
- OS boot process failed and drops to U-Boot shell
.. note ::
In the table above, 0 indicates LED switched off and 1 indicates LED
switched ON.
.. warning ::
If the "red" power LED is not glowing, the system power supply is not
functional. Please refer to `BeaglePlay documentation
<https://beagleplay.org/>`_ for further information.
A53 SPL DDR Memory Layout
-------------------------
.. include:: am62x_sk.rst
:start-after: .. am62x_evm_rst_include_start_ddr_mem_layout
:end-before: .. am62x_evm_rst_include_end_ddr_mem_layout
Switch Setting for Boot Mode
----------------------------
The boot time option is configured via "USR" button on the board.
See `Beagleplay Schematics <https://git.beagleboard.org/beagleplay/beagleplay/-/blob/main/BeaglePlay_sch.pdf>`_
for details.
.. list-table:: Boot Modes
:widths: 16 16 16
:header-rows: 1
* - USR Switch Position
- Primary Boot
- Secondary Boot
* - Not Pressed
- eMMC
- UART
* - Pressed
- SD/MMC File System (FS) mode
- USB Device Firmware Upgrade (DFU) mode
To switch to SD card boot mode, hold the USR button while powering on
with Type-C power supply, then release when power LED lights up.
Debugging U-Boot
----------------
See :ref:`Common Debugging environment - OpenOCD<k3_rst_refer_openocd>`: for
detailed setup and debugging information.
.. warning::
**OpenOCD support since**: v0.12.0
If the default package version of OpenOCD in your development
environment's distribution needs to be updated, it might be necessary to
build OpenOCD from the source.
.. include:: k3.rst
:start-after: .. k3_rst_include_start_openocd_connect_tag_connect
:end-before: .. k3_rst_include_end_openocd_connect_tag_connect
.. include:: k3.rst
:start-after: .. k3_rst_include_start_openocd_cfg_external_intro
:end-before: .. k3_rst_include_end_openocd_cfg_external_intro
For example, with BeaglePlay (AM62X platform), the openocd_connect.cfg:
.. code-block:: tcl
# TUMPA example:
# http://www.tiaowiki.com/w/TIAO_USB_Multi_Protocol_Adapter_User's_Manual
source [find interface/ftdi/tumpa.cfg]
transport select jtag
# default JTAG configuration has only SRST and no TRST
reset_config srst_only srst_push_pull
# delay after SRST goes inactive
adapter srst delay 20
if { ![info exists SOC] } {
# Set the SoC of interest
set SOC am625
}
source [find target/ti_k3.cfg]
ftdi tdo_sample_edge falling
# Speeds for FT2232H are in multiples of 2, and 32MHz is tops
# max speed we seem to achieve is ~20MHz.. so we pick 16MHz
adapter speed 16000

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@ -0,0 +1,697 @@
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After

Width:  |  Height:  |  Size: 24 KiB

View file

@ -30,6 +30,7 @@ K3 Based SoCs
.. toctree::
:maxdepth: 1
am62x_beagleplay
am62x_sk
../toradex/verdin-am62
am64x_evm

View file

@ -9,12 +9,6 @@
#ifndef __CONFIG_AM625_EVM_H
#define __CONFIG_AM625_EVM_H
#include <config_distro_bootcmd.h>
#include <env/ti/mmc.h>
/* DDR Configuration */
#define CFG_SYS_SDRAM_BASE1 0x880000000
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>

View file

@ -200,7 +200,7 @@
#define CFG_EXTRA_ENV_SETTINGS \
BOOTENV
#endif
#endif /* CONFIG_DISTRO_DEFAULTS */
#endif /* CONFIG_ARM64 */

View file

@ -13,8 +13,7 @@
/* DDR Configuration */
#define CFG_SYS_SDRAM_BASE 0x80000000
#define CFG_SYS_SDRAM_BASE1 0x880000000
#define CFG_SYS_SDRAM_SIZE SZ_2G /* Maximum supported size */
#define CFG_SYS_SDRAM_SIZE SZ_2G /* Maximum supported size, auto-detection is used */
#define MEM_LAYOUT_ENV_SETTINGS \
"fdt_addr_r=0x90200000\0" \
@ -46,10 +45,20 @@
"fdt_board=dev\0" \
"setup=setenv setupargs console=tty1 console=${console},${baudrate} " \
"consoleblank=0 earlycon=ns16550a,mmio32,0x02800000\0" \
"update_uboot=askenv confirm Did you load flash.bin (y/N)?; " \
"update_tiboot3=askenv confirm Did you load tiboot3.bin (y/N)?; " \
"if test \"$confirm\" = \"y\"; then " \
"setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
"${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \
"${blkcnt}; fi\0" \
"update_tispl=askenv confirm Did you load tispl.bin (y/N)?; " \
"if test \"$confirm\" = \"y\"; then " \
"setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
"${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x400 " \
"${blkcnt}; fi\0" \
"update_uboot=askenv confirm Did you load u-boot.img (y/N)?; " \
"if test \"$confirm\" = \"y\"; then " \
"setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
"${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x1400 " \
"${blkcnt}; fi\0"
#endif /* __VERDIN_AM62_H */

12
include/env/ti/default_findfdt.env vendored Normal file
View file

@ -0,0 +1,12 @@
default_device_tree=CONFIG_DEFAULT_DEVICE_TREE
default_device_tree_arch=ti
#ifdef CONFIG_ARM64
findfdt=
setenv name_fdt ${default_device_tree_arch}/${default_device_tree}.dtb;
setenv fdtfile ${name_fdt}
#else
default_device_tree_subarch=omap
findfdt=
setenv name_fdt ${default_device_tree_arch}/${default_device_tree_subarch}/${default_device_tree}.dtb;
setenv fdtfile ${name_fdt}
#endif

View file

@ -5,7 +5,9 @@ args_mmc=run finduuid;setenv bootargs console=${console}
${optargs}
root=PARTUUID=${uuid} rw
rootfstype=${mmcrootfstype}
#ifndef CONFIG_BOOTSTD
loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr
#endif
bootscript=echo Running bootscript from mmc${mmcdev} ...;
source ${loadaddr}
bootenvfile=uEnv.txt
@ -15,10 +17,10 @@ loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenvfile}
loadimage=load ${devtype} ${bootpart} ${loadaddr} ${bootdir}/${bootfile}
loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/dtb/${fdtfile}
get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/dtb/${name_fdt}
envboot=mmc dev ${mmcdev};
envboot=if mmc dev ${mmcdev}; then
if mmc rescan; then
echo SD/MMC found on device ${mmcdev};
if run loadbootscript; then
if test -n "${loadbootscript}" && run loadbootscript; then
run bootscript;
else
if run loadbootenv; then
@ -31,6 +33,7 @@ envboot=mmc dev ${mmcdev};
fi;
fi;
fi;
fi;
mmcloados=
if test ${boot_fdt} = yes || test ${boot_fdt} = try; then
if run get_fdt_mmc; then
@ -45,7 +48,7 @@ mmcloados=
else
bootz;
fi;
mmcboot=mmc dev ${mmcdev};
mmcboot=if mmc dev ${mmcdev}; then
devnum=${mmcdev};
devtype=mmc;
if mmc rescan; then
@ -59,6 +62,7 @@ mmcboot=mmc dev ${mmcdev};
fi;
fi;
fi;
fi;
init_mmc=run args_all args_mmc
get_overlay_mmc=