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clk: renesas: Synchronize R8A774E1 RZ/G2H clock tables with Linux 6.5.3

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Synchronize R8A774E1 RZ/G2H clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut 2023-09-17 16:11:41 +02:00
parent ff682fc80d
commit 610b078b33
1 changed files with 3 additions and 3 deletions
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6
drivers/clk/renesas/r8a774e1-cpg-mssr.c
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@ -48,7 +48,7 @@ enum clk_ids {
MOD_CLK_BASE
};
static const struct cpg_core_clk r8a774e1_core_clks[] = {
static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@ -123,7 +123,7 @@ static const struct cpg_core_clk r8a774e1_core_clks[] = {
DEF_BASE("r", R8A774E1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
static const struct mssr_mod_clk r8a774e1_mod_clks[] = {
static const struct mssr_mod_clk r8a774e1_mod_clks[] __initconst = {
DEF_MOD("fdp1-1", 118, R8A774E1_CLK_S0D1),
DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1),
DEF_MOD("tmu4", 121, R8A774E1_CLK_S0D6),
@ -286,7 +286,7 @@ static const struct mssr_mod_clk r8a774e1_mod_clks[] = {
(((md) & BIT(19)) >> 18) | \
(((md) & BIT(17)) >> 17))
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
/* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
{ 1, 192, 1, 192, 1, 16, },
{ 1, 192, 1, 128, 1, 16, },