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mpc83xx: cosmetic: sbc8349.h checkpatch compliance

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Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Joe Hershberger 2011-10-11 23:57:25 -05:00 committed by Kim Phillips
parent 80ae4df929
commit 60e1dc151e
1 changed files with 143 additions and 93 deletions
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122
include/configs/sbc8349.h
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@ -114,7 +114,9 @@
* NB: manual DDR setup untested on sbc834x * NB: manual DDR setup untested on sbc834x
*/ */
#define CONFIG_SYS_DDR_SIZE 256 /* MB */ #define CONFIG_SYS_DDR_SIZE 256 /* MB */
#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN \
| CSCONFIG_ROW_BIT_13 \
| CSCONFIG_COL_BIT_10)
#define CONFIG_SYS_DDR_TIMING_1 0x36332321 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
@ -122,10 +124,12 @@
#if defined(CONFIG_DDR_32BIT) #if defined(CONFIG_DDR_32BIT)
/* set burst length to 8 for 32-bit data path */ /* set burst length to 8 for 32-bit data path */
#define CONFIG_SYS_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */ /* DLL,normal,seq,4/2.5, 8 burst len */
#define CONFIG_SYS_DDR_MODE 0x00000023
#else #else
/* the default burst length is 4 - for 64-bit data path */ /* the default burst length is 4 - for 64-bit data path */
#define CONFIG_SYS_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ /* DLL,normal,seq,4/2.5, 4 burst len */
#define CONFIG_SYS_DDR_MODE 0x00000022
#endif #endif
#endif #endif
@ -144,12 +148,13 @@
#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \ #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
(2 << BR_PS_SHIFT) | /* 16 bit port size */ \ | (2 << BR_PS_SHIFT) /* 16 bit port */ \
BR_V) /* valid */ | BR_V) /* valid */
#define CONFIG_SYS_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */ #define CONFIG_SYS_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */ /* window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
@ -168,10 +173,13 @@
#endif #endif
#define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
/* Size of used area in RAM*/
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
@ -209,7 +217,8 @@
* FIXME: the top 17 bits of BR2. * FIXME: the top 17 bits of BR2.
*/ */
#define CONFIG_SYS_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ /* Port-size=32bit, MSEL=SDRAM */
#define CONFIG_SYS_BR2_PRELIM 0xF0001861
#define CONFIG_SYS_LBLAWBAR2_PRELIM 0xF0000000 #define CONFIG_SYS_LBLAWBAR2_PRELIM 0xF0000000
#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64M */ #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64M */
@ -229,8 +238,10 @@
#define CONFIG_SYS_OR2_PRELIM 0xFC006901 #define CONFIG_SYS_OR2_PRELIM 0xFC006901
#define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ /* LB sdram refresh timer, about 6us */
#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ #define CONFIG_SYS_LBC_LSRT 0x32000000
/* LB refresh timer prescal, 266MHz/32 */
#define CONFIG_SYS_LBC_MRTPR 0x20000000
#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
| LSDMR_BSMA1516 \ | LSDMR_BSMA1516 \
@ -239,8 +250,7 @@
| LSDMR_ACTTORW3 \ | LSDMR_ACTTORW3 \
| LSDMR_BL8 \ | LSDMR_BL8 \
| LSDMR_WRC3 \ | LSDMR_WRC3 \
| LSDMR_CL3 \ | LSDMR_CL3)
)
/* /*
* SDRAM Controller configuration sequence. * SDRAM Controller configuration sequence.
@ -439,9 +449,11 @@
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif #endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ /* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ /* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/* /*
@ -449,7 +461,8 @@
* have to be in the first 256 MB of memory, since this is * have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization. * the maximum mapped by the Linux kernel during initialization.
*/ */
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
@ -523,8 +536,8 @@
#define CONFIG_SYS_SICRL SICRL_LDP_A #define CONFIG_SYS_SICRL SICRL_LDP_A
#define CONFIG_SYS_HID0_INIT 0x000000000 #define CONFIG_SYS_HID0_INIT 0x000000000
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
HID0_ENABLE_INSTRUCTION_CACHE) | HID0_ENABLE_INSTRUCTION_CACHE)
/* #define CONFIG_SYS_HID0_FINAL (\ /* #define CONFIG_SYS_HID0_FINAL (\
HID0_ENABLE_INSTRUCTION_CACHE |\ HID0_ENABLE_INSTRUCTION_CACHE |\
@ -537,15 +550,31 @@
#define CONFIG_HIGH_BATS 1 /* High BATs supported */ #define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR @ 0x00000000 */ /* DDR @ 0x00000000 */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | BATL_PP_10 \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
/* PCI @ 0x80000000 */ /* PCI @ 0x80000000 */
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | BATL_PP_10 \
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
| BATL_PP_10 \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#else #else
#define CONFIG_SYS_IBAT1L (0) #define CONFIG_SYS_IBAT1L (0)
#define CONFIG_SYS_IBAT1U (0) #define CONFIG_SYS_IBAT1U (0)
@ -554,10 +583,21 @@
#endif #endif
#ifdef CONFIG_MPC83XX_PCI2 #ifdef CONFIG_MPC83XX_PCI2
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | BATL_PP_10 \
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
| BATL_PP_10 \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#else #else
#define CONFIG_SYS_IBAT3L (0) #define CONFIG_SYS_IBAT3L (0)
#define CONFIG_SYS_IBAT3U (0) #define CONFIG_SYS_IBAT3U (0)
@ -566,12 +606,20 @@
#endif #endif
/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) | BATL_PP_10 \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \ #define CONFIG_SYS_IBAT6L (0xF0000000 \
BATL_GUARDEDSTORAGE) | BATL_PP_10 \
| BATL_MEMCOHERENCE \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT7L (0) #define CONFIG_SYS_IBAT7L (0)
@ -613,7 +661,8 @@
#define CONFIG_ROOTPATH "/tftpboot/rootfs" #define CONFIG_ROOTPATH "/tftpboot/rootfs"
#define CONFIG_BOOTFILE "uImage" #define CONFIG_BOOTFILE "uImage"
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ /* default location for tftp and bootm */
#define CONFIG_LOADADDR 800000
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
@ -647,7 +696,8 @@
#define CONFIG_NFSBOOTCOMMAND \ #define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \ "setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \ "nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
"$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \ "console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \ "tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \ "tftp $fdtaddr $fdtfile;" \