Merge branch '2019-07-12-master-imports'

- First round of TI Davinci updates
- Some OMAP3 DM updates
- Other misc updates

.travis.yml

@@ -365,11 +365,13 @@ matrix:
     - name: "test/py sandbox"
       env:
         - TEST_PY_BD="sandbox"
+          TEST_PY_TEST_SPEC="not pci"
           BUILDMAN="^sandbox$"
           TOOLCHAIN="i386"
     - name: "test/py sandbox with clang"
       env:
         - TEST_PY_BD="sandbox"
+          TEST_PY_TEST_SPEC="not pci"
           BUILDMAN="^sandbox$"
           OVERRIDE="clang-7"
     - name: "test/py sandbox_spl"
@@ -382,6 +384,7 @@ matrix:
     - name: "test/py sandbox_flattree"
       env:
         - TEST_PY_BD="sandbox_flattree"
+          TEST_PY_TEST_SPEC="not pci"
           BUILDMAN="^sandbox_flattree$"
           TOOLCHAIN="i386"
     - name: "test/py vexpress_ca15_tc2"

arch/arm/dts/Makefile

@@ -30,7 +30,8 @@ dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb
 
 dtb-$(CONFIG_ARCH_DAVINCI) += \
 	da850-evm.dtb \
-	da850-lcdk.dtb
+	da850-lcdk.dtb \
+	da850-lego-ev3.dtb
 
 dtb-$(CONFIG_KIRKWOOD) += \
 	kirkwood-atl-sbx81lifkw.dtb \
@@ -288,7 +289,8 @@ dtb-$(CONFIG_AM33XX) += \
 	am335x-chiliboard.dtb \
 	am335x-sl50.dtb \
 	am335x-base0033.dtb \
-	am335x-guardian.dtb
+	am335x-guardian.dtb \
+	am335x-wega-rdk.dtb
 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb	\
 	am43x-epos-evm.dtb \
 	am437x-idk-evm.dtb \

arch/arm/dts/am335x-phycore-som.dtsi

@@ -0,0 +1,322 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015 Phytec Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "am33xx.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	model = "Phytec AM335x phyCORE";
+	compatible = "phytec,am335x-phycore-som", "ti,am33xx";
+
+	aliases {
+		rtc0 = &i2c_rtc;
+		rtc1 = &rtc;
+	};
+
+	cpus {
+		cpu@0 {
+			cpu0-supply = <&vdd1_reg>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>; /* 256 MB */
+	};
+
+	regulators {
+		compatible = "simple-bus";
+
+		vcc5v: fixedregulator0 {
+			compatible = "regulator-fixed";
+			regulator-name = "vcc5v";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+	};
+};
+
+/* Crypto Module */
+&aes {
+	status = "okay";
+};
+
+&sham {
+	status = "okay";
+};
+
+/* Ethernet */
+&am33xx_pinmux {
+	ethernet0_pins: pinmux_ethernet0 {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_crs.rmii1_crs_dv */
+			AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxerr.rmii1_rxerr */
+			AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE1)		/* mii1_txen.rmii1_txen */
+			AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE1)		/* mii1_txd1.rmii1_txd1 */
+			AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE1)		/* mii1_txd0.rmii1_txd0 */
+			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxd1.rmii1_rxd1 */
+			AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxd0.rmii1_rxd0 */
+			AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* rmii1_refclk.rmii1_refclk */
+		>;
+	};
+
+	mdio_pins: pinmux_mdio {
+		pinctrl-single,pins = <
+			/* MDIO */
+			AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
+			AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
+		>;
+	};
+};
+
+&cpsw_emac0 {
+	phy-handle = <&phy0>;
+	phy-mode = "rmii";
+	dual_emac_res_vlan = <1>;
+};
+
+&davinci_mdio {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mdio_pins>;
+	status = "okay";
+
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+	};
+};
+
+&mac {
+	slaves = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&ethernet0_pins>;
+	status = "okay";
+};
+
+/* I2C Busses */
+&am33xx_pinmux {
+	i2c0_pins: pinmux_i2c0 {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
+			AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
+		>;
+	};
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c0_pins>;
+	clock-frequency = <400000>;
+	status = "okay";
+
+	tps: pmic@2d {
+		reg = <0x2d>;
+	};
+
+	i2c_tmp102: temp@4b {
+		compatible = "ti,tmp102";
+		reg = <0x4b>;
+		status = "disabled";
+	};
+
+	i2c_eeprom: eeprom@52 {
+		compatible = "atmel,24c32";
+		pagesize = <32>;
+		reg = <0x52>;
+		status = "disabled";
+	};
+
+	i2c_rtc: rtc@68 {
+		compatible = "microcrystal,rv4162";
+		reg = <0x68>;
+		status = "disabled";
+	};
+};
+
+/* NAND memory */
+&am33xx_pinmux {
+		nandflash_pins: pinmux_nandflash {
+			pinctrl-single,pins = <
+			AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
+			AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
+			AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
+			AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
+			AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
+			AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
+			AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
+			AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
+			AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
+			AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0 */
+			AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
+			AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
+			AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
+			AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
+		>;
+	};
+};
+
+&elm {
+	status = "okay";
+};
+
+&gpmc {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&nandflash_pins>;
+	ranges = <0 0 0x08000000 0x1000000>;   /* CS0: NAND */
+	nandflash: nand@0,0 {
+		compatible = "ti,omap2-nand";
+		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+		interrupt-parent = <&gpmc>;
+		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+			     <1 IRQ_TYPE_NONE>;	/* termcount */
+		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
+		nand-bus-width = <8>;
+		ti,nand-ecc-opt = "bch8";
+		gpmc,device-nand = "true";
+		gpmc,device-width = <1>;
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <30>;
+		gpmc,cs-wr-off-ns = <30>;
+		gpmc,adv-on-ns = <0>;
+		gpmc,adv-rd-off-ns = <30>;
+		gpmc,adv-wr-off-ns = <30>;
+		gpmc,we-on-ns = <0>;
+		gpmc,we-off-ns = <20>;
+		gpmc,oe-on-ns = <10>;
+		gpmc,oe-off-ns = <30>;
+		gpmc,access-ns = <30>;
+		gpmc,rd-cycle-ns = <30>;
+		gpmc,wr-cycle-ns = <30>;
+		gpmc,bus-turnaround-ns = <0>;
+		gpmc,cycle2cycle-delay-ns = <50>;
+		gpmc,cycle2cycle-diffcsen;
+		gpmc,clk-activation-ns = <0>;
+		gpmc,wr-access-ns = <30>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+
+		ti,elm-id = <&elm>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+};
+
+/* Power */
+#include "tps65910.dtsi"
+
+&tps {
+	vcc1-supply = <&vcc5v>;
+	vcc2-supply = <&vcc5v>;
+	vcc3-supply = <&vcc5v>;
+	vcc4-supply = <&vcc5v>;
+	vcc5-supply = <&vcc5v>;
+	vcc6-supply = <&vcc5v>;
+	vcc7-supply = <&vcc5v>;
+	vccio-supply = <&vcc5v>;
+
+	regulators {
+		vrtc_reg: regulator@0 {
+			regulator-always-on;
+		};
+
+		vio_reg: regulator@1 {
+			regulator-always-on;
+		};
+
+		vdd1_reg: regulator@2 {
+			/* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
+			regulator-name = "vdd_mpu";
+			regulator-min-microvolt = <912500>;
+			regulator-max-microvolt = <1378000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		vdd2_reg: regulator@3 {
+			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+			regulator-name = "vdd_core";
+			regulator-min-microvolt = <912500>;
+			regulator-max-microvolt = <1150000>;
+			regulator-boot-on;
+			regulator-always-on;
+		};
+
+		vdd3_reg: regulator@4 {
+			regulator-always-on;
+		};
+
+		vdig1_reg: regulator@5 {
+			regulator-name = "vdig1_1p8v";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		vdig2_reg: regulator@6 {
+			regulator-always-on;
+		};
+
+		vpll_reg: regulator@7 {
+			regulator-always-on;
+		};
+
+		vdac_reg: regulator@8 {
+			regulator-always-on;
+		};
+
+		vaux1_reg: regulator@9 {
+			regulator-always-on;
+		};
+
+		vaux2_reg: regulator@10 {
+			regulator-always-on;
+		};
+
+		vaux33_reg: regulator@11 {
+			regulator-always-on;
+		};
+
+		vmmc_reg: regulator@12 {
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+	};
+};
+
+/* SPI Busses */
+&am33xx_pinmux {
+	spi0_pins: pinmux_spi0 {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* spi0_clk.spi0_clk */
+			AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* spi0_d0.spi0_d0 */
+			AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0)	/* spi0_d1.spi0_d1 */
+			AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0)	/* spi0_cs0.spi0_cs0 */
+		>;
+	};
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pins>;
+	status = "okay";
+
+	serial_flash: m25p80@0 {
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <48000000>;
+		reg = <0x0>;
+		m25p,fast-read;
+		status = "disabled";
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+};

arch/arm/dts/am335x-wega-rdk-u-boot.dtsi

@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 DENX Software Engineering GmbH
+ */
+
+/ {
+	chosen {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		bootargs = "console=ttyO0,115200 earlyprintk";
+		stdout-path = &uart0;
+	};
+
+	ocp {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&i2c0 {
+	u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+};
+
+&mmc1 {
+	u-boot,dm-pre-reloc;
+	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+};

arch/arm/dts/am335x-wega-rdk.dts

@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015 Phytec Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "am335x-phycore-som.dtsi"
+#include "am335x-wega.dtsi"
+
+/* SoM */
+&i2c_eeprom {
+	status = "okay";
+};
+
+&i2c_rtc {
+	status = "okay";
+};

arch/arm/dts/am335x-wega.dtsi

@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015 Phytec Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+	model = "Phytec AM335x phyBOARD-WEGA";
+	compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx";
+
+	sound: sound_iface {
+		compatible = "ti,da830-evm-audio";
+	};
+
+	regulators {
+		compatible = "simple-bus";
+
+		vcc3v3: fixedregulator1 {
+			compatible = "regulator-fixed";
+			regulator-name = "vcc3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-boot-on;
+		};
+	};
+};
+
+/* Audio */
+&am33xx_pinmux {
+	mcasp0_pins: pinmux_mcasp0 {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x9AC, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahclkx.mcasp0_ahclkx */
+			AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0)  /* mcasp0_aclkx.mcasp0_aclkx */
+			AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0)  /* mcasp0_fsx.mcasp0_fsx */
+			AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0)  /* mcasp0_axr0.mcasp0_axr0 */
+			AM33XX_IOPAD(0x9A8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr1.mcasp0_axr1 */
+		>;
+	};
+};
+
+&i2c0 {
+	tlv320aic3007: tlv320aic3007@18 {
+		compatible = "ti,tlv320aic3007";
+		reg = <0x18>;
+		AVDD-supply = <&vcc3v3>;
+		IOVDD-supply = <&vcc3v3>;
+		DRVDD-supply = <&vcc3v3>;
+		DVDD-supply = <&vdig1_reg>;
+		status = "okay";
+	};
+};
+
+&mcasp0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcasp0_pins>;
+	op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */
+	tdm-slots = <2>;
+	serial-dir = <
+		2 1 0 0 /* # 0: INACTIVE, 1: TX, 2: RX */
+	>;
+	tx-num-evt = <16>;
+	rt-num-evt = <16>;
+	status = "okay";
+};
+
+&sound {
+	ti,model = "AM335x-Wega";
+	ti,audio-codec = <&tlv320aic3007>;
+	ti,mcasp-controller = <&mcasp0>;
+	ti,audio-routing =
+		"Line Out",		"LLOUT",
+		"Line Out",		"RLOUT",
+		"LINE1L",		"Line In",
+		"LINE1R",		"Line In";
+	clocks = <&mcasp0_fck>;
+	clock-names = "mclk";
+	status = "okay";
+};
+
+/* CAN Busses */
+&am33xx_pinmux {
+	dcan1_pins: pinmux_dcan1 {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x968, PIN_OUTPUT_PULLUP | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
+			AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
+		>;
+	};
+};
+
+&dcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&dcan1_pins>;
+	status = "okay";
+};
+
+/* Ethernet */
+&am33xx_pinmux {
+	ethernet1_pins: pinmux_ethernet1 {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a0.mii2_txen */
+			AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a1.mii2_rxdv */
+			AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a2.mii2_txd3 */
+			AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a3.mii2_txd2 */
+			AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a4.mii2_txd1 */
+			AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a5.mii2_txd0 */
+			AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a6.mii2_txclk */
+			AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a7.mii2_rxclk */
+			AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a8.mii2_rxd3 */
+			AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a9.mii2_rxd2 */
+			AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a10.mii2_rxd1 */
+			AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a11.mii2_rxd0 */
+			AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_wpn.mii2_rxerr */
+			AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ben1.mii2_col */
+		>;
+	};
+};
+
+&cpsw_emac1 {
+	phy-handle = <&phy1>;
+	phy-mode = "mii";
+	dual_emac_res_vlan = <2>;
+};
+
+&davinci_mdio {
+	phy1: ethernet-phy@1 {
+		reg = <1>;
+	};
+};
+
+&mac {
+	slaves = <2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&ethernet0_pins &ethernet1_pins>;
+	dual_emac = <1>;
+};
+
+/* MMC */
+&am33xx_pinmux {
+	mmc1_pins: pinmux_mmc1 {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat3.mmc0_dat3 */
+			AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat2.mmc0_dat2 */
+			AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat1.mmc0_dat1 */
+			AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat0.mmc0_dat0 */
+			AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_clk.mmc0_clk */
+			AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_cmd.mmc0_cmd */
+			AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE7)	/* spi0_cs1.mmc0_sdcd */
+		>;
+	};
+};
+
+&mmc1 {
+	vmmc-supply = <&vcc3v3>;
+	bus-width = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins>;
+	cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+/* Power */
+&vdig1_reg {
+	regulator-boot-on;
+	regulator-always-on;
+};
+
+/* UARTs */
+&am33xx_pinmux {
+	uart0_pins: pinmux_uart0 {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
+			AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+		>;
+	};
+
+	uart1_pins: pinmux_uart1_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)	/* uart1_rxd.uart1_rxd */
+			AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart1_txd.uart1_txd */
+			AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0)		/* uart1_ctsn.uart1_ctsn */
+			AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart1_rtsn.uart1_rtsn */
+		>;
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins>;
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+	status = "okay";
+};
+
+/* USB */
+&cppi41dma {
+	status = "okay";
+};
+
+&usb_ctrl_mod {
+	status = "okay";
+};
+
+&usb {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+};
+
+&usb0_phy {
+	status = "okay";
+};
+
+&usb1 {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb1_phy {
+	status = "okay";
+};

arch/arm/dts/da850-lego-ev3.dts

@@ -0,0 +1,89 @@
+/*
+ * Device tree for LEGO MINDSTORMS EV3
+ *
+ * Copyright (C) 2017 David Lechner <david@lechnology.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * This is an absolute minimum device tree instead of using the one from Linux
+ * because the bootloader on the EV3 is limited to 256k. This saves us >10k.
+ */
+
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "lego,ev3", "ti,da850";
+	model = "LEGO MINDSTORMS EV3";
+
+	aliases {
+		serial1 = &serial1;
+		spi0 = &spi0;
+	};
+
+	chosen {
+		stdout-path = &serial1;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0xc0000000 0x04000000>;
+	};
+
+	arm {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		intc: interrupt-controller@fffee000 {
+			compatible = "ti,cp-intc";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			ti,intc-size = <101>;
+			reg = <0xfffee000 0x2000>;
+		};
+	};
+
+	soc@1c00000 {
+		compatible = "simple-bus";
+		model = "da850";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x01c00000 0x400000>;
+		interrupt-parent = <&intc>;
+
+		mmc0: mmc@40000 {
+			compatible = "ti,da830-mmc";
+			reg = <0x40000 0x1000>;
+			cap-sd-highspeed;
+			cap-mmc-highspeed;
+			interrupts = <16>;
+			max-frequency = <50000000>;
+			bus-width = <4>;
+		};
+
+		spi0: spi@41000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "ti,da830-spi";
+			reg = <0x41000 0x1000>;
+			num-cs = <6>;
+			ti,davinci-spi-intr-line = <1>;
+			interrupts = <20>;
+
+			flash@0 {
+				compatible = "micron,n25q128a13", "jedec,spi-nor", "spi-flash";
+				reg = <0>;
+				spi-max-frequency = <50000000>;
+			};
+		};
+
+		serial1: serial@10c000 {
+			compatible = "ti,da830-uart", "ns16550a";
+			reg = <0x10c000 0x100>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			interrupts = <53>;
+		};
+	};
+};

arch/arm/dts/da850.dtsi

@@ -476,7 +476,7 @@
 		clocksource: timer@20000 {
 			compatible = "ti,da830-timer";
 			reg = <0x20000 0x1000>;
-			interrupts = <12>, <13>;
+			interrupts = <21>, <22>;
 			interrupt-names = "tint12", "tint34";
 			clocks = <&pll0_auxclk>;
 		};

arch/arm/dts/logicpd-som-lv-35xx-devkit-u-boot.dtsi

@@ -10,6 +10,11 @@
 	chosen {
 		stdout-path = &uart1;
 	};
+
+	aliases {
+		/delete-property/ serial1;
+		/delete-property/ serial2;
+	};
 };
 
 &i2c1 {
@@ -20,15 +25,8 @@
 	clock-frequency = <400000>;
 };
 
-&mmc1 {
+/delete-node/ &uart2;
-	cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;		/* gpio_110 */
+/delete-node/ &uart3;
-};
+/delete-node/ &mmc2;
-
+/delete-node/ &mmc3;
-&mmc2 {
-      status = "disabled";
-};
-
-&mmc3 {
-      status = "disabled";
-};
 

arch/arm/dts/logicpd-som-lv-37xx-devkit-u-boot.dtsi

@@ -10,6 +10,11 @@
 	chosen {
 		stdout-path = &uart1;
 	};
+
+	aliases {
+		/delete-property/ serial1;
+		/delete-property/ serial2;
+	};
 };
 
 &i2c1 {
@@ -20,11 +25,8 @@
 	clock-frequency = <400000>;
 };
 
-&mmc2 {
+/delete-node/ &uart2;
-      status = "disabled";
+/delete-node/ &uart3;
-};
+/delete-node/ &mmc2;
-
+/delete-node/ &mmc3;
-&mmc3 {
-      status = "disabled";
-};
 

arch/arm/dts/logicpd-som-lv-baseboard.dtsi

@@ -152,8 +152,8 @@
 	interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc1_pins>;
-	wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;	/* gpio_126 */
+	wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;		/* gpio_126 */
-	cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;		/* gpio_110 */
+	cd-gpios = <&gpio4 14 IRQ_TYPE_LEVEL_LOW>;		/* gpio_110 */
 	vmmc-supply = <&vmmc1>;
 	bus-width = <4>;
 	cap-power-off-card;

arch/arm/dts/logicpd-torpedo-35xx-devkit-u-boot.dtsi

@@ -6,6 +6,13 @@
 
 #include "omap3-u-boot.dtsi"
 
+/ {
+	aliases {
+		/delete-property/ serial1;
+		/delete-property/ serial2;
+	};
+};
+
 &i2c1 {
 	clock-frequency = <400000>;
 };
@@ -14,11 +21,7 @@
 	clock-frequency = <400000>;
 };
 
-&mmc2 {
+/delete-node/ &uart2;
-      status = "disabled";
+/delete-node/ &uart3;
-};
+/delete-node/ &mmc2;
-
+/delete-node/ &mmc3;
-&mmc3 {
-      status = "disabled";
-};
-

arch/arm/dts/logicpd-torpedo-37xx-devkit-u-boot.dtsi

@@ -6,6 +6,13 @@
 
 #include "omap3-u-boot.dtsi"
 
+/ {
+	aliases {
+		/delete-property/ serial1;
+		/delete-property/ serial2;
+	};
+};
+
 &i2c1 {
 	clock-frequency = <400000>;
 };
@@ -14,11 +21,8 @@
 	clock-frequency = <400000>;
 };
 
-&mmc2 {
+/delete-node/ &uart2;
-      status = "disabled";
+/delete-node/ &uart3;
-};
+/delete-node/ &mmc2;
-
+/delete-node/ &mmc3;
-&mmc3 {
-      status = "disabled";
-};
 

arch/arm/dts/omap3-evm-37xx.dts

@@ -90,19 +90,19 @@
 			label = "X-Loader";
 			reg = <0 0x80000>;
 		};
-		partition@0x80000 {
+		partition@80000 {
 			label = "U-Boot";
 			reg = <0x80000 0x1c0000>;
 		};
-		partition@0x1c0000 {
+		partition@1c0000 {
 			label = "Environment";
 			reg = <0x240000 0x40000>;
 		};
-		partition@0x280000 {
+		partition@280000 {
 			label = "Kernel";
 			reg = <0x280000 0x500000>;
 		};
-		partition@0x780000 {
+		partition@780000 {
 			label = "Filesystem";
 			reg = <0x780000 0x1f880000>;
 		};

arch/arm/dts/omap3-evm-common.dtsi

@@ -122,6 +122,7 @@
 };
 
 &mmc2 {
+	interrupts-extended = <&intc 86 &omap3_pmx_core 0x12e>;
 	vmmc-supply = <&wl12xx_vmmc>;
 	non-removable;
 	bus-width = <4>;
@@ -132,8 +133,10 @@
 	wlcore: wlcore@2 {
 		compatible = "ti,wl1271";
 		reg = <2>;
-		interrupt-parent = <&gpio5>;
+		/* gpio_149 with uart1_rts pad as wakeirq */
-		interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 149 */
+		interrupts-extended = <&gpio5 21 IRQ_TYPE_EDGE_RISING>,
+				      <&omap3_pmx_core 0x14e>;
+		interrupt-names = "irq", "wakeup";
 		ref-clock-frequency = <38400000>;
 	};
 };

arch/arm/dts/omap3-evm-processor-common.dtsi

@@ -86,6 +86,10 @@
 			OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
 			OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat2.sdmmc2_dat2 */
 			OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc2_dat3.sdmmc2_dat3 */
+			OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1)	/* sdmmc2_dat4.sdmmc2_dir_dat0 */
+			OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1)	/* sdmmc2_dat5.sdmmc2_dir_dat1 */
+			OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1)	/* sdmmc2_dat6.sdmmc2_dir_cmd */
+			OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1)	/* sdmmc2_dat7.sdmmc2_clkin */
 		>;
 	};
 
@@ -127,9 +131,13 @@
 		>;
 	};
 
+	/*
+	 * Note that gpio_150 pulled high with internal pull to prevent wlcore
+	 * reset on return from off mode in idle.
+	 */
 	wl12xx_gpio: pinmux_wl12xx_gpio {
 		pinctrl-single,pins = <
-			OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4)		/* uart1_cts.gpio_150 */
+			OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT_PULLUP | MUX_MODE7)		/* uart1_cts.gpio_150 */
 			OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4)		/* uart1_rts.gpio_149 */
 		>;
 	};

arch/arm/mach-omap2/Kconfig

@@ -11,7 +11,7 @@ config OMAP34XX
 	select ARM_ERRATA_454179
 	select ARM_ERRATA_621766
 	select ARM_ERRATA_725233
-	select USE_TINY_PRINTF
+	select USE_TINY_PRINTF if SPL
 	imply NAND_OMAP_GPMC
 	imply SPL_FS_EXT4
 	imply SPL_FS_FAT
@@ -186,6 +186,7 @@ source "board/ti/am43xx/Kconfig"
 source "board/ti/am335x/Kconfig"
 source "board/compulab/cm_t335/Kconfig"
 source "board/compulab/cm_t43/Kconfig"
+source "board/phytec/phycore_am335x_r2/Kconfig"
 
 config SPL_LDSCRIPT
         default "arch/arm/mach-omap2/u-boot-spl.lds"

arch/arm/mach-omap2/am33xx/Kconfig

@@ -177,6 +177,13 @@ config TARGET_PEPPER
 	select DM_SERIAL
 	imply CMD_DM
 
+config TARGET_PHYCORE_AM335X_R2
+	bool "Support phyCORE AM335X R2"
+	select DM
+	select DM_GPIO
+	select DM_SERIAL
+	imply CMD_DM
+
 config TARGET_PXM2
 	bool "Support pxm2"
 	select BOARD_LATE_INIT

arch/arm/mach-rmobile/Kconfig.32

@@ -57,7 +57,6 @@ config TARGET_BLANCHE
 	bool "Blanche board"
 	select DM
 	select DM_SERIAL
-	select USE_TINY_PRINTF
 	imply CMD_DM
 
 config TARGET_GOSE

board/davinci/da8xxevm/da850evm.c

@@ -216,21 +216,29 @@ static const struct pinmux_config gpio_pins[] = {
 };
 
 const struct pinmux_resource pinmuxes[] = {
+#ifndef CONFIG_SPL_BUILD
 #ifdef CONFIG_DRIVER_TI_EMAC
 	PINMUX_ITEM(emac_pins_mdio),
 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
 	PINMUX_ITEM(emac_pins_rmii),
 #else
 	PINMUX_ITEM(emac_pins_mii),
-#endif
+#endif /* CONFIG_DRIVER_TI_EMAC */
-#endif
+#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
+#endif /* CONFIG_SPL_BUILD */
 #ifdef CONFIG_SPI_FLASH
+#if !CONFIG_IS_ENABLED(PINCTRL)
 	PINMUX_ITEM(spi1_pins_base),
 	PINMUX_ITEM(spi1_pins_scs0),
 #endif
+#endif
+#if !CONFIG_IS_ENABLED(PINCTRL)
 	PINMUX_ITEM(uart2_pins_txrx),
 	PINMUX_ITEM(uart2_pins_rtscts),
+#endif
+#if !CONFIG_IS_ENABLED(PINCTRL)
 	PINMUX_ITEM(i2c0_pins),
+#endif
 #ifdef CONFIG_NAND_DAVINCI
 	PINMUX_ITEM(emifa_pins_cs3),
 	PINMUX_ITEM(emifa_pins_cs4),
@@ -241,8 +249,10 @@ const struct pinmux_resource pinmuxes[] = {
 #endif
 	PINMUX_ITEM(gpio_pins),
 #ifdef CONFIG_MMC_DAVINCI
+#if !CONFIG_IS_ENABLED(PINCTRL)
 	PINMUX_ITEM(mmc0_pins),
 #endif
+#endif
 };
 
 const int pinmuxes_size = ARRAY_SIZE(pinmuxes);

board/lego/ev3/README

@@ -50,3 +50,6 @@ software or a 3rd party program capable of uploading a firmware file.
 If you are booting from the microSD card, it is enough to just write uboot.bin
 to the flash. If you are not using a microSD card, you will need to create an
 image file using the layout described above.
+
+IMPORTANT: The EEPROM bootloader only copies 256k, so u-boot.img must not
+exceed that size!

board/lego/ev3/legoev3.c

@@ -25,11 +25,6 @@
 #include <asm/mach-types.h>
 #include <asm/setup.h>
 
-#ifdef CONFIG_MMC_DAVINCI
-#include <mmc.h>
-#include <asm/arch/sdmmc_defs.h>
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
 u8 board_rev;
@@ -38,23 +33,6 @@ u8 board_rev;
 #define EEPROM_REV_OFFSET	0x3F00
 #define EEPROM_MAC_OFFSET	0x3F06
 
-#ifdef CONFIG_MMC_DAVINCI
-static struct davinci_mmc mmc_sd0 = {
-	.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
-	.host_caps = MMC_MODE_4BIT,     /* DA850 supports only 4-bit SD/MMC */
-	.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
-	.version = MMC_CTLR_VERSION_2,
-};
-
-int board_mmc_init(bd_t *bis)
-{
-	mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
-
-	/* Add slot-0 to mmc subsystem */
-	return davinci_mmc_init(bis, &mmc_sd0);
-}
-#endif
-
 const struct pinmux_resource pinmuxes[] = {
 	PINMUX_ITEM(spi0_pins_base),
 	PINMUX_ITEM(spi0_pins_scs0),

board/phytec/phycore_am335x_r2/Kconfig

@@ -0,0 +1,15 @@
+if TARGET_PHYCORE_AM335X_R2
+
+config SYS_BOARD
+	default "phycore_am335x_r2"
+
+config SYS_VENDOR
+	default "phytec"
+
+config SYS_SOC
+	default "am33xx"
+
+config SYS_CONFIG_NAME
+	default "phycore_am335x_r2"
+
+endif

board/phytec/phycore_am335x_r2/MAINTAINERS

@@ -0,0 +1,7 @@
+phyCORE AM335x R2 WEGA BOARD
+M:	Niel Fourie <lusus@denx.de>
+M:	Parthiban Nallathambi <pn@denx.de>
+S:	Maintained
+F:	board/phytec/phycore_am335x_r2
+F:	include/configs/phycore_am335x_r2.h
+F:	configs/phycore-am335x-r2-wega_defconfig

board/phytec/phycore_am335x_r2/Makefile

@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+
+ifdef CONFIG_SPL_BUILD
+obj-y	+= mux.o
+endif
+
+obj-y	+= board.o

board/phytec/phycore_am335x_r2/board.c

@@ -0,0 +1,260 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * board.c
+ *
+ * Board functions for Phytec phyCORE-AM335x R2 (PCL060 / PCM060) based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
+ * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH
+ * Copyright (C) 2019 DENX Software Engineering GmbH
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <power/tps65910.h>
+#include <jffs2/load_kernel.h>
+#include <mtd_node.h>
+#include <fdt_support.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_SPL_BUILD
+
+static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+/* DDR RAM defines */
+#define DDR_CLK_MHZ		400 /* DDR_DPLL_MULT value */
+
+#define OSC	(V_OSCK / 1000000)
+const struct dpll_params dpll_ddr = {
+		DDR_CLK_MHZ, OSC - 1, 1, -1, -1, -1, -1};
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr;
+}
+
+const struct ctrl_ioregs ioregs = {
+	.cm0ioctl		= 0x18B,
+	.cm1ioctl		= 0x18B,
+	.cm2ioctl		= 0x18B,
+	.dt0ioctl		= 0x18B,
+	.dt1ioctl		= 0x18B,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = 0x80,
+	.cmd0iclkout = 0x0,
+
+	.cmd1csratio = 0x80,
+	.cmd1iclkout = 0x0,
+
+	.cmd2csratio = 0x80,
+	.cmd2iclkout = 0x0,
+};
+
+enum {
+	PHYCORE_R2_MT41K128M16JT_256MB,
+	PHYCORE_R2_MT41K256M16TW107IT_512MB,
+	PHYCORE_R2_MT41K512M16HA125IT_1024MB,
+};
+
+struct am335x_sdram_timings {
+	struct emif_regs ddr3_emif_reg_data;
+	struct ddr_data ddr3_data;
+};
+
+static struct am335x_sdram_timings physom_timings[] = {
+	[PHYCORE_R2_MT41K128M16JT_256MB] = {
+		.ddr3_emif_reg_data = {
+			.sdram_config = 0x61C052B2,
+			.ref_ctrl = 0x00000C30,
+			.sdram_tim1 = 0x0AAAD4DB,
+			.sdram_tim2 = 0x26437FDA,
+			.sdram_tim3 = 0x501F83FF,
+			.zq_config = 0x50074BE4,
+			.emif_ddr_phy_ctlr_1 = 0x7,
+			.ocp_config = 0x003d3d3d,
+		},
+		.ddr3_data = {
+			.datardsratio0 = 0x36,
+			.datawdsratio0 = 0x38,
+			.datafwsratio0 = 0x99,
+			.datawrsratio0 = 0x73,
+		},
+	},
+	[PHYCORE_R2_MT41K256M16TW107IT_512MB] = {
+		.ddr3_emif_reg_data = {
+			.sdram_config = 0x61C05332,
+			.ref_ctrl = 0x00000C30,
+			.sdram_tim1 = 0x0AAAD4DB,
+			.sdram_tim2 = 0x266B7FDA,
+			.sdram_tim3 = 0x501F867F,
+			.zq_config = 0x50074BE4,
+			.emif_ddr_phy_ctlr_1 = 0x7,
+			.ocp_config = 0x003d3d3d,
+		},
+		.ddr3_data = {
+			.datardsratio0 = 0x37,
+			.datawdsratio0 = 0x38,
+			.datafwsratio0 = 0x92,
+			.datawrsratio0 = 0x72,
+		},
+	},
+	[PHYCORE_R2_MT41K512M16HA125IT_1024MB] = {
+		.ddr3_emif_reg_data = {
+			.sdram_config = 0x61C053B2,
+			.ref_ctrl = 0x00000C30,
+			.sdram_tim1 = 0x0AAAD4DB,
+			.sdram_tim2 = 0x268F7FDA,
+			.sdram_tim3 = 0x501F88BF,
+			.zq_config = 0x50074BE4,
+			.emif_ddr_phy_ctlr_1 = 0x7,
+			.ocp_config = 0x003d3d3d,
+		},
+		.ddr3_data = {
+			.datardsratio0 = 0x38,
+			.datawdsratio0 = 0x4d,
+			.datafwsratio0 = 0x9d,
+			.datawrsratio0 = 0x82,
+		},
+	},
+};
+
+void sdram_init(void)
+{
+	/* Configure memory to maximum supported size for detection */
+	int ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
+
+	config_ddr(DDR_CLK_MHZ, &ioregs,
+		   &physom_timings[ram_type_index].ddr3_data,
+		   &ddr3_cmd_ctrl_data,
+		   &physom_timings[ram_type_index].ddr3_emif_reg_data,
+		   0);
+
+	/* Detect memory physically present */
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_MAX_RAM_BANK_SIZE);
+
+	/* Reconfigure memory for actual detected size */
+	switch (gd->ram_size) {
+	case SZ_1G:
+		ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
+		break;
+	case SZ_512M:
+		ram_type_index = PHYCORE_R2_MT41K256M16TW107IT_512MB;
+		break;
+	case SZ_256M:
+	default:
+		ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
+		break;
+	}
+	config_ddr(DDR_CLK_MHZ, &ioregs,
+		   &physom_timings[ram_type_index].ddr3_data,
+		   &ddr3_cmd_ctrl_data,
+		   &physom_timings[ram_type_index].ddr3_emif_reg_data,
+		   0);
+}
+
+const struct dpll_params *get_dpll_mpu_params(void)
+{
+	int ind = get_sys_clk_index();
+	int freq = am335x_get_efuse_mpu_max_freq(cdev);
+
+	switch (freq) {
+	case MPUPLL_M_1000:
+		return &dpll_mpu_opp[ind][5];
+	case MPUPLL_M_800:
+		return &dpll_mpu_opp[ind][4];
+	case MPUPLL_M_720:
+		return &dpll_mpu_opp[ind][3];
+	case MPUPLL_M_600:
+		return &dpll_mpu_opp[ind][2];
+	case MPUPLL_M_500:
+		return &dpll_mpu_opp100;
+	case MPUPLL_M_300:
+		return &dpll_mpu_opp[ind][0];
+	}
+
+	return &dpll_mpu_opp[ind][0];
+}
+
+static void scale_vcores_generic(int freq)
+{
+	int sil_rev, mpu_vdd;
+
+	/*
+	 * We use a TPS65910 PMIC. For all  MPU frequencies we support we use a
+	 * CORE voltage of 1.10V. For MPU voltage we need to switch based on
+	 * the frequency we are running at.
+	 */
+	if (power_tps65910_init(0))
+		return;
+
+	/*
+	 * Depending on MPU clock and PG we will need a different
+	 * VDD to drive at that speed.
+	 */
+	sil_rev = readl(&cdev->deviceid) >> 28;
+	mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
+
+	/* Tell the TPS65910 to use i2c */
+	tps65910_set_i2c_control();
+
+	/* First update MPU voltage. */
+	if (tps65910_voltage_update(MPU, mpu_vdd))
+		return;
+
+	/* Second, update the CORE voltage. */
+	if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
+		return;
+}
+
+void scale_vcores(void)
+{
+	int freq;
+
+	freq = am335x_get_efuse_mpu_max_freq(cdev);
+	scale_vcores_generic(freq);
+}
+
+void set_uart_mux_conf(void)
+{
+	enable_uart0_pin_mux();
+}
+
+void set_mux_conf_regs(void)
+{
+	enable_i2c0_pin_mux();
+	enable_board_pin_mux();
+}
+#endif
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+	static const struct node_info nodes[] = {
+		{ "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
+	};
+
+	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+#endif
+	return 0;
+}
+#endif

board/phytec/phycore_am335x_r2/board.h

@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * board.h
+ *
+ * Phytec phyCORE-AM335x (PCL060 / PCM060) boards information header
+ *
+ * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
+ * Copyright (C) 2019 DENX Software Engineering GmbH
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * We have three pin mux functions that must exist.  We must be able to enable
+ * uart0, for initial output and i2c0 to access the PMIC. We then have a main
+ * pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void enable_i2c0_pin_mux(void);
+void enable_board_pin_mux(void);
+void enable_cbmux_pin_mux(void);
+#endif

board/phytec/phycore_am335x_r2/mux.c

@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * mux.c
+ *
+ * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
+ * Copyright (C) 2019 DENX Software Engineering GmbH
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include "board.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},		/* UART0_TXD */
+	{-1},
+};
+
+#ifdef CONFIG_MMC
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
+	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},	/* MMC0_CD */
+	{-1},
+};
+#endif
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
+			PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
+	{-1},
+};
+
+#ifdef CONFIG_SPI
+static struct module_pin_mux spi0_pin_mux[] = {
+	{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)},	/* SPI0_SCLK */
+	{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
+			PULLUDEN | PULLUP_EN)},			/* SPI0_D0 */
+	{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)},	/* SPI0_D1 */
+	{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
+			PULLUDEN | PULLUP_EN)},			/* SPI0_CS0 */
+	{-1},
+};
+#endif
+
+static struct module_pin_mux rmii1_pin_mux[] = {
+	{OFFSET(mii1_crs), MODE(1) | RXACTIVE},     /* RMII1_CRS */
+	{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE},   /* RMII1_RXERR */
+	{OFFSET(mii1_txen), MODE(1)},               /* RMII1_TXEN */
+	{OFFSET(mii1_txd1), MODE(1)},               /* RMII1_TXD1 */
+	{OFFSET(mii1_txd0), MODE(1)},               /* RMII1_TXD0 */
+	{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE},    /* RMII1_RXD1 */
+	{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE},    /* RMII1_RXD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},    /* MDIO_CLK */
+	{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
+	{-1},
+};
+
+static struct module_pin_mux cbmux_pin_mux[] = {
+	{OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLDOWN_EN}, /* JP3 */
+	{OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUP_EN},	/* JP4 */
+	{-1},
+};
+
+#ifdef CONFIG_NAND
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{-1},
+};
+#endif
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_i2c0_pin_mux(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+}
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(rmii1_pin_mux);
+	configure_module_pin_mux(mmc0_pin_mux);
+	configure_module_pin_mux(cbmux_pin_mux);
+#ifdef CONFIG_NAND
+	configure_module_pin_mux(nand_pin_mux);
+#endif
+#ifdef CONFIG_SPI
+	configure_module_pin_mux(spi0_pin_mux);
+#endif
+}

board/ronetix/pm9261/pm9261.c

@@ -17,9 +17,6 @@
 #include <asm/arch/at91_matrix.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
-
-#include <lcd.h>
-#include <atmel_lcdc.h>
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
 #include <net.h>
 #endif
@@ -110,105 +107,6 @@ static void pm9261_dm9000_hw_init(void)
 }
 #endif
 
-#ifdef CONFIG_LCD
-vidinfo_t panel_info = {
-	.vl_col =		240,
-	.vl_row =		320,
-	.vl_clk =		4965000,
-	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
-				ATMEL_LCDC_INVFRAME_INVERTED,
-	.vl_bpix =		3,
-	.vl_tft =		1,
-	.vl_hsync_len =		5,
-	.vl_left_margin =	1,
-	.vl_right_margin =	33,
-	.vl_vsync_len =		1,
-	.vl_upper_margin =	1,
-	.vl_lower_margin =	0,
-	.mmio =			ATMEL_BASE_LCDC,
-};
-
-void lcd_enable(void)
-{
-	at91_set_pio_value(AT91_PIO_PORTA, 22, 0);  /* power up */
-}
-
-void lcd_disable(void)
-{
-	at91_set_pio_value(AT91_PIO_PORTA, 22, 1);  /* power down */
-}
-
-static void pm9261_lcd_hw_init(void)
-{
-	at91_set_a_periph(AT91_PIO_PORTB, 1, 0);	/* LCDHSYNC */
-	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* LCDDOTCK */
-	at91_set_a_periph(AT91_PIO_PORTB, 3, 0);	/* LCDDEN */
-	at91_set_a_periph(AT91_PIO_PORTB, 4, 0);	/* LCDCC */
-	at91_set_a_periph(AT91_PIO_PORTB, 7, 0);	/* LCDD2 */
-	at91_set_a_periph(AT91_PIO_PORTB, 8, 0);	/* LCDD3 */
-	at91_set_a_periph(AT91_PIO_PORTB, 9, 0);	/* LCDD4 */
-	at91_set_a_periph(AT91_PIO_PORTB, 10, 0);	/* LCDD5 */
-	at91_set_a_periph(AT91_PIO_PORTB, 11, 0);	/* LCDD6 */
-	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* LCDD7 */
-	at91_set_a_periph(AT91_PIO_PORTB, 15, 0);	/* LCDD10 */
-	at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* LCDD11 */
-	at91_set_a_periph(AT91_PIO_PORTB, 17, 0);	/* LCDD12 */
-	at91_set_a_periph(AT91_PIO_PORTB, 18, 0);	/* LCDD13 */
-	at91_set_a_periph(AT91_PIO_PORTB, 19, 0);	/* LCDD14 */
-	at91_set_a_periph(AT91_PIO_PORTB, 20, 0);	/* LCDD15 */
-	at91_set_b_periph(AT91_PIO_PORTB, 23, 0);	/* LCDD18 */
-	at91_set_b_periph(AT91_PIO_PORTB, 24, 0);	/* LCDD19 */
-	at91_set_b_periph(AT91_PIO_PORTB, 25, 0);	/* LCDD20 */
-	at91_set_b_periph(AT91_PIO_PORTB, 26, 0);	/* LCDD21 */
-	at91_set_b_periph(AT91_PIO_PORTB, 27, 0);	/* LCDD22 */
-	at91_set_b_periph(AT91_PIO_PORTB, 28, 0);	/* LCDD23 */
-
-	at91_system_clk_enable(AT91_PMC_HCK1);
-
-	gd->fb_base = ATMEL_BASE_SRAM;
-}
-
-#ifdef CONFIG_LCD_INFO
-#include <nand.h>
-#include <version.h>
-
-extern flash_info_t flash_info[];
-
-void lcd_show_board_info(void)
-{
-	ulong dram_size, nand_size, flash_size;
-	int i;
-	char temp[32];
-
-	lcd_printf ("%s\n", U_BOOT_VERSION);
-	lcd_printf ("(C) 2009 Ronetix GmbH\n");
-	lcd_printf ("support@ronetix.at\n");
-	lcd_printf ("%s CPU at %s MHz",
-		CONFIG_SYS_AT91_CPU_NAME,
-		strmhz(temp, get_cpu_clk_rate()));
-
-	dram_size = 0;
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
-		dram_size += gd->bd->bi_dram[i].size;
-
-	nand_size = 0;
-	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += get_nand_dev_by_index(i)->size;
-
-	flash_size = 0;
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
-		flash_size += flash_info[i].size;
-
-	lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
-			"%ld MB DataFlash\n",
-		dram_size >> 20,
-		nand_size >> 20,
-		flash_size >> 20);
-}
-#endif /* CONFIG_LCD_INFO */
-
-#endif /* CONFIG_LCD */
-
 int board_early_init_f(void)
 {
 	return 0;
@@ -227,9 +125,6 @@ int board_init(void)
 #endif
 #ifdef CONFIG_DRIVER_DM9000
 	pm9261_dm9000_hw_init();
-#endif
-#ifdef CONFIG_LCD
-	pm9261_lcd_hw_init();
 #endif
 	return 0;
 }

board/ronetix/pm9263/pm9263.c

@@ -17,8 +17,6 @@
 #include <asm/arch/at91_matrix.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
-#include <lcd.h>
-#include <atmel_lcdc.h>
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
 #include <net.h>
 #endif
@@ -109,32 +107,6 @@ static void pm9263_macb_hw_init(void)
 #endif
 
 #ifdef CONFIG_LCD
-vidinfo_t panel_info = {
-	.vl_col =		240,
-	.vl_row =		320,
-	.vl_clk =		4965000,
-	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
-					ATMEL_LCDC_INVFRAME_INVERTED,
-	.vl_bpix =		3,
-	.vl_tft =		1,
-	.vl_hsync_len =		5,
-	.vl_left_margin =	1,
-	.vl_right_margin =	33,
-	.vl_vsync_len =		1,
-	.vl_upper_margin =	1,
-	.vl_lower_margin =	0,
-	.mmio =			ATMEL_BASE_LCDC,
-};
-
-void lcd_enable(void)
-{
-	at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */
-}
-
-void lcd_disable(void)
-{
-	at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
-}
 
 #ifdef CONFIG_LCD_IN_PSRAM
 
@@ -226,32 +198,6 @@ static int pm9263_lcd_hw_psram_init(void)
 
 static void pm9263_lcd_hw_init(void)
 {
-	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* LCDVSYNC */
-	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* LCDHSYNC */
-	at91_set_a_periph(AT91_PIO_PORTC, 2, 0);	/* LCDDOTCK */
-	at91_set_a_periph(AT91_PIO_PORTC, 3, 0);	/* LCDDEN */
-	at91_set_b_periph(AT91_PIO_PORTB, 9, 0);	/* LCDCC */
-	at91_set_a_periph(AT91_PIO_PORTC, 6, 0);	/* LCDD2 */
-	at91_set_a_periph(AT91_PIO_PORTC, 7, 0);	/* LCDD3 */
-	at91_set_a_periph(AT91_PIO_PORTC, 8, 0);	/* LCDD4 */
-	at91_set_a_periph(AT91_PIO_PORTC, 9, 0);	/* LCDD5 */
-	at91_set_a_periph(AT91_PIO_PORTC, 10, 0);	/* LCDD6 */
-	at91_set_a_periph(AT91_PIO_PORTC, 11, 0);	/* LCDD7 */
-	at91_set_a_periph(AT91_PIO_PORTC, 14, 0);	/* LCDD10 */
-	at91_set_a_periph(AT91_PIO_PORTC, 15, 0);	/* LCDD11 */
-	at91_set_a_periph(AT91_PIO_PORTC, 16, 0);	/* LCDD12 */
-	at91_set_b_periph(AT91_PIO_PORTC, 12, 0);	/* LCDD13 */
-	at91_set_a_periph(AT91_PIO_PORTC, 18, 0);	/* LCDD14 */
-	at91_set_a_periph(AT91_PIO_PORTC, 19, 0);	/* LCDD15 */
-	at91_set_a_periph(AT91_PIO_PORTC, 22, 0);	/* LCDD18 */
-	at91_set_a_periph(AT91_PIO_PORTC, 23, 0);	/* LCDD19 */
-	at91_set_a_periph(AT91_PIO_PORTC, 24, 0);	/* LCDD20 */
-	at91_set_b_periph(AT91_PIO_PORTC, 17, 0);	/* LCDD21 */
-	at91_set_a_periph(AT91_PIO_PORTC, 26, 0);	/* LCDD22 */
-	at91_set_a_periph(AT91_PIO_PORTC, 27, 0);	/* LCDD23 */
-
-	at91_periph_clk_enable(ATMEL_ID_LCDC);
-
 	/* Power Control */
 	at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
 	at91_set_pio_value(AT91_PIO_PORTA, 22, 0);	/* power down */
@@ -267,45 +213,6 @@ static void pm9263_lcd_hw_init(void)
 
 }
 
-#ifdef CONFIG_LCD_INFO
-#include <nand.h>
-#include <version.h>
-
-extern flash_info_t flash_info[];
-
-void lcd_show_board_info(void)
-{
-	ulong dram_size, nand_size, flash_size;
-	int i;
-	char temp[32];
-
-	lcd_printf ("%s\n", U_BOOT_VERSION);
-	lcd_printf ("(C) 2009 Ronetix GmbH\n");
-	lcd_printf ("support@ronetix.at\n");
-	lcd_printf ("%s CPU at %s MHz",
-		CONFIG_SYS_AT91_CPU_NAME,
-		strmhz(temp, get_cpu_clk_rate()));
-
-	dram_size = 0;
-	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
-		dram_size += gd->bd->bi_dram[i].size;
-
-	nand_size = 0;
-	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-		nand_size += get_nand_dev_by_index(i)->size;
-
-	flash_size = 0;
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
-		flash_size += flash_info[i].size;
-
-	lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
-			"4 MB PSRAM\n",
-		dram_size >> 20,
-		nand_size >> 20,
-		flash_size >> 20);
-}
-#endif /* CONFIG_LCD_INFO */
-
 #endif /* CONFIG_LCD */
 
 int board_early_init_f(void)

board/ti/evm/evm.c

@@ -30,11 +30,6 @@
 #include <linux/usb/musb.h>
 #include "evm.h"
 
-#ifdef CONFIG_USB_EHCI_HCD
-#include <usb.h>
-#include <asm/ehci-omap.h>
-#endif
-
 #define OMAP3EVM_GPIO_ETH_RST_GEN1 64
 #define OMAP3EVM_GPIO_ETH_RST_GEN2 7
 
@@ -307,32 +302,6 @@ void board_mmc_power_init(void)
 }
 #endif /* CONFIG_MMC */
 
-#if defined(CONFIG_USB_EHCI_HCD) && !defined(CONFIG_SPL_BUILD)
-/* Call usb_stop() before starting the kernel */
-void show_boot_progress(int val)
-{
-	if (val == BOOTSTAGE_ID_RUN_OS)
-		usb_stop();
-}
-
-static struct omap_usbhs_board_data usbhs_bdata = {
-	.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
-	.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
-};
-
-int ehci_hcd_init(int index, enum usb_init_type init,
-		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
-{
-	return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
-}
-
-int ehci_hcd_stop(int index)
-{
-	return omap_ehci_hcd_stop();
-}
-#endif /* CONFIG_USB_EHCI_HCD */
-
 #if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET) && !defined(CONFIG_CMD_NET)
 int board_eth_init(bd_t *bis)
 {

cmd/Kconfig

@@ -441,6 +441,19 @@ config CMD_NVEDIT_EFI
 	  If enabled, we are allowed to set/print UEFI variables using
 	  "env" command with "-e" option without knowing details.
 
+config CMD_NVEDIT_INFO
+	bool "env info - print or evaluate environment information"
+	help
+	  Print environment information:
+	  - env_valid : is environment valid
+	  - env_ready : is environment imported into hash table
+	  - env_use_default : is default environment used
+
+	  This command can be optionally used for evaluation in scripts:
+	  [-d] : evaluate whether default environment is used
+	  [-p] : evaluate whether environment can be persisted
+	  The result of multiple evaluations will be combined with AND.
+
 endmenu
 
 menu "Memory commands"

cmd/nvedit.c

@@ -1163,6 +1163,106 @@ sep_err:
 }
 #endif
 
+#if defined(CONFIG_CMD_NVEDIT_INFO)
+/*
+ * print_env_info - print environment information
+ */
+static int print_env_info(void)
+{
+	const char *value;
+
+	/* print environment validity value */
+	switch (gd->env_valid) {
+	case ENV_INVALID:
+		value = "invalid";
+		break;
+	case ENV_VALID:
+		value = "valid";
+		break;
+	case ENV_REDUND:
+		value = "redundant";
+		break;
+	default:
+		value = "unknown";
+		break;
+	}
+	printf("env_valid = %s\n", value);
+
+	/* print environment ready flag */
+	value = gd->flags & GD_FLG_ENV_READY ? "true" : "false";
+	printf("env_ready = %s\n", value);
+
+	/* print environment using default flag */
+	value = gd->flags & GD_FLG_ENV_DEFAULT ? "true" : "false";
+	printf("env_use_default = %s\n", value);
+
+	return CMD_RET_SUCCESS;
+}
+
+#define ENV_INFO_IS_DEFAULT	BIT(0) /* default environment bit mask */
+#define ENV_INFO_IS_PERSISTED	BIT(1) /* environment persistence bit mask */
+
+/*
+ * env info - display environment information
+ * env info [-d] - evaluate whether default environment is used
+ * env info [-p] - evaluate whether environment can be persisted
+ */
+static int do_env_info(cmd_tbl_t *cmdtp, int flag,
+		       int argc, char * const argv[])
+{
+	int eval_flags = 0;
+	int eval_results = 0;
+
+	/* display environment information */
+	if (argc <= 1)
+		return print_env_info();
+
+	/* process options */
+	while (--argc > 0 && **++argv == '-') {
+		char *arg = *argv;
+
+		while (*++arg) {
+			switch (*arg) {
+			case 'd':
+				eval_flags |= ENV_INFO_IS_DEFAULT;
+				break;
+			case 'p':
+				eval_flags |= ENV_INFO_IS_PERSISTED;
+				break;
+			default:
+				return CMD_RET_USAGE;
+			}
+		}
+	}
+
+	/* evaluate whether default environment is used */
+	if (eval_flags & ENV_INFO_IS_DEFAULT) {
+		if (gd->flags & GD_FLG_ENV_DEFAULT) {
+			printf("Default environment is used\n");
+			eval_results |= ENV_INFO_IS_DEFAULT;
+		} else {
+			printf("Environment was loaded from persistent storage\n");
+		}
+	}
+
+	/* evaluate whether environment can be persisted */
+	if (eval_flags & ENV_INFO_IS_PERSISTED) {
+#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
+		printf("Environment can be persisted\n");
+		eval_results |= ENV_INFO_IS_PERSISTED;
+#else
+		printf("Environment cannot be persisted\n");
+#endif
+	}
+
+	/* The result of evaluations is combined with AND */
+	if (eval_flags != eval_results)
+		return CMD_RET_FAILURE;
+
+	return CMD_RET_SUCCESS;
+}
+#endif
+
 #if defined(CONFIG_CMD_ENV_EXISTS)
 static int do_env_exists(cmd_tbl_t *cmdtp, int flag, int argc,
 		       char * const argv[])
@@ -1206,6 +1306,9 @@ static cmd_tbl_t cmd_env_sub[] = {
 #endif
 #if defined(CONFIG_CMD_IMPORTENV)
 	U_BOOT_CMD_MKENT(import, 5, 0, do_env_import, "", ""),
+#endif
+#if defined(CONFIG_CMD_NVEDIT_INFO)
+	U_BOOT_CMD_MKENT(info, 2, 0, do_env_info, "", ""),
 #endif
 	U_BOOT_CMD_MKENT(print, CONFIG_SYS_MAXARGS, 1, do_env_print, "", ""),
 #if defined(CONFIG_CMD_RUN)
@@ -1278,6 +1381,11 @@ static char env_help_text[] =
 #endif
 #if defined(CONFIG_CMD_IMPORTENV)
 	"env import [-d] [-t [-r] | -b | -c] addr [size] [var ...] - import environment\n"
+#endif
+#if defined(CONFIG_CMD_NVEDIT_INFO)
+	"env info - display environment information\n"
+	"env info [-d] - whether default environment is used\n"
+	"env info [-p] - whether environment can be persisted\n"
 #endif
 	"env print [-a | name ...] - print environment\n"
 #if defined(CONFIG_CMD_NVEDIT_EFI)

common/board_r.c

@@ -49,6 +49,9 @@
 #include <linux/err.h>
 #include <efi_loader.h>
 #include <wdt.h>
+#if defined(CONFIG_DM_GPIO_HOG)
+#include <asm/gpio.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -796,6 +799,9 @@ static init_fnc_t init_sequence_r[] = {
 #ifdef CONFIG_CMD_NET
 	initr_ethaddr,
 #endif
+#if defined(CONFIG_DM_GPIO_HOG)
+	gpio_hog_probe_all,
+#endif
 #ifdef CONFIG_BOARD_LATE_INIT
 	board_late_init,
 #endif

common/spl/Kconfig

@@ -572,6 +572,23 @@ config SPL_MMC_SUPPORT
 	  this option to build the drivers in drivers/mmc as part of an SPL
 	  build.
 
+config SPL_MMC_TINY
+	bool "Tiny MMC framework in SPL"
+	depends on SPL_MMC_SUPPORT
+	default n
+	help
+	  Enable MMC framework tinification support. This option is useful if
+	  if your SPL is extremely size constrained. Heed the warning, enable
+	  this option if and only if you know exactly what you are doing, if
+	  you are reading this help text, you most likely have no idea :-)
+
+	  The MMC framework is reduced to bare minimum to be useful. No malloc
+	  support is needed for the MMC framework operation with this option
+	  enabled. The framework supports exactly one MMC device and exactly
+	  one MMC driver. The MMC driver can be adjusted to avoid any malloc
+	  operations too, which can remove the need for malloc support in SPL
+	  and thus further reduce footprint.
+
 config SPL_MMC_WRITE
 	bool "MMC/SD/SDIO card support for write operations in SPL"
 	depends on SPL_MMC_SUPPORT

configs/legoev3_defconfig

@@ -23,12 +23,19 @@ CONFIG_CMD_SPI=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_DIAG=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="da850-lego-ev3"
+CONFIG_DM=y
+# CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_SYS_I2C_DAVINCI=y
+CONFIG_DM_MMC=y
+CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=50000000
 CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
+CONFIG_DM_SPI=y
 CONFIG_DAVINCI_SPI=y
-CONFIG_OF_LIBFDT=y
 # CONFIG_EFI_LOADER is not set

configs/ls1043ardb_nand_SECURE_BOOT_defconfig

@@ -67,6 +67,7 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
+# CONFIG_USE_TINY_PRINTF is not set
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

configs/ls1043ardb_nand_defconfig

@@ -67,4 +67,5 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
+# CONFIG_USE_TINY_PRINTF is not set
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig

@@ -65,6 +65,7 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
+# CONFIG_USE_TINY_PRINTF is not set
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

configs/ls1043ardb_sdcard_defconfig

@@ -65,4 +65,5 @@ CONFIG_USB=y
 CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
+# CONFIG_USE_TINY_PRINTF is not set
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y

configs/omap3_evm_defconfig

@@ -66,7 +66,10 @@ CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_OMAP3_SPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
+# CONFIG_SPL_DM_USB is not set
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OMAP3=y
 CONFIG_USB_MUSB_GADGET=y
 CONFIG_USB_MUSB_OMAP2PLUS=y
 CONFIG_USB_GADGET=y

configs/phycore-am335x-r2-wega_defconfig

@@ -0,0 +1,82 @@
+CONFIG_ARM=y
+CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_AM33XX=y
+CONFIG_SYS_MPUCLK=1000
+CONFIG_TARGET_PHYCORE_AM335X_R2=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+# CONFIG_FIT is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DEFAULT_FDT_FILE="am335x-wega-rdk.dtb"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_PAYLOAD="u-boot.img"
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_SPL=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),512k(NAND.u-boot),512k(NAND.u-boot.backup1),256k(NAND.u-boot-env),-(NAND.UBI)"
+CONFIG_CMD_UBI=y
+CONFIG_DOS_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="am335x-wega-rdk"
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_IS_IN_NAND=y
+CONFIG_ENV_OFFSET=0x000a0000
+CONFIG_ENV_FAT_INTERFACE="mmc"
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DM_I2C=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_OMAP_HS=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
+CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x100000
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_ETH=y
+CONFIG_MII=y
+CONFIG_DRIVER_TI_CPSW=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_OMAP3_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_MUSB_TI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_ETHER=y
+# CONFIG_OMAP_WATCHDOG is not set
+CONFIG_FDT_FIXUP_PARTITIONS=y
+# CONFIG_EFI_LOADER is not set

configs/pm9261_defconfig

@@ -33,6 +33,7 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM=y
+CONFIG_BLK=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
 CONFIG_DM_GPIO=y
@@ -54,5 +55,7 @@ CONFIG_ATMEL_USART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_LCD=y
+CONFIG_DM_VIDEO=y

configs/pm9263_defconfig

@@ -33,6 +33,7 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM=y
+CONFIG_BLK=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
 CONFIG_DM_GPIO=y
@@ -52,5 +53,7 @@ CONFIG_ATMEL_USART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y
+CONFIG_DM_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_LCD=y
+CONFIG_DM_VIDEO=y

configs/sandbox64_defconfig

@@ -163,6 +163,7 @@ CONFIG_REMOTEPROC_SANDBOX=y
 CONFIG_DM_RESET=y
 CONFIG_SANDBOX_RESET=y
 CONFIG_DM_RTC=y
+CONFIG_RTC_RV8803=y
 CONFIG_SANDBOX_SERIAL=y
 CONFIG_SMEM=y
 CONFIG_SANDBOX_SMEM=y

configs/sandbox_defconfig

@@ -179,6 +179,7 @@ CONFIG_REMOTEPROC_SANDBOX=y
 CONFIG_DM_RESET=y
 CONFIG_SANDBOX_RESET=y
 CONFIG_DM_RTC=y
+CONFIG_RTC_RV8803=y
 CONFIG_DEBUG_UART_SANDBOX=y
 CONFIG_SANDBOX_SERIAL=y
 CONFIG_SMEM=y

configs/sandbox_spl_defconfig

@@ -191,6 +191,7 @@ CONFIG_OSD=y
 CONFIG_SANDBOX_OSD=y
 CONFIG_FS_CBFS=y
 CONFIG_FS_CRAMFS=y
+# CONFIG_USE_TINY_PRINTF is not set
 CONFIG_CMD_DHRYSTONE=y
 CONFIG_TPM=y
 CONFIG_LZ4=y

doc/device-tree-bindings/gpio/gpio.txt

@@ -210,3 +210,58 @@ Example 2:
 Here, three GPIO ranges are defined wrt. two pin controllers. pinctrl1 GPIO
 ranges are defined using pin numbers whereas the GPIO ranges wrt. pinctrl2
 are named "foo" and "bar".
+
+3) GPIO hog definitions
+-----------------------
+
+The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism
+providing automatic GPIO request and configuration as part of the
+gpio-controller's driver probe function.
+
+Each GPIO hog definition is represented as a child node of the GPIO controller.
+Required properties:
+- gpio-hog:   A property specifying that this child node represents a GPIO hog.
+- gpios:      Store the GPIO information (id, flags) for the GPIO to
+	      affect.
+
+              ! Not yet support more than one gpio !
+
+Only one of the following properties scanned in the order shown below.
+- input:      A property specifying to set the GPIO direction as input.
+- output-low  A property specifying to set the GPIO direction as output with
+	      the value low.
+- output-high A property specifying to set the GPIO direction as output with
+	      the value high.
+
+Optional properties:
+- line-name:  The GPIO label name. If not present the node name is used.
+
+Example:
+
+        tca6416@20 {
+                compatible = "ti,tca6416";
+                reg = <0x20>;
+                #gpio-cells = <2>;
+                gpio-controller;
+
+                env_reset {
+                        gpio-hog;
+                        input;
+                        gpios = <6 GPIO_ACTIVE_LOW>;
+                };
+                boot_rescue {
+                        gpio-hog;
+                        input;
+                        gpios = <7 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+For the above Example you can than access the gpio in your boardcode
+with:
+
+        desc = gpio_hog_lookup_name("boot_rescue.gpio-hog");
+        if (desc) {
+                if (dm_gpio_get_value(desc))
+                        printf("\nBooting into Rescue System\n");
+		else
+			printf("\nBoot normal\n");

drivers/core/uclass.c

@@ -260,7 +260,7 @@ int uclass_find_device_by_name(enum uclass_id id, const char *name,
 		return ret;
 
 	uclass_foreach_dev(dev, uc) {
-		if (!strncmp(dev->name, name, strlen(name))) {
+		if (!strcmp(dev->name, name)) {
 			*devp = dev;
 			return 0;
 		}

drivers/gpio/Kconfig

@@ -14,6 +14,16 @@ config DM_GPIO
 	  particular GPIOs that they provide. The uclass interface
 	  is defined in include/asm-generic/gpio.h.
 
+config DM_GPIO_HOG
+	bool "Enable GPIO hog support"
+	depends on DM_GPIO
+	default n
+	help
+	  Enable gpio hog support
+	  The GPIO chip may contain GPIO hog definitions. GPIO hogging
+	  is a mechanism providing automatic GPIO request and config-
+	  uration as part of the gpio-controller's driver probe function.
+
 config ALTERA_PIO
 	bool "Altera PIO driver"
 	depends on DM_GPIO

drivers/gpio/gpio-uclass.c

@@ -5,6 +5,9 @@
 
 #include <common.h>
 #include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dm/uclass-internal.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <errno.h>
 #include <fdtdec.h>
@@ -141,6 +144,118 @@ static int gpio_find_and_xlate(struct gpio_desc *desc,
 		return gpio_xlate_offs_flags(desc->dev, desc, args);
 }
 
+#if defined(CONFIG_DM_GPIO_HOG)
+
+struct gpio_hog_priv {
+	struct gpio_desc gpiod;
+};
+
+struct gpio_hog_data {
+	int gpiod_flags;
+	int value;
+	u32 val[2];
+};
+
+static int gpio_hog_ofdata_to_platdata(struct udevice *dev)
+{
+	struct gpio_hog_data *plat = dev_get_platdata(dev);
+	const char *nodename;
+	int ret;
+
+	plat->value = 0;
+	if (dev_read_bool(dev, "input")) {
+		plat->gpiod_flags = GPIOD_IS_IN;
+	} else if (dev_read_bool(dev, "output-high")) {
+		plat->value = 1;
+		plat->gpiod_flags = GPIOD_IS_OUT;
+	} else if (dev_read_bool(dev, "output-low")) {
+		plat->gpiod_flags = GPIOD_IS_OUT;
+	} else {
+		printf("%s: missing gpio-hog state.\n", __func__);
+		return -EINVAL;
+	}
+	ret = dev_read_u32_array(dev, "gpios", plat->val, 2);
+	if (ret) {
+		printf("%s: wrong gpios property, 2 values needed %d\n",
+		       __func__, ret);
+		return ret;
+	}
+	nodename = dev_read_string(dev, "line-name");
+	if (!nodename)
+		nodename = dev_read_name(dev);
+	device_set_name(dev, nodename);
+
+	return 0;
+}
+
+static int gpio_hog_probe(struct udevice *dev)
+{
+	struct gpio_hog_data *plat = dev_get_platdata(dev);
+	struct gpio_hog_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = gpio_dev_request_index(dev->parent, dev->name, "gpio-hog",
+				     plat->val[0], plat->gpiod_flags,
+				     plat->val[1], &priv->gpiod);
+	if (ret < 0) {
+		debug("%s: node %s could not get gpio.\n", __func__,
+		      dev->name);
+		return ret;
+	}
+	dm_gpio_set_dir(&priv->gpiod);
+	if (plat->gpiod_flags == GPIOD_IS_OUT)
+		dm_gpio_set_value(&priv->gpiod, plat->value);
+
+	return 0;
+}
+
+int gpio_hog_probe_all(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	for (uclass_first_device(UCLASS_NOP, &dev);
+	     dev;
+	     uclass_find_next_device(&dev)) {
+		if (dev->driver == DM_GET_DRIVER(gpio_hog)) {
+			ret = device_probe(dev);
+			if (ret)
+				return ret;
+		}
+	}
+
+	return 0;
+}
+
+struct gpio_desc *gpio_hog_lookup_name(const char *name)
+{
+	struct udevice *dev;
+
+	gpio_hog_probe_all();
+	if (!uclass_get_device_by_name(UCLASS_NOP, name, &dev)) {
+		struct gpio_hog_priv *priv = dev_get_priv(dev);
+
+		return &priv->gpiod;
+	}
+
+	return NULL;
+}
+
+U_BOOT_DRIVER(gpio_hog) = {
+	.name	= "gpio_hog",
+	.id	= UCLASS_NOP,
+	.ofdata_to_platdata = gpio_hog_ofdata_to_platdata,
+	.probe = gpio_hog_probe,
+	.priv_auto_alloc_size = sizeof(struct gpio_hog_priv),
+	.platdata_auto_alloc_size = sizeof(struct gpio_hog_data),
+};
+#else
+struct gpio_desc *gpio_hog_lookup_name(const char *name)
+{
+	return NULL;
+}
+#endif
+
 int dm_gpio_request(struct gpio_desc *desc, const char *label)
 {
 	struct udevice *dev = desc->dev;
@@ -640,22 +755,25 @@ int dm_gpio_get_values_as_int(const struct gpio_desc *desc_list, int count)
 	return vector;
 }
 
-static int gpio_request_tail(int ret, ofnode node,
+static int gpio_request_tail(int ret, const char *nodename,
 			     struct ofnode_phandle_args *args,
 			     const char *list_name, int index,
-			     struct gpio_desc *desc, int flags, bool add_index)
+			     struct gpio_desc *desc, int flags,
+			     bool add_index, struct udevice *dev)
 {
-	desc->dev = NULL;
+	desc->dev = dev;
 	desc->offset = 0;
 	desc->flags = 0;
 	if (ret)
 		goto err;
 
-	ret = uclass_get_device_by_ofnode(UCLASS_GPIO, args->node,
+	if (!desc->dev) {
-					  &desc->dev);
+		ret = uclass_get_device_by_ofnode(UCLASS_GPIO, args->node,
-	if (ret) {
+						  &desc->dev);
-		debug("%s: uclass_get_device_by_ofnode failed\n", __func__);
+		if (ret) {
-		goto err;
+			debug("%s: uclass_get_device_by_ofnode failed\n", __func__);
+			goto err;
+		}
 	}
 	ret = gpio_find_and_xlate(desc, args);
 	if (ret) {
@@ -663,8 +781,7 @@ static int gpio_request_tail(int ret, ofnode node,
 		goto err;
 	}
 	ret = dm_gpio_requestf(desc, add_index ? "%s.%s%d" : "%s.%s",
-			       ofnode_get_name(node),
+			       nodename, list_name, index);
-			       list_name, index);
 	if (ret) {
 		debug("%s: dm_gpio_requestf failed\n", __func__);
 		goto err;
@@ -678,7 +795,7 @@ static int gpio_request_tail(int ret, ofnode node,
 	return 0;
 err:
 	debug("%s: Node '%s', property '%s', failed to request GPIO index %d: %d\n",
-	      __func__, ofnode_get_name(node), list_name, index, ret);
+	      __func__, nodename, list_name, index, ret);
 	return ret;
 }
 
@@ -692,8 +809,8 @@ static int _gpio_request_by_name_nodev(ofnode node, const char *list_name,
 	ret = ofnode_parse_phandle_with_args(node, list_name, "#gpio-cells", 0,
 					     index, &args);
 
-	return gpio_request_tail(ret, node, &args, list_name, index, desc,
+	return gpio_request_tail(ret, ofnode_get_name(node), &args, list_name,
-				 flags, add_index);
+				 index, desc, flags, add_index, NULL);
 }
 
 int gpio_request_by_name_nodev(ofnode node, const char *list_name, int index,
@@ -707,13 +824,14 @@ int gpio_request_by_name(struct udevice *dev, const char *list_name, int index,
 			 struct gpio_desc *desc, int flags)
 {
 	struct ofnode_phandle_args args;
+	ofnode node;
 	int ret;
 
 	ret = dev_read_phandle_with_args(dev, list_name, "#gpio-cells", 0,
 					 index, &args);
-
+	node = dev_ofnode(dev);
-	return gpio_request_tail(ret, dev_ofnode(dev), &args, list_name,
+	return gpio_request_tail(ret, ofnode_get_name(node), &args, list_name,
-				 index, desc, flags, index > 0);
+				 index, desc, flags, index > 0, NULL);
 }
 
 int gpio_request_list_by_name_nodev(ofnode node, const char *list_name,
@@ -854,8 +972,28 @@ static int gpio_pre_remove(struct udevice *dev)
 	return gpio_renumber(dev);
 }
 
+int gpio_dev_request_index(struct udevice *dev, const char *nodename,
+			   char *list_name, int index, int flags,
+			   int dtflags, struct gpio_desc *desc)
+{
+	struct ofnode_phandle_args args;
+
+	args.node =  ofnode_null();
+	args.args_count = 2;
+	args.args[0] = index;
+	args.args[1] = dtflags;
+
+	return gpio_request_tail(0, nodename, &args, list_name, index, desc,
+				 flags, 0, dev);
+}
+
 static int gpio_post_bind(struct udevice *dev)
 {
+#if defined(CONFIG_DM_GPIO_HOG)
+	struct udevice *child;
+	ofnode node;
+#endif
+
 #if defined(CONFIG_NEEDS_MANUAL_RELOC)
 	struct dm_gpio_ops *ops = (struct dm_gpio_ops *)device_get_ops(dev);
 	static int reloc_done;
@@ -885,6 +1023,17 @@ static int gpio_post_bind(struct udevice *dev)
 		reloc_done++;
 	}
 #endif
+
+#if defined(CONFIG_DM_GPIO_HOG)
+	dev_for_each_subnode(node, dev) {
+		if (ofnode_read_bool(node, "gpio-hog")) {
+			const char *name = ofnode_get_name(node);
+
+			device_bind_driver_to_node(dev, "gpio_hog", name,
+						   node, &child);
+		}
+	}
+#endif
 	return 0;
 }
 

drivers/mmc/Kconfig

@@ -158,21 +158,6 @@ config MMC_TRACE
 
 	  If you need to see the MMC core message, say Y.
 
-config SPL_MMC_TINY
-	bool "Tiny MMC framework in SPL"
-	help
-	  Enable MMC framework tinification support. This option is useful if
-	  if your SPL is extremely size constrained. Heed the warning, enable
-	  this option if and only if you know exactly what you are doing, if
-	  you are reading this help text, you most likely have no idea :-)
-
-	  The MMC framework is reduced to bare minimum to be useful. No malloc
-	  support is needed for the MMC framework operation with this option
-	  enabled. The framework supports exactly one MMC device and exactly
-	  one MMC driver. The MMC driver can be adjusted to avoid any malloc
-	  operations too, which can remove the need for malloc support in SPL
-	  and thus further reduce footprint.
-
 config MMC_DAVINCI
 	bool "TI DAVINCI Multimedia Card Interface support"
 	depends on ARCH_DAVINCI

drivers/mmc/mmc_legacy.c

@@ -150,6 +150,15 @@ struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
 {
 	struct mmc *mmc = &mmc_static;
 
+	/* First MMC device registered, fail to register a new one.
+	 * Given users are not expecting this to fail, instead
+	 * of failing let's just return the only MMC device
+	 */
+	if (mmc->cfg) {
+		debug("Warning: MMC_TINY doesn't support multiple MMC devices\n");
+		return mmc;
+	}
+
 	mmc->cfg = cfg;
 	mmc->priv = priv;
 

drivers/pci/pci-uclass.c

@@ -1572,9 +1572,9 @@ void pci_init(void)
 	 * Enumerate all known controller devices. Enumeration has the side-
 	 * effect of probing them, so PCIe devices will be enumerated too.
 	 */
-	for (uclass_first_device(UCLASS_PCI, &bus);
+	for (uclass_first_device_check(UCLASS_PCI, &bus);
 	     bus;
-	     uclass_next_device(&bus)) {
+	     uclass_next_device_check(&bus)) {
 		;
 	}
 }

drivers/pinctrl/pinctrl-single.c

@@ -16,6 +16,7 @@ struct single_pdata {
 	int offset;		/* index of last configuration register */
 	u32 mask;		/* configuration-value mask bits */
 	int width;		/* configuration register bit width */
+	bool bits_per_mux;
 };
 
 struct single_fdt_pin_cfg {
@@ -23,6 +24,12 @@ struct single_fdt_pin_cfg {
 	fdt32_t val;		/* configuration register value */
 };
 
+struct single_fdt_bits_cfg {
+	fdt32_t reg;		/* configuration register offset */
+	fdt32_t val;		/* configuration register value */
+	fdt32_t mask;		/* configuration register mask */
+};
+
 /**
  * single_configure_pins() - Configure pins based on FDT data
  *
@@ -71,15 +78,53 @@ static int single_configure_pins(struct udevice *dev,
 	return 0;
 }
 
+static int single_configure_bits(struct udevice *dev,
+				 const struct single_fdt_bits_cfg *pins,
+				 int size)
+{
+	struct single_pdata *pdata = dev->platdata;
+	int count = size / sizeof(struct single_fdt_bits_cfg);
+	phys_addr_t n, reg;
+	u32 val, mask;
+
+	for (n = 0; n < count; n++, pins++) {
+		reg = fdt32_to_cpu(pins->reg);
+		if ((reg < 0) || (reg > pdata->offset)) {
+			dev_dbg(dev, "  invalid register offset 0x%pa\n", &reg);
+			continue;
+		}
+		reg += pdata->base;
+
+		mask = fdt32_to_cpu(pins->mask);
+		val = fdt32_to_cpu(pins->val) & mask;
+
+		switch (pdata->width) {
+		case 16:
+			writew((readw(reg) & ~mask) | val, reg);
+			break;
+		case 32:
+			writel((readl(reg) & ~mask) | val, reg);
+			break;
+		default:
+			dev_warn(dev, "unsupported register width %i\n",
+				 pdata->width);
+			continue;
+		}
+		dev_dbg(dev, "  reg/val 0x%pa/0x%08x\n", &reg, val);
+	}
+	return 0;
+}
 static int single_set_state(struct udevice *dev,
 			    struct udevice *config)
 {
 	const void *fdt = gd->fdt_blob;
 	const struct single_fdt_pin_cfg *prop;
+	const struct single_fdt_bits_cfg *prop_bits;
 	int len;
 
 	prop = fdt_getprop(fdt, dev_of_offset(config), "pinctrl-single,pins",
 			   &len);
+
 	if (prop) {
 		dev_dbg(dev, "configuring pins for %s\n", config->name);
 		if (len % sizeof(struct single_fdt_pin_cfg)) {
@@ -87,9 +132,24 @@ static int single_set_state(struct udevice *dev,
 			return -FDT_ERR_BADSTRUCTURE;
 		}
 		single_configure_pins(dev, prop, len);
-		len = 0;
+		return 0;
 	}
 
+	/* pinctrl-single,pins not found so check for pinctrl-single,bits */
+	prop_bits = fdt_getprop(fdt, dev_of_offset(config),
+				"pinctrl-single,bits",
+				    &len);
+	if (prop_bits) {
+		dev_dbg(dev, "configuring pins for %s\n", config->name);
+		if (len % sizeof(struct single_fdt_bits_cfg)) {
+			dev_dbg(dev, "  invalid bits configuration in fdt\n");
+			return -FDT_ERR_BADSTRUCTURE;
+		}
+		single_configure_bits(dev, prop_bits, len);
+		return 0;
+	}
+
+	/* Neither 'pinctrl-single,pins' nor 'pinctrl-single,bits' were found */
 	return len;
 }
 
@@ -119,6 +179,9 @@ static int single_ofdata_to_platdata(struct udevice *dev)
 	pdata->mask = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
 				     "pinctrl-single,function-mask",
 				     0xffffffff);
+	pdata->bits_per_mux = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
+					      "pinctrl-single,bit-per-mux");
+
 	return 0;
 }
 

drivers/power/pmic/Kconfig

@@ -245,3 +245,24 @@ config PMIC_STPMIC1
 	The STPMIC1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF and 2 power switches.
 	It is accessed via an I2C interface. The device is used with STM32MP1
 	SoCs. This driver implements register read/write operations.
+
+config SPL_PMIC_PALMAS
+	bool "Enable driver for Texas Instruments PALMAS PMIC"
+	depends on DM_PMIC
+	help
+	The PALMAS is a PMIC containing several LDOs, SMPS.
+	This driver binds the pmic children in SPL.
+
+config SPL_PMIC_LP873X
+	bool "Enable driver for Texas Instruments LP873X PMIC"
+	depends on DM_PMIC
+	help
+	The LP873X is a PMIC containing couple of LDOs and couple of SMPS.
+	This driver binds the pmic children in SPL.
+
+config SPL_PMIC_LP87565
+	bool "Enable driver for Texas Instruments LP87565 PMIC"
+	depends on DM_PMIC
+	help
+	The LP87565 is a PMIC containing a bunch of SMPS.
+	This driver binds the pmic children in SPL.

drivers/power/regulator/Kconfig

@@ -258,3 +258,29 @@ config SPL_DM_REGULATOR_STPMIC1
 	depends on SPL_DM_REGULATOR && PMIC_STPMIC1
 	help
 	  Enable support for the regulator functions of the STPMIC1 PMIC in SPL.
+
+config SPL_DM_REGULATOR_PALMAS
+	bool "Enable driver for PALMAS PMIC regulators"
+       depends on SPL_PMIC_PALMAS
+	help
+	This enables implementation of driver-model regulator uclass
+	features for REGULATOR PALMAS and the family of PALMAS PMICs.
+	The driver implements get/set api for: value and enable in SPL.
+
+config SPL_DM_REGULATOR_LP87565
+	bool "Enable driver for LP87565 PMIC regulators"
+       depends on SPL_PMIC_LP87565
+	help
+	This enables implementation of driver-model regulator uclass
+	features for REGULATOR LP87565 and the family of LP87565 PMICs.
+	LP87565 series of PMICs have 4 single phase BUCKs that can also
+	be configured in multi phase modes. The driver implements
+	get/set api for value and enable in SPL.
+
+config SPL_DM_REGULATOR_LP873X
+	bool "Enable driver for LP873X PMIC regulators"
+	depends on SPL_PMIC_LP873X
+	help
+	This enables implementation of driver-model regulator uclass
+	features for REGULATOR LP873X and the family of LP873X PMICs.
+	The driver implements get/set api for: value and enable in SPL.

drivers/power/regulator/regulator-uclass.c

@@ -238,6 +238,9 @@ int regulator_autoset(struct udevice *dev)
 	if (!uc_pdata->always_on && !uc_pdata->boot_on)
 		return -EMEDIUMTYPE;
 
+	if (uc_pdata->type == REGULATOR_TYPE_FIXED)
+		return regulator_set_enable(dev, true);
+
 	if (uc_pdata->flags & REGULATOR_FLAG_AUTOSET_UV)
 		ret = regulator_set_value(dev, uc_pdata->min_uV);
 	if (!ret && (uc_pdata->flags & REGULATOR_FLAG_AUTOSET_UA))

drivers/rtc/Kconfig

@@ -70,6 +70,16 @@ config RTC_RV3029
 	  This driver supports reading and writing the RTC/calendar and the
 	  battery-baced SRAM section.
 
+config RTC_RV8803
+	bool "Enable RV8803 driver"
+	depends on DM_RTC
+	help
+	  The Micro Crystal RV8803 is a high accuracy, ultra-low power I2C
+	  Real Time Clock (RTC) with temperature compensation.
+
+	  This driver supports reading and writing the RTC/calendar and
+	  detects total power failures.
+
 config RTC_RX8010SJ
 	bool "Enable RX8010SJ driver"
 	depends on DM_RTC

drivers/rtc/Makefile

@@ -46,6 +46,7 @@ obj-$(CONFIG_RTC_PL031) += pl031.o
 obj-$(CONFIG_RTC_PT7C4338) += pt7c4338.o
 obj-$(CONFIG_RTC_RS5C372A) += rs5c372.o
 obj-$(CONFIG_RTC_RV3029) += rv3029.o
+obj-$(CONFIG_RTC_RV8803) += rv8803.o
 obj-$(CONFIG_RTC_RX8025) += rx8025.o
 obj-$(CONFIG_RTC_RX8010SJ) += rx8010sj.o
 obj-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o

drivers/rtc/ds1307.c

@@ -23,6 +23,7 @@ enum ds_type {
 	ds_1307,
 	ds_1337,
 	ds_1340,
+	m41t11,
 	mcp794xx,
 };
 
@@ -260,6 +261,18 @@ read_rtc:
 		}
 	}
 
+	if (type == m41t11) {
+		/* clock halted?  turn it on, so clock can tick. */
+		if (buf[RTC_SEC_REG_ADDR] & RTC_SEC_BIT_CH) {
+			buf[RTC_SEC_REG_ADDR] &= ~RTC_SEC_BIT_CH;
+			dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR,
+					 MCP7941X_BIT_ST);
+			dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR,
+					 buf[RTC_SEC_REG_ADDR]);
+			goto read_rtc;
+		}
+	}
+
 	if (type == mcp794xx) {
 		/* make sure that the backup battery is enabled */
 		if (!(buf[RTC_DAY_REG_ADDR] & MCP7941X_BIT_VBATEN)) {
@@ -332,6 +345,7 @@ static const struct udevice_id ds1307_rtc_ids[] = {
 	{ .compatible = "dallas,ds1337", .data = ds_1337 },
 	{ .compatible = "dallas,ds1340", .data = ds_1340 },
 	{ .compatible = "microchip,mcp7941x", .data = mcp794xx },
+	{ .compatible = "st,m41t11", .data = m41t11 },
 	{ }
 };
 

drivers/rtc/rv8803.c

@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Date & Time support for Micro Crystal RV-8803-C7.
+ *
+ * based on ds1307.c which is
+ *   (C) Copyright 2001, 2002, 2003
+ *   Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *   Keith Outwater, keith_outwater@mvis.com`
+ *   Steven Scholz, steven.scholz@imc-berlin.de
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <rtc.h>
+#include <i2c.h>
+
+/*
+ * RTC register addresses
+ */
+#define RTC_SEC_REG_ADDR	0x00
+#define RTC_MIN_REG_ADDR	0x01
+#define RTC_HR_REG_ADDR		0x02
+#define RTC_DAY_REG_ADDR	0x03
+#define RTC_DATE_REG_ADDR	0x04
+#define RTC_MON_REG_ADDR	0x05
+#define RTC_YR_REG_ADDR		0x06
+
+#define RTC_FLAG_REG_ADDR	0x0E
+#define RTC_FLAG_BIT_V1F	BIT(0)
+#define RTC_FLAG_BIT_V2F	BIT(1)
+
+#define RTC_CTL_REG_ADDR	0x0F
+#define RTC_CTL_BIT_RST		BIT(0)
+
+static int rv8803_rtc_set(struct udevice *dev, const struct rtc_time *tm)
+{
+	int ret;
+	u8 buf[7];
+
+	debug("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+	      tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
+	      tm->tm_hour, tm->tm_min, tm->tm_sec);
+
+	if (tm->tm_year < 2000 || tm->tm_year > 2099)
+		printf("WARNING: year should be between 2000 and 2099!\n");
+
+	buf[RTC_YR_REG_ADDR] = bin2bcd(tm->tm_year % 100);
+	buf[RTC_MON_REG_ADDR] = bin2bcd(tm->tm_mon);
+	buf[RTC_DAY_REG_ADDR] = 1 << (tm->tm_wday & 0x7);
+	buf[RTC_DATE_REG_ADDR] = bin2bcd(tm->tm_mday);
+	buf[RTC_HR_REG_ADDR] = bin2bcd(tm->tm_hour);
+	buf[RTC_MIN_REG_ADDR] = bin2bcd(tm->tm_min);
+	buf[RTC_SEC_REG_ADDR] = bin2bcd(tm->tm_sec);
+
+	ret = dm_i2c_write(dev, 0, buf, sizeof(buf));
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static int rv8803_rtc_get(struct udevice *dev, struct rtc_time *tm)
+{
+	int ret;
+	u8 buf[7];
+	int flags;
+
+	flags = dm_i2c_reg_read(dev, RTC_FLAG_REG_ADDR);
+	if (flags < 0)
+		return flags;
+	debug("%s: flags=%Xh\n", __func__, flags);
+
+	if (flags & RTC_FLAG_BIT_V1F)
+		printf("### Warning: temperature compensation has stopped\n");
+
+	if (flags & RTC_FLAG_BIT_V2F) {
+		printf("### Warning: Voltage low, data is invalid\n");
+		return -1;
+	}
+
+	ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
+	if (ret < 0)
+		return ret;
+
+	tm->tm_sec  = bcd2bin(buf[RTC_SEC_REG_ADDR] & 0x7F);
+	tm->tm_min  = bcd2bin(buf[RTC_MIN_REG_ADDR] & 0x7F);
+	tm->tm_hour = bcd2bin(buf[RTC_HR_REG_ADDR] & 0x3F);
+	tm->tm_mday = bcd2bin(buf[RTC_DATE_REG_ADDR] & 0x3F);
+	tm->tm_mon  = bcd2bin(buf[RTC_MON_REG_ADDR] & 0x1F);
+	tm->tm_year = bcd2bin(buf[RTC_YR_REG_ADDR]) + 2000;
+	tm->tm_wday = fls(buf[RTC_DAY_REG_ADDR] & 0x7F) - 1;
+	tm->tm_yday = 0;
+	tm->tm_isdst = 0;
+
+	debug("Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+	      tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
+	      tm->tm_hour, tm->tm_min, tm->tm_sec);
+
+	return 0;
+}
+
+static int rv8803_rtc_reset(struct udevice *dev)
+{
+	int ret;
+	struct rtc_time tmp = {
+		.tm_year = 2000,
+		.tm_mon = 1,
+		.tm_mday = 1,
+		.tm_hour = 0,
+		.tm_min = 0,
+		.tm_sec = 0,
+	};
+
+	/* assert reset */
+	ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR, RTC_CTL_BIT_RST);
+	if (ret < 0)
+		return ret;
+
+	/* clear all flags */
+	ret = dm_i2c_reg_write(dev, RTC_FLAG_REG_ADDR, 0);
+	if (ret < 0)
+		return ret;
+
+	ret = rv8803_rtc_set(dev, &tmp);
+	if (ret < 0)
+		return ret;
+
+	/* clear reset */
+	ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR, 0);
+	if (ret < 0)
+		return ret;
+
+	debug("RTC:   %4d-%02d-%02d %2d:%02d:%02d UTC\n",
+	      tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
+	      tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
+
+	return 0;
+}
+
+static int rv8803_probe(struct udevice *dev)
+{
+	i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS |
+			   DM_I2C_CHIP_WR_ADDRESS);
+
+	return 0;
+}
+
+static const struct rtc_ops rv8803_rtc_ops = {
+	.get = rv8803_rtc_get,
+	.set = rv8803_rtc_set,
+	.reset = rv8803_rtc_reset,
+};
+
+static const struct udevice_id rv8803_rtc_ids[] = {
+	{ .compatible = "microcrystal,rv8803", },
+	{ }
+};
+
+U_BOOT_DRIVER(rtc_rv8803) = {
+	.name	= "rtc-rv8803",
+	.id	= UCLASS_RTC,
+	.probe	= rv8803_probe,
+	.of_match = rv8803_rtc_ids,
+	.ops	= &rv8803_rtc_ops,
+};

drivers/usb/musb-new/omap2430.c

@@ -215,11 +215,13 @@ static int omap2430_musb_probe(struct udevice *dev)
 {
 #ifdef CONFIG_USB_MUSB_HOST
 	struct musb_host_data *host = dev_get_priv(dev);
+#else
+	struct musb *musbp;
 #endif
 	struct omap2430_musb_platdata *platdata = dev_get_platdata(dev);
 	struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
 	struct omap_musb_board_data *otg_board_data;
-	int ret;
+	int ret = 0;
 	void *base = dev_read_addr_ptr(dev);
 
 	priv->desc_before_addr = true;
@@ -236,9 +238,11 @@ static int omap2430_musb_probe(struct udevice *dev)
 
 	ret = musb_lowlevel_init(host);
 #else
-	ret = musb_register(&platdata->plat,
+	musbp = musb_register(&platdata->plat,
 			  (struct device *)otg_board_data,
 			  platdata->base);
+	if (IS_ERR_OR_NULL(musbp))
+		return -EINVAL;
 #endif
 	return ret;
 }

include/asm-generic/gpio.h

@@ -348,6 +348,22 @@ const char *gpio_get_bank_info(struct udevice *dev, int *offset_count);
  */
 int dm_gpio_lookup_name(const char *name, struct gpio_desc *desc);
 
+/**
+ * gpio_hog_lookup_name() - Look up a named GPIO and return the gpio descr.
+ *
+ * @name:	Name to look up
+ * @return:	Returns gpio_desc for gpio
+ */
+struct gpio_desc *gpio_hog_lookup_name(const char *name);
+
+/**
+ * gpio_hog_probe_all() - probe all gpio devices with
+ * gpio-hog subnodes.
+ *
+ * @return:	Returns return value from device_probe()
+ */
+int gpio_hog_probe_all(void);
+
 /**
  * gpio_lookup_name - Look up a GPIO name and return its details
  *
@@ -503,6 +519,22 @@ int gpio_request_list_by_name_nodev(ofnode node, const char *list_name,
 				    struct gpio_desc *desc_list, int max_count,
 				    int flags);
 
+/**
+ * gpio_dev_request_index() - request single GPIO from gpio device
+ *
+ * @dev:	GPIO device
+ * @nodename:	Name of node
+ * @list_name:	Name of GPIO list (e.g. "board-id-gpios")
+ * @index:	Index number of the GPIO in that list use request (0=first)
+ * @flags:	GPIOD_* flags
+ * @dtflags:	GPIO flags read from DT
+ * @desc:	GPIO descriotor filled from this function
+ * @return:	return value from gpio_request_tail()
+ */
+int gpio_dev_request_index(struct udevice *dev, const char *nodename,
+			   char *list_name, int index, int flags,
+			   int dtflags, struct gpio_desc *desc);
+
 /**
  * dm_gpio_free() - Free a single GPIO
  *

include/configs/legoev3.h

@@ -42,11 +42,8 @@
  * Serial Driver info
  */
 #define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size */
-#define CONFIG_SYS_NS16550_COM1	DAVINCI_UART1_BASE /* Base address of UART1 */
 #define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
 
-#define CONFIG_SYS_SPI_BASE		DAVINCI_SPI0_BASE
 #define CONFIG_SYS_SPI_CLK		clk_get(DAVINCI_SPI0_CLKID)
 
 /*

include/configs/omap3_evm.h

@@ -52,9 +52,6 @@
 #endif /* CONFIG_SPL_OS_BOOT */
 #endif /* CONFIG_NAND */
 
-/* Environment */
-#define CONFIG_PREBOOT                  "usb start"
-
 #define MEM_LAYOUT_ENV_SETTINGS \
 	DEFAULT_LINUX_BOOT_ENV
 

include/configs/phycore_am335x_r2.h

@@ -0,0 +1,128 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * phycore_am335x_r2.h
+ *
+ * Phytec phyCORE-AM335x R2 (PCL060 / PCM060) boards information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
+ * Copyright (C) 2019 DENX Software Engineering GmbH
+ */
+
+#ifndef __CONFIG_PHYCORE_AM335x_R2_H
+#define __CONFIG_PHYCORE_AM335x_R2_H
+
+#include <configs/ti_am335x_common.h>
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_SBC_PHYCORE_AM335X
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+
+#ifdef CONFIG_NAND
+#define NANDARGS \
+	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
+	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype}\0" \
+	"nandroot=ubi0:root ubi.mtd=NAND.UBI\0" \
+	"nandrootfstype=ubifs rootwait rw fsck.repair=yes\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"ubi part NAND.UBI; " \
+		"ubi readvol ${fdtaddr} oftree; " \
+		"ubi readvol ${loadaddr} kernel; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0"
+
+#else
+#define NANDARGS ""
+#endif
+
+/* set to negative value for no autoboot */
+#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
+	"bootcmd_" #devtypel #instance "=" \
+	"setenv mmcdev " #instance "; "\
+	"setenv bootpart " #instance ":1 ; "\
+	"setenv rootpart " #instance ":2 ; "\
+	"run mmcboot\0"
+
+#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
+	#devtypel #instance " "
+
+#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
+	"bootcmd_" #devtypel #instance "=" \
+	"run nandboot\0"
+
+#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
+	#devtypel #instance " "
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(LEGACY_MMC, legacy_mmc, 0) \
+	func(MMC, mmc, 1) \
+	func(LEGACY_MMC, legacy_mmc, 1) \
+	func(NAND, nand, 0)
+
+#include <config_distro_bootcmd.h>
+#include <environment/ti/dfu.h>
+#include <environment/ti/mmc.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	DEFAULT_MMC_TI_ARGS \
+	DEFAULT_LINUX_BOOT_ENV \
+	"bootfile=zImage\0" \
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"console=ttyS0,115200\0" \
+	"optargs=\0" \
+	"mmcrootfstype=ext2 rootwait\0" \
+	"finduuid=part uuid mmc ${rootpart} uuid\0" \
+	"boot_fit=0\0" \
+	NANDARGS \
+	BOOTENV
+
+/* Clock Macros */
+#define V_OSCK				25000000  /* Clock output from T2 */
+#define V_SCLK				V_OSCK
+
+#define CONFIG_POWER_TPS65910
+
+#ifdef CONFIG_NAND
+/* NAND: device related configs */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+/* NAND: driver related configs */
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW
+
+/* NAND: SPL related configs */
+#ifdef CONFIG_SPL_OS_BOOT
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00200000 /* kernel offset */
+#endif
+#endif /* !CONFIG_NAND */
+
+/* CPU */
+
+#ifdef CONFIG_SPI_BOOT
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
+#define CONFIG_SYS_SPI_U_BOOT_SIZE	0x40000
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+#define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
+#endif
+
+#endif	/* ! __CONFIG_PHYCORE_AM335x_R2_H */

lib/Kconfig

@@ -97,6 +97,8 @@ config SYS_HZ
 
 config USE_TINY_PRINTF
 	bool "Enable tiny printf() version"
+	depends on SPL || TPL
+	default y
 	help
 	  This option enables a tiny, stripped down printf version.
 	  This should only be used in space limited environments,

test/dm/adc.c

@@ -24,7 +24,7 @@ static int dm_test_adc_bind(struct unit_test_state *uts)
 	struct udevice *dev;
 	unsigned int channel_mask;
 
-	ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc", &dev));
+	ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc@0", &dev));
 	ut_asserteq_str(SANDBOX_ADC_DEVNAME, dev->name);
 
 	ut_assertok(adc_channel_mask(dev, &channel_mask));
@@ -38,7 +38,7 @@ static int dm_test_adc_wrong_channel_selection(struct unit_test_state *uts)
 {
 	struct udevice *dev;
 
-	ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc", &dev));
+	ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc@0", &dev));
 	ut_asserteq(-EINVAL, adc_start_channel(dev, SANDBOX_ADC_CHANNELS));
 
 	return 0;
@@ -51,7 +51,7 @@ static int dm_test_adc_supply(struct unit_test_state *uts)
 	struct udevice *dev;
 	int uV;
 
-	ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc", &dev));
+	ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc@0", &dev));
 
 	/* Test Vss value - predefined 0 uV */
 	ut_assertok(adc_vss_value(dev, &uV));
@@ -94,7 +94,7 @@ static int dm_test_adc_single_channel_conversion(struct unit_test_state *uts)
 	unsigned int i, data;
 	struct udevice *dev;
 
-	ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc", &dev));
+	ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc@0", &dev));
 	/* Test each ADC channel's value */
 	for (i = 0; i < SANDBOX_ADC_CHANNELS; i++, tdata++) {
 		ut_assertok(adc_start_channel(dev, tdata->id));
@@ -117,7 +117,7 @@ static int dm_test_adc_multi_channel_conversion(struct unit_test_state *uts)
 		       ADC_CHANNEL(2) | ADC_CHANNEL(3);
 
 	/* Start multi channel conversion */
-	ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc", &dev));
+	ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc@0", &dev));
 	ut_assertok(adc_start_channels(dev, channel_mask));
 	ut_assertok(adc_channels_data(dev, channel_mask, channels));
 
@@ -136,7 +136,7 @@ static int dm_test_adc_single_channel_shot(struct unit_test_state *uts)
 
 	for (i = 0; i < SANDBOX_ADC_CHANNELS; i++, tdata++) {
 		/* Start single channel conversion */
-		ut_assertok(adc_channel_single_shot("adc", tdata->id, &data));
+		ut_assertok(adc_channel_single_shot("adc@0", tdata->id, &data));
 		/* Compare the expected and returned conversion data. */
 		ut_asserteq(tdata->data, data);
 	}
@@ -155,7 +155,7 @@ static int dm_test_adc_multi_channel_shot(struct unit_test_state *uts)
 		       ADC_CHANNEL(2) | ADC_CHANNEL(3);
 
 	/* Start single call and multi channel conversion */
-	ut_assertok(adc_channels_single_shot("adc", channel_mask, channels));
+	ut_assertok(adc_channels_single_shot("adc@0", channel_mask, channels));
 
 	/* Compare the expected and returned conversion data. */
 	for (i = 0; i < SANDBOX_ADC_CHANNELS; i++, tdata++)
@@ -183,7 +183,7 @@ static int dm_test_adc_raw_to_uV(struct unit_test_state *uts)
 	struct udevice *dev;
 	int uV;
 
-	ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc", &dev));
+	ut_assertok(uclass_get_device_by_name(UCLASS_ADC, "adc@0", &dev));
 	/* Test each ADC channel's value in microvolts */
 	for (i = 0; i < SANDBOX_ADC_CHANNELS; i++, tdata++) {
 		ut_assertok(adc_start_channel(dev, tdata->id));

test/dm/usb.c

@@ -125,7 +125,7 @@ static int dm_test_usb_keyb(struct unit_test_state *uts)
 	/* Initially there should be no characters */
 	ut_asserteq(0, tstc());
 
-	ut_assertok(uclass_get_device_by_name(UCLASS_USB_EMUL, "keyb",
+	ut_assertok(uclass_get_device_by_name(UCLASS_USB_EMUL, "keyb@3",
 					      &dev));
 
 	/*