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rockchip: rk3328: add board_debug_uart_init()

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Add board_debug_uart_init() to make the debug UART work with
correct setting.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Kever Yang 2019-07-22 20:01:58 +08:00
parent b7abef2ecb
commit 604814c8dc
1 changed files with 49 additions and 0 deletions
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49
arch/arm/mach-rockchip/rk3328/rk3328.c
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@ -6,11 +6,17 @@
#include <common.h> #include <common.h>
#include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/grf_rk3328.h>
#include <asm/arch-rockchip/uart.h>
#include <asm/armv8/mmu.h> #include <asm/armv8/mmu.h>
#include <asm/io.h> #include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
#define CRU_BASE 0xFF440000
#define GRF_BASE 0xFF100000
#define UART2_BASE 0xFF130000
const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
[BROM_BOOTSOURCE_EMMC] = "rksdmmc@ff520000", [BROM_BOOTSOURCE_EMMC] = "rksdmmc@ff520000",
[BROM_BOOTSOURCE_SD] = "rksdmmc@ff500000", [BROM_BOOTSOURCE_SD] = "rksdmmc@ff500000",
@ -55,3 +61,46 @@ int arch_cpu_init(void)
return 0; return 0;
} }
void board_debug_uart_init(void)
{
struct rk3328_grf_regs * const grf = (void *)GRF_BASE;
struct rk_uart * const uart = (void *)UART2_BASE;
enum{
GPIO2A0_SEL_SHIFT = 0,
GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT,
GPIO2A0_UART2_TX_M1 = 1,
GPIO2A1_SEL_SHIFT = 2,
GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT,
GPIO2A1_UART2_RX_M1 = 1,
};
enum {
IOMUX_SEL_UART2_SHIFT = 0,
IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT,
IOMUX_SEL_UART2_M0 = 0,
IOMUX_SEL_UART2_M1,
};
/* uart_sel_clk default select 24MHz */
writel((3 << (8 + 16)) | (2 << 8), CRU_BASE + 0x148);
/* init uart baud rate 1500000 */
writel(0x83, &uart->lcr);
writel(0x1, &uart->rbr);
writel(0x3, &uart->lcr);
/* Enable early UART2 */
rk_clrsetreg(&grf->com_iomux,
IOMUX_SEL_UART2_MASK,
IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT);
rk_clrsetreg(&grf->gpio2a_iomux,
GPIO2A0_SEL_MASK,
GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT);
rk_clrsetreg(&grf->gpio2a_iomux,
GPIO2A1_SEL_MASK,
GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT);
/* enable FIFO */
writel(0x1, &uart->sfe);
}