mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx
This commit is contained in:
Tom Rini
commit
5fcb084932
1 changed files with 101 additions and 64 deletions
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@ -12,7 +12,6 @@
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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@ -34,14 +33,14 @@
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DECLARE_GLOBAL_DATA_PTR;
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extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
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extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
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extern void __ft_board_setup(void *blob, bd_t *bd);
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ulong flash_get_size(ulong base, int banknum);
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int pci_is_66mhz(void);
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static int pci_is_66mhz(void);
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int is_monarch(void);
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int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
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uchar *buffer, unsigned cnt);
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static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
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uchar *buffer, unsigned cnt);
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struct serial_device *default_serial_console(void)
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{
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@ -58,23 +57,24 @@ struct serial_device *default_serial_console(void)
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if (((val & 0xf0000000) >> 29) != 7)
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return &eserial2_device;
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ulong scratchreg = in_be32((void*)GPIO0_ISR3L);
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ulong scratchreg = in_be32((void *)GPIO0_ISR3L);
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if (!(scratchreg & 0x80)) {
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/* mark scratchreg valid */
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scratchreg = (scratchreg & 0xffffff00) | 0x80;
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i2c_init_all();
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i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
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0x10, buf, 4);
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if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
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scratchreg |= buf[2];
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/* bringup delay for console */
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for (delay=0; delay<(1000 * (ulong)buf[3]); delay++) {
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for (delay = 0; delay < (1000 * (ulong)buf[3]); delay++)
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udelay(1000);
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}
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} else
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scratchreg |= 0x01;
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out_be32((void*)GPIO0_ISR3L, scratchreg);
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out_be32((void *)GPIO0_ISR3L, scratchreg);
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}
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if (scratchreg & 0x01)
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@ -93,10 +93,7 @@ int board_early_init_f(void)
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mtdcr(EBC0_CFGADDR, EBC0_CFG);
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mtdcr(EBC0_CFGDATA, 0xf8400000);
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/*
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* Setup the GPIO pins
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* TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file
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*/
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/* Setup the GPIO pins */
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out_be32((void *)GPIO0_OR, 0x40000102);
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out_be32((void *)GPIO0_TCR, 0x4c90011f);
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out_be32((void *)GPIO0_OSRL, 0x28051400);
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@ -259,7 +256,7 @@ int misc_init_r(void)
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* USB suff...
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*/
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if ((act == NULL || strcmp(act, "host") == 0) &&
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!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){
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!(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
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/* SDR Setting */
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mfsdr(SDR0_PFC1, sdr0_pfc1);
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mfsdr(SDR0_USB2D0CR, usb2d0cr);
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@ -326,16 +323,16 @@ int misc_init_r(void)
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mtsdr(SDR0_SRST1, 0x00000000);
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mtsdr(SDR0_SRST0, 0x00000000);
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if (!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
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if (!(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
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/* enable power on USB socket */
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out_be32((void*)GPIO1_OR,
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in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
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out_be32((void *)GPIO1_OR,
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in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N);
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}
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printf("USB: Host\n");
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} else if ((strcmp(act, "dev") == 0) ||
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(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
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(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT)) {
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mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
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@ -414,30 +411,31 @@ int misc_init_r(void)
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#endif
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/* turn off POST LED */
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out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_POST_N);
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out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) & ~GPIO1_POST_N);
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/* turn on RUN LED */
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out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~GPIO0_LED_RUN_N);
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out_be32((void *)GPIO0_OR,
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in_be32((void *)GPIO0_OR) & ~GPIO0_LED_RUN_N);
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return 0;
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}
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int is_monarch(void)
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{
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if (in_be32((void*)GPIO1_IR) & GPIO1_NONMONARCH)
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if (in_be32((void *)GPIO1_IR) & GPIO1_NONMONARCH)
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return 0;
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return 1;
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}
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int pci_is_66mhz(void)
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static int pci_is_66mhz(void)
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{
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if (in_be32((void*)GPIO1_IR) & GPIO1_M66EN)
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if (in_be32((void *)GPIO1_IR) & GPIO1_M66EN)
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return 1;
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return 0;
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}
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int board_revision(void)
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static int board_revision(void)
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{
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return (int)((in_be32((void*)GPIO1_IR) & GPIO1_HWID_MASK) >> 4);
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return (int)((in_be32((void *)GPIO1_IR) & GPIO1_HWID_MASK) >> 4);
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}
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int checkboard(void)
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@ -495,7 +493,7 @@ void pci_target_init(struct pci_controller *hose)
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out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
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/* - disabled b4 setting */
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out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
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out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
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out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Addr */
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out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
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out32r(PCIL0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */
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/* and enable region */
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@ -532,7 +530,8 @@ void pci_target_init(struct pci_controller *hose)
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if (is_monarch()) {
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/* BAR2: map FPGA registers behind system memory at 1GB */
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pci_hose_write_config_dword(hose, 0, PCI_BASE_ADDRESS_2, 0x40000008);
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pci_hose_write_config_dword(hose, 0,
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PCI_BASE_ADDRESS_2, 0x40000008);
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}
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/*
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@ -562,10 +561,10 @@ void pci_target_init(struct pci_controller *hose)
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CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
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/* PCI configuration done: release ERREADY */
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out_be32((void*)GPIO1_OR,
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in_be32((void*)GPIO1_OR) | GPIO1_PPC_EREADY);
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out_be32((void*)GPIO1_TCR,
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in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY);
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out_be32((void *)GPIO1_OR,
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in_be32((void *)GPIO1_OR) | GPIO1_PPC_EREADY);
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out_be32((void *)GPIO1_TCR,
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in_be32((void *)GPIO1_TCR) | GPIO1_PPC_EREADY);
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} else {
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/* Program the board's subsystem id/classcode */
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pci_hose_write_config_word(hose, 0, PCI_SUBSYSTEM_ID,
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@ -595,14 +594,14 @@ void pci_master_init(struct pci_controller *hose)
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static void wait_for_pci_ready(void)
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{
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if (!(in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY)) {
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if (!(in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY)) {
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printf("PCI: Waiting for EREADY (CTRL-C to skip) ... ");
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while (1) {
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if (ctrlc()) {
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puts("abort\n");
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break;
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}
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if (in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY) {
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if (in_be32((void *)GPIO1_IR) & GPIO1_PPC_EREADY) {
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printf("done\n");
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break;
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}
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@ -641,34 +640,73 @@ int is_pci_host(struct pci_controller *hose)
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#endif /* defined(CONFIG_PCI) */
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#ifdef CONFIG_RESET_PHY_R
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static int pmc440_setup_vsc8601(char *devname, int phy_addr,
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unsigned short behavior, unsigned short method)
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{
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/* adjust LED behavior */
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if (miiphy_write(devname, phy_addr, 0x1f, 0x0001) != 0) {
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printf("Phy%d: register write access failed\n", phy_addr);
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return -1;
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}
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miiphy_write(devname, phy_addr, 0x11, 0x0010);
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miiphy_write(devname, phy_addr, 0x11, behavior);
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miiphy_write(devname, phy_addr, 0x10, method);
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miiphy_write(devname, phy_addr, 0x1f, 0x0000);
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return 0;
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}
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static int pmc440_setup_ksz9031(char *devname, int phy_addr)
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{
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unsigned short id1, id2;
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if (miiphy_read(devname, phy_addr, 2, &id1) ||
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miiphy_read(devname, phy_addr, 3, &id2)) {
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printf("Phy%d: cannot read id\n", phy_addr);
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return -1;
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}
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if ((id1 != 0x0022) || ((id2 & 0xfff0) != 0x1620)) {
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printf("Phy%d: unexpected id\n", phy_addr);
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return -1;
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}
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/* MMD 2.08: adjust tx_clk pad skew */
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miiphy_write(devname, phy_addr, 0x0d, 2);
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miiphy_write(devname, phy_addr, 0x0e, 8);
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miiphy_write(devname, phy_addr, 0x0d, 0x4002);
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miiphy_write(devname, phy_addr, 0x0e, 0xf | (0x17 << 5));
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return 0;
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}
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void reset_phy(void)
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{
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char *s;
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unsigned short val_method, val_behavior;
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/* special LED setup for NGCC/CANDES */
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if ((s = getenv("bd_type")) &&
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((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) {
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val_method = 0x0e0a;
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val_behavior = 0x0cf2;
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if (gd->board_type < 4) {
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/* special LED setup for NGCC/CANDES */
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s = getenv("bd_type");
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if (s && ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) {
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val_method = 0x0e0a;
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val_behavior = 0x0cf2;
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} else {
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/* PMC440 standard type */
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val_method = 0x0e10;
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val_behavior = 0x0cf0;
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}
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/* boards up to rev. 1.3 use Vitesse VSC8601 phys */
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pmc440_setup_vsc8601("ppc_4xx_eth0", CONFIG_PHY_ADDR,
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val_method, val_behavior);
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pmc440_setup_vsc8601("ppc_4xx_eth1", CONFIG_PHY1_ADDR,
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val_method, val_behavior);
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} else {
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/* PMC440 standard type */
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val_method = 0x0e10;
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val_behavior = 0x0cf0;
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}
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if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) {
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miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010);
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miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, val_behavior);
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miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, val_method);
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miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000);
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}
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if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) {
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miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010);
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miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, val_behavior);
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miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, val_method);
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miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000);
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/* rev. 1.4 uses a Micrel KSZ9031 */
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pmc440_setup_ksz9031("ppc_4xx_eth0", CONFIG_PHY_ADDR);
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pmc440_setup_ksz9031("ppc_4xx_eth1", CONFIG_PHY1_ADDR);
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}
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}
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#endif
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@ -729,7 +767,6 @@ int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
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* We must write the address again when changing pages
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* because the address counter only increments within a page.
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*/
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while (offset < end) {
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unsigned alen, len;
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unsigned maxlen;
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@ -771,8 +808,8 @@ int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
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return rcode;
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}
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int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset,
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uchar *buffer, unsigned cnt)
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static int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,
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uchar *buffer, unsigned cnt)
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{
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unsigned end = offset + cnt;
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unsigned blk_off;
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@ -820,10 +857,10 @@ int board_usb_init(int index, enum usb_init_type init)
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int i;
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if ((act == NULL || strcmp(act, "host") == 0) &&
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!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT))
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!(in_be32((void *)GPIO0_IR) & GPIO0_USB_PRSNT))
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/* enable power on USB socket */
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out_be32((void*)GPIO1_OR,
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in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
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out_be32((void *)GPIO1_OR,
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in_be32((void *)GPIO1_OR) & ~GPIO1_USB_PWR_N);
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for (i=0; i<1000; i++)
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udelay(1000);
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@ -834,7 +871,7 @@ int board_usb_init(int index, enum usb_init_type init)
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int usb_board_stop(void)
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{
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/* disable power on USB socket */
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out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_USB_PWR_N);
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out_be32((void *)GPIO1_OR, in_be32((void *)GPIO1_OR) | GPIO1_USB_PWR_N);
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return 0;
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}
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@ -858,8 +895,8 @@ void ft_board_setup(void *blob, bd_t *bd)
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rc = fdt_find_and_setprop(blob, "/plb/pci@1ec000000", "status",
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"disabled", sizeof("disabled"), 1);
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if (rc) {
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printf("Unable to update property status in PCI node, err=%s\n",
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fdt_strerror(rc));
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printf("Unable to update property status in PCI node, ");
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printf("err=%s\n", fdt_strerror(rc));
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}
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}
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}
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