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net: zynq_gem: Add check for 64-bit dma support by hardware

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This patch throws an error if 64-bit support is expected
but DMA hardware is not capable of 64-bit support. It also
prints a debug message if DMA is capable of 64-bit but not
using it.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
This commit is contained in:
Siva Durga Prasad Paladugu 2018-11-26 16:27:39 +05:30 committed by Michal Simek
parent 9a7799f4f4
commit 5f68f44c14
1 changed files with 23 additions and 1 deletions
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24
drivers/net/zynq_gem.c
View file

@ -102,6 +102,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000 #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000
#define ZYNQ_GEM_DCFG_DBG6_DMA_64B BIT(23)
/* Use MII register 1 (MII status register) to detect PHY */ /* Use MII register 1 (MII status register) to detect PHY */
#define PHY_DETECT_REG 1 #define PHY_DETECT_REG 1
@ -150,7 +152,9 @@ struct zynq_gem_regs {
u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
u32 reserved9[20]; u32 reserved9[20];
u32 pcscntrl; u32 pcscntrl;
u32 reserved7[143]; u32 rserved12[36];
u32 dcfg6; /* 0x294 Design config reg6 */
u32 reserved7[106];
u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
u32 reserved8[15]; u32 reserved8[15];
u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
@ -198,6 +202,7 @@ struct zynq_gem_priv {
struct clk clk; struct clk clk;
u32 max_speed; u32 max_speed;
bool int_pcs; bool int_pcs;
bool dma_64bit;
}; };
static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
@ -378,6 +383,23 @@ static int zynq_gem_init(struct udevice *dev)
struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
if (readl(&regs->dcfg6) & ZYNQ_GEM_DCFG_DBG6_DMA_64B)
priv->dma_64bit = true;
else
priv->dma_64bit = false;
#if defined(CONFIG_PHYS_64BIT)
if (!priv->dma_64bit) {
printf("ERR: %s: Using 64-bit DMA but HW doesn't support it\n",
__func__);
return -EINVAL;
}
#else
if (priv->dma_64bit)
debug("WARN: %s: Not using 64-bit dma even HW supports it\n",
__func__);
#endif
if (!priv->init) { if (!priv->init) {
/* Disable all interrupts */ /* Disable all interrupts */
writel(0xFFFFFFFF, &regs->idr); writel(0xFFFFFFFF, &regs->idr);