mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-21 07:01:57 +00:00
ARM: Add support for IGEP COM AQUILA/CYGNUS
The IGEP COM AQUILA and CYGNUS are industrial processors modules with following highlights: o AM3352/AM3354 Texas Instruments processor o Cortex-A8 ARM CPU o 3.3 volts Inputs / Outputs use industrial o 256 MB DDR3 SDRAM / 128 Megabytes FLASH o MicroSD card reader on-board o Ethernet controller on-board o JTAG debug connector available o Designed for industrial range purposes Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
This commit is contained in:
Enric Balletbo i Serra
Tom Rini
parent
cc175e6353
commit
5f5c1d13d3
7 changed files with 680 additions and 0 deletions
|
|
@ -607,6 +607,7 @@ Enric Balletbo i Serra <eballetbo@iseebcn.com>
|
||||||
igep0020 ARM ARMV7 (OMAP3xx SoC)
|
igep0020 ARM ARMV7 (OMAP3xx SoC)
|
||||||
igep0030 ARM ARMV7 (OMAP3xx SoC)
|
igep0030 ARM ARMV7 (OMAP3xx SoC)
|
||||||
igep0032 ARM ARMV7 (OMAP3xx SoC)
|
igep0032 ARM ARMV7 (OMAP3xx SoC)
|
||||||
|
igep0033 ARM ARMV7 (AM33xx Soc)
|
||||||
|
|
||||||
Eric Benard <eric@eukrea.com>
|
Eric Benard <eric@eukrea.com>
|
||||||
|
|
||||||
|
|
|
||||||
46
board/isee/igep0033/Makefile
Normal file
46
board/isee/igep0033/Makefile
Normal file
|
|
@ -0,0 +1,46 @@
|
||||||
|
#
|
||||||
|
# Makefile
|
||||||
|
#
|
||||||
|
# Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
|
||||||
|
#
|
||||||
|
# This program is free software; you can redistribute it and/or
|
||||||
|
# modify it under the terms of the GNU General Public License as
|
||||||
|
# published by the Free Software Foundation; either version 2 of
|
||||||
|
# the License, or (at your option) any later version.
|
||||||
|
#
|
||||||
|
# This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||||
|
# kind, whether express or implied; without even the implied warranty
|
||||||
|
# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU General Public License for more details.
|
||||||
|
#
|
||||||
|
|
||||||
|
include $(TOPDIR)/config.mk
|
||||||
|
|
||||||
|
LIB = $(obj)lib$(BOARD).o
|
||||||
|
|
||||||
|
ifdef CONFIG_SPL_BUILD
|
||||||
|
COBJS := mux.o
|
||||||
|
endif
|
||||||
|
|
||||||
|
COBJS += board.o
|
||||||
|
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||||
|
OBJS := $(addprefix $(obj),$(COBJS))
|
||||||
|
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||||
|
|
||||||
|
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||||
|
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
|
||||||
|
|
||||||
|
clean:
|
||||||
|
rm -f $(SOBJS) $(OBJS)
|
||||||
|
|
||||||
|
distclean: clean
|
||||||
|
rm -f $(LIB) core *.bak $(obj).depend
|
||||||
|
|
||||||
|
#########################################################################
|
||||||
|
|
||||||
|
# defines $(obj).depend target
|
||||||
|
include $(SRCTREE)/rules.mk
|
||||||
|
|
||||||
|
sinclude $(obj).depend
|
||||||
|
|
||||||
|
#########################################################################
|
||||||
232
board/isee/igep0033/board.c
Normal file
232
board/isee/igep0033/board.c
Normal file
|
|
@ -0,0 +1,232 @@
|
||||||
|
/*
|
||||||
|
* Board functions for IGEP COM AQUILA/CYGNUS based boards
|
||||||
|
*
|
||||||
|
* Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <errno.h>
|
||||||
|
#include <spl.h>
|
||||||
|
#include <asm/arch/cpu.h>
|
||||||
|
#include <asm/arch/hardware.h>
|
||||||
|
#include <asm/arch/omap.h>
|
||||||
|
#include <asm/arch/ddr_defs.h>
|
||||||
|
#include <asm/arch/clock.h>
|
||||||
|
#include <asm/arch/gpio.h>
|
||||||
|
#include <asm/arch/mmc_host_def.h>
|
||||||
|
#include <asm/arch/sys_proto.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <asm/emif.h>
|
||||||
|
#include <asm/gpio.h>
|
||||||
|
#include <i2c.h>
|
||||||
|
#include <miiphy.h>
|
||||||
|
#include <cpsw.h>
|
||||||
|
#include "board.h"
|
||||||
|
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
|
||||||
|
#ifdef CONFIG_SPL_BUILD
|
||||||
|
static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* MII mode defines */
|
||||||
|
#define RMII_MODE_ENABLE 0x4D
|
||||||
|
|
||||||
|
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
|
||||||
|
|
||||||
|
/* UART Defines */
|
||||||
|
#ifdef CONFIG_SPL_BUILD
|
||||||
|
#define UART_RESET (0x1 << 1)
|
||||||
|
#define UART_CLK_RUNNING_MASK 0x1
|
||||||
|
#define UART_SMART_IDLE_EN (0x1 << 0x3)
|
||||||
|
|
||||||
|
static void rtc32k_enable(void)
|
||||||
|
{
|
||||||
|
struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Unlock the RTC's registers. For more details please see the
|
||||||
|
* RTC_SS section of the TRM. In order to unlock we need to
|
||||||
|
* write these specific values (keys) in this order.
|
||||||
|
*/
|
||||||
|
writel(0x83e70b13, &rtc->kick0r);
|
||||||
|
writel(0x95a4f1e0, &rtc->kick1r);
|
||||||
|
|
||||||
|
/* Enable the RTC 32K OSC by setting bits 3 and 6. */
|
||||||
|
writel((1 << 3) | (1 << 6), &rtc->osc);
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct ddr_data ddr3_data = {
|
||||||
|
.datardsratio0 = K4B2G1646EBIH9_RD_DQS,
|
||||||
|
.datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
|
||||||
|
.datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
|
||||||
|
.datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
|
||||||
|
.datadldiff0 = PHY_DLL_LOCK_DIFF,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct cmd_control ddr3_cmd_ctrl_data = {
|
||||||
|
.cmd0csratio = K4B2G1646EBIH9_RATIO,
|
||||||
|
.cmd0dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
|
||||||
|
.cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
|
||||||
|
|
||||||
|
.cmd1csratio = K4B2G1646EBIH9_RATIO,
|
||||||
|
.cmd1dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
|
||||||
|
.cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
|
||||||
|
|
||||||
|
.cmd2csratio = K4B2G1646EBIH9_RATIO,
|
||||||
|
.cmd2dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
|
||||||
|
.cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct emif_regs ddr3_emif_reg_data = {
|
||||||
|
.sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
|
||||||
|
.ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
|
||||||
|
.sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
|
||||||
|
.sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
|
||||||
|
.sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
|
||||||
|
.zq_config = K4B2G1646EBIH9_ZQ_CFG,
|
||||||
|
.emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Early system init of muxing and clocks.
|
||||||
|
*/
|
||||||
|
void s_init(void)
|
||||||
|
{
|
||||||
|
/* WDT1 is already running when the bootloader gets control
|
||||||
|
* Disable it to avoid "random" resets
|
||||||
|
*/
|
||||||
|
writel(0xAAAA, &wdtimer->wdtwspr);
|
||||||
|
while (readl(&wdtimer->wdtwwps) != 0x0)
|
||||||
|
;
|
||||||
|
writel(0x5555, &wdtimer->wdtwspr);
|
||||||
|
while (readl(&wdtimer->wdtwwps) != 0x0)
|
||||||
|
;
|
||||||
|
|
||||||
|
#ifdef CONFIG_SPL_BUILD
|
||||||
|
/* Setup the PLLs and the clocks for the peripherals */
|
||||||
|
pll_init();
|
||||||
|
|
||||||
|
/* Enable RTC32K clock */
|
||||||
|
rtc32k_enable();
|
||||||
|
|
||||||
|
/* UART softreset */
|
||||||
|
u32 regval;
|
||||||
|
|
||||||
|
enable_uart0_pin_mux();
|
||||||
|
|
||||||
|
regval = readl(&uart_base->uartsyscfg);
|
||||||
|
regval |= UART_RESET;
|
||||||
|
writel(regval, &uart_base->uartsyscfg);
|
||||||
|
while ((readl(&uart_base->uartsyssts) &
|
||||||
|
UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
|
||||||
|
;
|
||||||
|
|
||||||
|
/* Disable smart idle */
|
||||||
|
regval = readl(&uart_base->uartsyscfg);
|
||||||
|
regval |= UART_SMART_IDLE_EN;
|
||||||
|
writel(regval, &uart_base->uartsyscfg);
|
||||||
|
|
||||||
|
gd = &gdata;
|
||||||
|
|
||||||
|
preloader_console_init();
|
||||||
|
|
||||||
|
/* Configure board pin mux */
|
||||||
|
enable_board_pin_mux();
|
||||||
|
|
||||||
|
config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
|
||||||
|
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Basic board specific setup. Pinmux has been handled already.
|
||||||
|
*/
|
||||||
|
int board_init(void)
|
||||||
|
{
|
||||||
|
gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
|
||||||
|
|
||||||
|
gpmc_init();
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined(CONFIG_DRIVER_TI_CPSW)
|
||||||
|
static void cpsw_control(int enabled)
|
||||||
|
{
|
||||||
|
/* VTP can be added here */
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct cpsw_slave_data cpsw_slaves[] = {
|
||||||
|
{
|
||||||
|
.slave_reg_ofs = 0x208,
|
||||||
|
.sliver_reg_ofs = 0xd80,
|
||||||
|
.phy_id = 0,
|
||||||
|
.phy_if = PHY_INTERFACE_MODE_RMII,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct cpsw_platform_data cpsw_data = {
|
||||||
|
.mdio_base = CPSW_MDIO_BASE,
|
||||||
|
.cpsw_base = CPSW_BASE,
|
||||||
|
.mdio_div = 0xff,
|
||||||
|
.channels = 8,
|
||||||
|
.cpdma_reg_ofs = 0x800,
|
||||||
|
.slaves = 1,
|
||||||
|
.slave_data = cpsw_slaves,
|
||||||
|
.ale_reg_ofs = 0xd00,
|
||||||
|
.ale_entries = 1024,
|
||||||
|
.host_port_reg_ofs = 0x108,
|
||||||
|
.hw_stats_reg_ofs = 0x900,
|
||||||
|
.mac_control = (1 << 5),
|
||||||
|
.control = cpsw_control,
|
||||||
|
.host_port_num = 0,
|
||||||
|
.version = CPSW_CTRL_VERSION_2,
|
||||||
|
};
|
||||||
|
|
||||||
|
int board_eth_init(bd_t *bis)
|
||||||
|
{
|
||||||
|
int rv, ret = 0;
|
||||||
|
uint8_t mac_addr[6];
|
||||||
|
uint32_t mac_hi, mac_lo;
|
||||||
|
|
||||||
|
if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
|
||||||
|
/* try reading mac address from efuse */
|
||||||
|
mac_lo = readl(&cdev->macid0l);
|
||||||
|
mac_hi = readl(&cdev->macid0h);
|
||||||
|
mac_addr[0] = mac_hi & 0xFF;
|
||||||
|
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
|
||||||
|
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
|
||||||
|
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
|
||||||
|
mac_addr[4] = mac_lo & 0xFF;
|
||||||
|
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
|
||||||
|
if (is_valid_ether_addr(mac_addr))
|
||||||
|
eth_setenv_enetaddr("ethaddr", mac_addr);
|
||||||
|
}
|
||||||
|
|
||||||
|
writel(RMII_MODE_ENABLE, &cdev->miisel);
|
||||||
|
|
||||||
|
rv = cpsw_register(&cpsw_data);
|
||||||
|
if (rv < 0)
|
||||||
|
printf("Error %d registering CPSW switch\n", rv);
|
||||||
|
else
|
||||||
|
ret += rv;
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
27
board/isee/igep0033/board.h
Normal file
27
board/isee/igep0033/board.h
Normal file
|
|
@ -0,0 +1,27 @@
|
||||||
|
/*
|
||||||
|
* IGEP COM AQUILA/CYGNUS boards information header
|
||||||
|
*
|
||||||
|
* Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _BOARD_H_
|
||||||
|
#define _BOARD_H_
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We must be able to enable uart0, for initial output. We then have a
|
||||||
|
* main pinmux function that can be overridden to enable all other pinmux that
|
||||||
|
* is required on the board.
|
||||||
|
*/
|
||||||
|
void enable_uart0_pin_mux(void);
|
||||||
|
void enable_board_pin_mux(void);
|
||||||
|
#endif
|
||||||
89
board/isee/igep0033/mux.c
Normal file
89
board/isee/igep0033/mux.c
Normal file
|
|
@ -0,0 +1,89 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation version 2.
|
||||||
|
*
|
||||||
|
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||||
|
* kind, whether express or implied; without even the implied warranty
|
||||||
|
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <asm/arch/sys_proto.h>
|
||||||
|
#include <asm/arch/hardware.h>
|
||||||
|
#include <asm/arch/mux.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <i2c.h>
|
||||||
|
#include "board.h"
|
||||||
|
|
||||||
|
static struct module_pin_mux uart0_pin_mux[] = {
|
||||||
|
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
|
||||||
|
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
|
||||||
|
{-1},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct module_pin_mux mmc0_pin_mux[] = {
|
||||||
|
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
|
||||||
|
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
|
||||||
|
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
|
||||||
|
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
|
||||||
|
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
|
||||||
|
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
|
||||||
|
{OFFSET(mcasp0_aclkx), (MODE(4) | RXACTIVE)}, /* MMC0_CD */
|
||||||
|
{-1},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct module_pin_mux nand_pin_mux[] = {
|
||||||
|
{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
|
||||||
|
{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
|
||||||
|
{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
|
||||||
|
{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
|
||||||
|
{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
|
||||||
|
{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
|
||||||
|
{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
|
||||||
|
{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
|
||||||
|
{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
|
||||||
|
{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
|
||||||
|
{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
|
||||||
|
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
|
||||||
|
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
|
||||||
|
{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
|
||||||
|
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
|
||||||
|
{-1},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct module_pin_mux rmii1_pin_mux[] = {
|
||||||
|
{OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
|
||||||
|
{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
|
||||||
|
{OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */
|
||||||
|
{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
|
||||||
|
{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
|
||||||
|
{OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
|
||||||
|
{OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
|
||||||
|
{OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REF_CLK */
|
||||||
|
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
|
||||||
|
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
|
||||||
|
{-1},
|
||||||
|
};
|
||||||
|
|
||||||
|
void enable_uart0_pin_mux(void)
|
||||||
|
{
|
||||||
|
configure_module_pin_mux(uart0_pin_mux);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Do board-specific muxes.
|
||||||
|
*/
|
||||||
|
void enable_board_pin_mux(void)
|
||||||
|
{
|
||||||
|
/* NAND Flash */
|
||||||
|
configure_module_pin_mux(nand_pin_mux);
|
||||||
|
/* SD Card */
|
||||||
|
configure_module_pin_mux(mmc0_pin_mux);
|
||||||
|
/* Ethernet pinmux. */
|
||||||
|
configure_module_pin_mux(rmii1_pin_mux);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -277,6 +277,7 @@ igep0020_nand arm armv7 igep00x0 isee
|
||||||
igep0030 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND
|
igep0030 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND
|
||||||
igep0030_nand arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND
|
igep0030_nand arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND
|
||||||
igep0032 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND
|
igep0032 arm armv7 igep00x0 isee omap3 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND
|
||||||
|
igep0033 arm armv7 igep0033 isee am33xx
|
||||||
am3517_evm arm armv7 am3517evm logicpd omap3
|
am3517_evm arm armv7 am3517evm logicpd omap3
|
||||||
mt_ventoux arm armv7 mt_ventoux teejet omap3
|
mt_ventoux arm armv7 mt_ventoux teejet omap3
|
||||||
omap3_zoom1 arm armv7 zoom1 logicpd omap3
|
omap3_zoom1 arm armv7 zoom1 logicpd omap3
|
||||||
|
|
|
||||||
284
include/configs/igep0033.h
Normal file
284
include/configs/igep0033.h
Normal file
|
|
@ -0,0 +1,284 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation version 2.
|
||||||
|
*
|
||||||
|
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||||
|
* kind, whether express or implied; without even the implied warranty
|
||||||
|
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CONFIG_IGEP0033_H
|
||||||
|
#define __CONFIG_IGEP0033_H
|
||||||
|
|
||||||
|
#define CONFIG_AM33XX
|
||||||
|
|
||||||
|
#include <asm/arch/omap.h>
|
||||||
|
|
||||||
|
/* Mach type */
|
||||||
|
#define MACH_TYPE_IGEP0033 4521 /* Until the next sync */
|
||||||
|
#define CONFIG_MACH_TYPE MACH_TYPE_IGEP0033
|
||||||
|
|
||||||
|
/* Clock defines */
|
||||||
|
#define V_OSCK 24000000 /* Clock output from T2 */
|
||||||
|
#define V_SCLK (V_OSCK)
|
||||||
|
|
||||||
|
/* DMA defines */
|
||||||
|
#define CONFIG_DMA_COHERENT
|
||||||
|
#define CONFIG_DMA_COHERENT_SIZE (1 << 20)
|
||||||
|
|
||||||
|
#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
|
||||||
|
#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
|
||||||
|
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||||
|
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
|
||||||
|
#define CONFIG_SYS_PROMPT "U-Boot# "
|
||||||
|
#define CONFIG_SYS_NO_FLASH
|
||||||
|
|
||||||
|
/* Display cpuinfo */
|
||||||
|
#define CONFIG_DISPLAY_CPUINFO
|
||||||
|
|
||||||
|
/* Commands to include */
|
||||||
|
#include <config_cmd_default.h>
|
||||||
|
|
||||||
|
#define CONFIG_CMD_ASKENV
|
||||||
|
#define CONFIG_CMD_BOOTZ
|
||||||
|
#define CONFIG_CMD_DHCP
|
||||||
|
#define CONFIG_CMD_ECHO
|
||||||
|
#define CONFIG_CMD_EXT4
|
||||||
|
#define CONFIG_CMD_FAT
|
||||||
|
#define CONFIG_CMD_FS_GENERIC
|
||||||
|
#define CONFIG_CMD_MMC
|
||||||
|
#define CONFIG_CMD_MTDPARTS
|
||||||
|
#define CONFIG_CMD_NAND
|
||||||
|
#define CONFIG_CMD_NET
|
||||||
|
#define CONFIG_CMD_PING
|
||||||
|
#define CONFIG_CMD_UBI
|
||||||
|
#define CONFIG_CMD_UBIFS
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Because the issues explained in doc/README.memory-test, the "mtest command
|
||||||
|
* is considered deprecated. It should not be enabled in most normal ports of
|
||||||
|
* U-Boot.
|
||||||
|
*/
|
||||||
|
#undef CONFIG_CMD_MEMTEST
|
||||||
|
|
||||||
|
#define CONFIG_BOOTDELAY 1 /* negative for no autoboot */
|
||||||
|
#define CONFIG_ENV_VARS_UBOOT_CONFIG
|
||||||
|
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||||
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||||
|
"loadaddr=0x80200000\0" \
|
||||||
|
"rdaddr=0x81000000\0" \
|
||||||
|
"bootfile=/boot/uImage\0" \
|
||||||
|
"console=ttyO0,115200n8\0" \
|
||||||
|
"optargs=\0" \
|
||||||
|
"mmcdev=0\0" \
|
||||||
|
"mmcroot=/dev/mmcblk0p2 rw\0" \
|
||||||
|
"mmcrootfstype=ext4 rootwait\0" \
|
||||||
|
"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
|
||||||
|
"ramrootfstype=ext2\0" \
|
||||||
|
"mmcargs=setenv bootargs console=${console} " \
|
||||||
|
"${optargs} " \
|
||||||
|
"root=${mmcroot} " \
|
||||||
|
"rootfstype=${mmcrootfstype}\0" \
|
||||||
|
"bootenv=uEnv.txt\0" \
|
||||||
|
"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
|
||||||
|
"importbootenv=echo Importing environment from mmc ...; " \
|
||||||
|
"env import -t $loadaddr $filesize\0" \
|
||||||
|
"ramargs=setenv bootargs console=${console} " \
|
||||||
|
"${optargs} " \
|
||||||
|
"root=${ramroot} " \
|
||||||
|
"rootfstype=${ramrootfstype}\0" \
|
||||||
|
"loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
|
||||||
|
"loaduimagefat=load mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
|
||||||
|
"loaduimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \
|
||||||
|
"mmcboot=echo Booting from mmc ...; " \
|
||||||
|
"run mmcargs; " \
|
||||||
|
"bootm ${loadaddr}\0" \
|
||||||
|
"ramboot=echo Booting from ramdisk ...; " \
|
||||||
|
"run ramargs; " \
|
||||||
|
"bootm ${loadaddr}\0" \
|
||||||
|
|
||||||
|
#define CONFIG_BOOTCOMMAND \
|
||||||
|
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||||
|
"echo SD/MMC found on device ${mmcdev};" \
|
||||||
|
"if run loadbootenv; then " \
|
||||||
|
"echo Loaded environment from ${bootenv};" \
|
||||||
|
"run importbootenv;" \
|
||||||
|
"fi;" \
|
||||||
|
"if test -n $uenvcmd; then " \
|
||||||
|
"echo Running uenvcmd ...;" \
|
||||||
|
"run uenvcmd;" \
|
||||||
|
"fi;" \
|
||||||
|
"if run loaduimage; then " \
|
||||||
|
"run mmcboot;" \
|
||||||
|
"fi;" \
|
||||||
|
"fi;" \
|
||||||
|
|
||||||
|
/* Max number of command args */
|
||||||
|
#define CONFIG_SYS_MAXARGS 16
|
||||||
|
|
||||||
|
/* Console I/O Buffer Size */
|
||||||
|
#define CONFIG_SYS_CBSIZE 512
|
||||||
|
|
||||||
|
/* Print Buffer Size */
|
||||||
|
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
|
||||||
|
+ sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||||
|
|
||||||
|
/* Boot Argument Buffer Size */
|
||||||
|
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||||
|
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
|
||||||
|
#define CONFIG_SYS_HZ 1000 /* 1ms clock */
|
||||||
|
|
||||||
|
/* Physical Memory Map */
|
||||||
|
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
|
||||||
|
#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
|
||||||
|
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
|
||||||
|
|
||||||
|
#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
|
||||||
|
#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
|
||||||
|
GENERATED_GBL_DATA_SIZE)
|
||||||
|
/* Platform/Board specific defs */
|
||||||
|
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
|
||||||
|
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
|
||||||
|
#define CONFIG_SYS_HZ 1000
|
||||||
|
|
||||||
|
/* NS16550 Configuration */
|
||||||
|
#define CONFIG_SYS_NS16550
|
||||||
|
#define CONFIG_SYS_NS16550_SERIAL
|
||||||
|
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||||
|
#define CONFIG_SYS_NS16550_CLK (48000000)
|
||||||
|
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
|
||||||
|
|
||||||
|
#define CONFIG_SERIAL_MULTI
|
||||||
|
#define CONFIG_CONS_INDEX 1
|
||||||
|
#define CONFIG_BAUDRATE 115200
|
||||||
|
|
||||||
|
#define CONFIG_ENV_OVERWRITE 1
|
||||||
|
#define CONFIG_SYS_CONSOLE_INFO_QUIET
|
||||||
|
|
||||||
|
/* MMC support */
|
||||||
|
#define CONFIG_MMC
|
||||||
|
#define CONFIG_GENERIC_MMC
|
||||||
|
#define CONFIG_OMAP_HSMMC
|
||||||
|
#define CONFIG_DOS_PARTITION
|
||||||
|
|
||||||
|
/* GPIO support */
|
||||||
|
#define CONFIG_OMAP_GPIO
|
||||||
|
|
||||||
|
/* Ethernet support */
|
||||||
|
#define CONFIG_DRIVER_TI_CPSW
|
||||||
|
#define CONFIG_MII
|
||||||
|
#define CONFIG_BOOTP_DEFAULT
|
||||||
|
#define CONFIG_BOOTP_DNS
|
||||||
|
#define CONFIG_BOOTP_DNS2
|
||||||
|
#define CONFIG_BOOTP_SEND_HOSTNAME
|
||||||
|
#define CONFIG_BOOTP_GATEWAY
|
||||||
|
#define CONFIG_BOOTP_SUBNETMASK
|
||||||
|
#define CONFIG_NET_RETRY_COUNT 10
|
||||||
|
#define CONFIG_NET_MULTI
|
||||||
|
#define CONFIG_PHYLIB
|
||||||
|
#define CONFIG_PHY_ADDR 0
|
||||||
|
#define CONFIG_PHY_SMSC
|
||||||
|
|
||||||
|
/* NAND support */
|
||||||
|
#define CONFIG_NAND
|
||||||
|
#define CONFIG_NAND_OMAP_GPMC
|
||||||
|
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
|
||||||
|
#define CONFIG_SYS_NAND_BASE (0x08000000) /* phys address CS0 */
|
||||||
|
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||||
|
#define CONFIG_SYS_NAND_ONFI_DETECTION 1
|
||||||
|
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
|
||||||
|
#define CONFIG_ENV_IS_IN_NAND
|
||||||
|
#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
|
||||||
|
|
||||||
|
#define CONFIG_MTD_PARTITIONS
|
||||||
|
#define CONFIG_MTD_DEVICE
|
||||||
|
#define CONFIG_RBTREE
|
||||||
|
#define CONFIG_LZO
|
||||||
|
|
||||||
|
#define MTDIDS_DEFAULT "nand0=nand"
|
||||||
|
#define MTDPARTS_DEFAULT "mtdparts=nand:512k(SPL),"\
|
||||||
|
"1m(U-Boot),128k(U-Boot Env),"\
|
||||||
|
"5m(Kernel),-(File System)"
|
||||||
|
|
||||||
|
/* Unsupported features */
|
||||||
|
#undef CONFIG_USE_IRQ
|
||||||
|
|
||||||
|
/* Defines for SPL */
|
||||||
|
#define CONFIG_SPL
|
||||||
|
#define CONFIG_SPL_FRAMEWORK
|
||||||
|
#define CONFIG_SPL_TEXT_BASE 0x402F0400
|
||||||
|
#define CONFIG_SPL_MAX_SIZE (101 * 1024)
|
||||||
|
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
|
||||||
|
|
||||||
|
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
|
||||||
|
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
|
||||||
|
|
||||||
|
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
|
||||||
|
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
|
||||||
|
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
|
||||||
|
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
|
||||||
|
#define CONFIG_SPL_MMC_SUPPORT
|
||||||
|
#define CONFIG_SPL_FAT_SUPPORT
|
||||||
|
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||||
|
#define CONFIG_SPL_LIBDISK_SUPPORT
|
||||||
|
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||||
|
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||||
|
#define CONFIG_SPL_GPIO_SUPPORT
|
||||||
|
#define CONFIG_SPL_YMODEM_SUPPORT
|
||||||
|
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
|
||||||
|
|
||||||
|
#define CONFIG_SPL_BOARD_INIT
|
||||||
|
#define CONFIG_SPL_NAND_AM33XX_BCH
|
||||||
|
#define CONFIG_SPL_NAND_SUPPORT
|
||||||
|
#define CONFIG_SPL_NAND_BASE
|
||||||
|
#define CONFIG_SPL_NAND_DRIVERS
|
||||||
|
#define CONFIG_SPL_NAND_ECC
|
||||||
|
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||||
|
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
|
||||||
|
CONFIG_SYS_NAND_PAGE_SIZE)
|
||||||
|
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
|
||||||
|
#define CONFIG_SYS_NAND_OOBSIZE 64
|
||||||
|
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
|
||||||
|
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||||
|
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||||
|
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||||
|
18, 19, 20, 21, 22, 23, 24, 25, \
|
||||||
|
26, 27, 28, 29, 30, 31, 32, 33, \
|
||||||
|
34, 35, 36, 37, 38, 39, 40, 41, \
|
||||||
|
42, 43, 44, 45, 46, 47, 48, 49, \
|
||||||
|
50, 51, 52, 53, 54, 55, 56, 57, }
|
||||||
|
|
||||||
|
#define CONFIG_SYS_NAND_ECCSIZE 512
|
||||||
|
#define CONFIG_SYS_NAND_ECCBYTES 14
|
||||||
|
|
||||||
|
#define CONFIG_SYS_NAND_ECCSTEPS 4
|
||||||
|
#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
|
||||||
|
CONFIG_SYS_NAND_ECCSTEPS)
|
||||||
|
|
||||||
|
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
|
||||||
|
|
||||||
|
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
|
||||||
|
|
||||||
|
/*
|
||||||
|
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
|
||||||
|
* 64 bytes before this address should be set aside for u-boot.img's
|
||||||
|
* header. That is 0x800FFFC0--0x80100000 should not be used for any
|
||||||
|
* other needs.
|
||||||
|
*/
|
||||||
|
#define CONFIG_SYS_TEXT_BASE 0x80800000
|
||||||
|
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
|
||||||
|
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Since SPL did pll and ddr initialization for us,
|
||||||
|
* we don't need to do it twice.
|
||||||
|
*/
|
||||||
|
#ifndef CONFIG_SPL_BUILD
|
||||||
|
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* ! __CONFIG_IGEP0033_H */
|
||||||
Loading…
Reference in a new issue