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Merge branch 'master' of git://git.denx.de/u-boot-x86

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This commit is contained in:
Tom Rini 2016-10-12 08:32:09 -04:00
commit 5ebd27d860
81 changed files with 662 additions and 530 deletions
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5
arch/x86/cpu/baytrail/valleyview.c
View file

@ -12,8 +12,9 @@
#include <asm/post.h>
static struct pci_device_id mmc_supported[] = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SDIO },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SD },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_EMMC2 },
{},
};

1
arch/x86/cpu/broadwell/sdram.c
View file

@ -291,7 +291,6 @@ void board_debug_uart_init(void)
static const struct udevice_id broadwell_syscon_ids[] = {
{ .compatible = "intel,me", .data = X86_SYSCON_ME },
{ .compatible = "intel,gma", .data = X86_SYSCON_GMA },
{ }
};

4
arch/x86/cpu/coreboot/Kconfig
View file

@ -8,8 +8,4 @@ config CBMEM_CONSOLE
bool
default y
config VIDEO_COREBOOT
bool
default y
endif

10
arch/x86/cpu/cpu.c
View file

@ -135,7 +135,7 @@ static void load_gdt(const u64 *boot_gdt, u16 num_entries)
struct gdt_ptr gdt;
gdt.len = (num_entries * X86_GDT_ENTRY_SIZE) - 1;
gdt.ptr = (u32)boot_gdt;
gdt.ptr = (ulong)boot_gdt;
asm volatile("lgdtl %0\n" : : "m" (gdt));
}
@ -630,13 +630,11 @@ static void build_pagetable(uint32_t *pgtable)
memset(pgtable, '\0', PAGETABLE_SIZE);
/* Level 4 needs a single entry */
pgtable[0] = (uint32_t)&pgtable[1024] + 7;
pgtable[0] = (ulong)&pgtable[1024] + 7;
/* Level 3 has one 64-bit entry for each GiB of memory */
for (i = 0; i < 4; i++) {
pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] +
0x1000 * i + 7;
}
for (i = 0; i < 4; i++)
pgtable[1024 + i * 2] = (ulong)&pgtable[2048] + 0x1000 * i + 7;
/* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
for (i = 0; i < 2048; i++)

9
arch/x86/cpu/interrupts.c
View file

@ -182,8 +182,8 @@ static inline void load_idt(const struct desc_ptr *dtr)
void set_vector(u8 intnum, void *routine)
{
idt[intnum].base_high = (u16)((u32)(routine) >> 16);
idt[intnum].base_low = (u16)((u32)(routine) & 0xffff);
idt[intnum].base_high = (u16)((ulong)(routine) >> 16);
idt[intnum].base_low = (u16)((ulong)(routine) & 0xffff);
}
/*
@ -238,8 +238,11 @@ int disable_interrupts(void)
{
long flags;
#ifdef CONFIG_X86_64
asm volatile ("pushfq ; popq %0 ; cli\n" : "=g" (flags) : );
#else
asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
#endif
return flags & X86_EFLAGS_IF;
}

1
arch/x86/cpu/ivybridge/Makefile
View file

@ -9,7 +9,6 @@ obj-y += fsp_configs.o ivybridge.o
else
obj-y += cpu.o
obj-y += early_me.o
obj-y += gma.o
obj-y += lpc.o
obj-y += model_206ax.o
obj-y += northbridge.o

12
arch/x86/cpu/ivybridge/bd82x6x.c
View file

@ -9,14 +9,12 @@
#include <fdtdec.h>
#include <malloc.h>
#include <pch.h>
#include <syscon.h>
#include <asm/cpu.h>
#include <asm/intel_regs.h>
#include <asm/io.h>
#include <asm/lapic.h>
#include <asm/lpc_common.h>
#include <asm/pci.h>
#include <asm/arch/bd82x6x.h>
#include <asm/arch/model_206ax.h>
#include <asm/arch/pch.h>
#include <asm/arch/sandybridge.h>
@ -155,22 +153,12 @@ void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,
static int bd82x6x_probe(struct udevice *dev)
{
struct udevice *gma_dev;
int ret;
if (!(gd->flags & GD_FLG_RELOC))
return 0;
/* Cause the SATA device to do its init */
uclass_first_device(UCLASS_AHCI, &dev);
ret = syscon_get_by_driver_data(X86_SYSCON_GMA, &gma_dev);
if (ret)
return ret;
ret = gma_func0_init(gma_dev);
if (ret)
return ret;
return 0;
}
#endif /* CONFIG_HAVE_FSP */

1
arch/x86/cpu/ivybridge/early_me.c
View file

@ -162,7 +162,6 @@ int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
static const struct udevice_id ivybridge_syscon_ids[] = {
{ .compatible = "intel,me", .data = X86_SYSCON_ME },
{ .compatible = "intel,gma", .data = X86_SYSCON_GMA },
{ }
};

156
arch/x86/cpu/ivybridge/gma.h
View file

@ -1,156 +0,0 @@
/*
* From Coreboot file of the same name
*
* Copyright (C) 2012 Chromium OS Authors
*
* SPDX-License-Identifier: GPL-2.0
*/
/* mailbox 0: header */
__packed struct opregion_header {
u8 signature[16];
u32 size;
u32 version;
u8 sbios_version[32];
u8 vbios_version[16];
u8 driver_version[16];
u32 mailboxes;
u8 reserved[164];
};
#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem"
#define IGD_OPREGION_VERSION 2
#define IGD_MBOX1 (1 << 0)
#define IGD_MBOX2 (1 << 1)
#define IGD_MBOX3 (1 << 2)
#define IGD_MBOX4 (1 << 3)
#define IGD_MBOX5 (1 << 4)
#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \
IGD_MBOX4 | IGD_MBOX5)
#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4)
#define SBIOS_VERSION_SIZE 32
/* mailbox 1: public acpi methods */
__packed struct opregion_mailbox1 {
u32 drdy;
u32 csts;
u32 cevt;
u8 reserved1[20];
u32 didl[8];
u32 cpdl[8];
u32 cadl[8];
u32 nadl[8];
u32 aslp;
u32 tidx;
u32 chpd;
u32 clid;
u32 cdck;
u32 sxsw;
u32 evts;
u32 cnot;
u32 nrdy;
u8 reserved2[60];
};
/* mailbox 2: software sci interface */
__packed struct opregion_mailbox2 {
u32 scic;
u32 parm;
u32 dslp;
u8 reserved[244];
};
/* mailbox 3: power conservation */
__packed struct opregion_mailbox3 {
u32 ardy;
u32 aslc;
u32 tche;
u32 alsi;
u32 bclp;
u32 pfit;
u32 cblv;
u16 bclm[20];
u32 cpfm;
u32 epfm;
u8 plut[74];
u32 pfmb;
u32 ccdv;
u32 pcft;
u8 reserved[94];
};
#define IGD_BACKLIGHT_BRIGHTNESS 0xff
#define IGD_INITIAL_BRIGHTNESS 0x64
#define IGD_FIELD_VALID (1 << 31)
#define IGD_WORD_FIELD_VALID (1 << 15)
#define IGD_PFIT_STRETCH 6
/* mailbox 4: vbt */
__packed struct {
u8 gvd1[7168];
} opregion_vbt_t;
/* IGD OpRegion */
__packed struct igd_opregion {
opregion_header_t header;
opregion_mailbox1_t mailbox1;
opregion_mailbox2_t mailbox2;
opregion_mailbox3_t mailbox3;
opregion_vbt_t vbt;
};
/* Intel Video BIOS (Option ROM) */
__packed struct optionrom_header {
u16 signature;
u8 size;
u8 reserved[21];
u16 pcir_offset;
u16 vbt_offset;
};
#define OPROM_SIGNATURE 0xaa55
__packed struct optionrom_pcir {
u32 signature;
u16 vendor;
u16 device;
u16 reserved1;
u16 length;
u8 revision;
u8 classcode[3];
u16 imagelength;
u16 coderevision;
u8 codetype;
u8 indicator;
u16 reserved2;
};
__packed struct optionrom_vbt {
u8 hdr_signature[20];
u16 hdr_version;
u16 hdr_size;
u16 hdr_vbt_size;
u8 hdr_vbt_checksum;
u8 hdr_reserved;
u32 hdr_vbt_datablock;
u32 hdr_aim[4];
u8 datahdr_signature[16];
u16 datahdr_version;
u16 datahdr_size;
u16 datahdr_datablocksize;
u8 coreblock_id;
u16 coreblock_size;
u16 coreblock_biossize;
u8 coreblock_biostype;
u8 coreblock_releasestatus;
u8 coreblock_hwsupported;
u8 coreblock_integratedhw;
u8 coreblock_biosbuild[4];
u8 coreblock_biossignon[155];
};
#define VBT_SIGNATURE 0x54425624

16
arch/x86/cpu/ivybridge/lpc.c
View file

@ -213,10 +213,10 @@ static int pch_power_options(struct udevice *pch)
dm_pci_read_config16(pch, 0x40, &pmbase);
pmbase &= 0xfffe;
writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node,
"intel,gpe0-enable", 0));
writew(pmbase + ALT_GP_SMI_EN, fdtdec_get_int(blob, node,
"intel,alt-gp-smi-enable", 0));
writel(fdtdec_get_int(blob, node, "intel,gpe0-enable", 0),
(ulong)pmbase + GPE0_EN);
writew(fdtdec_get_int(blob, node, "intel,alt-gp-smi-enable", 0),
(ulong)pmbase + ALT_GP_SMI_EN);
/* Set up power management block and determine sleep mode */
reg32 = inl(pmbase + 0x04); /* PM1_CNT */
@ -355,10 +355,10 @@ static void enable_clock_gating(struct udevice *pch)
reg16 |= (1 << 2) | (1 << 11);
dm_pci_write_config16(pch, GEN_PMCON_1, reg16);
pch_iobp_update(pch, 0xEB007F07, ~0UL, (1 << 31));
pch_iobp_update(pch, 0xEB004000, ~0UL, (1 << 7));
pch_iobp_update(pch, 0xEC007F07, ~0UL, (1 << 31));
pch_iobp_update(pch, 0xEC004000, ~0UL, (1 << 7));
pch_iobp_update(pch, 0xeb007f07, ~0U, 1 << 31);
pch_iobp_update(pch, 0xeb004000, ~0U, 1 << 7);
pch_iobp_update(pch, 0xec007f07, ~0U, 1 << 31);
pch_iobp_update(pch, 0xec004000, ~0U, 1 << 7);
reg32 = readl(RCB_REG(CG));
reg32 |= (1 << 31);

1
arch/x86/cpu/ivybridge/model_206ax.c
View file

@ -20,7 +20,6 @@
#include <asm/processor.h>
#include <asm/speedstep.h>
#include <asm/turbo.h>
#include <asm/arch/bd82x6x.h>
#include <asm/arch/model_206ax.h>
static void enable_vmx(void)

1
arch/x86/cpu/ivybridge/sata.c
View file

@ -12,7 +12,6 @@
#include <asm/pch_common.h>
#include <asm/pci.h>
#include <asm/arch/pch.h>
#include <asm/arch/bd82x6x.h>
DECLARE_GLOBAL_DATA_PTR;

1
arch/x86/dts/bayleybay.dts
View file

@ -14,6 +14,7 @@
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/include/ "coreboot_fb.dtsi"
/ {
model = "Intel Bayley Bay";

1
arch/x86/dts/broadwell_som-6896.dts
View file

@ -4,6 +4,7 @@
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/include/ "coreboot_fb.dtsi"
/ {
model = "Advantech SOM-6896";

1
arch/x86/dts/chromebook_link.dts
View file

@ -7,6 +7,7 @@
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/include/ "coreboot_fb.dtsi"
/ {
model = "Google Link";

1
arch/x86/dts/chromebook_samus.dts
View file

@ -7,6 +7,7 @@
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/include/ "coreboot_fb.dtsi"
/ {
model = "Google Samus";

1
arch/x86/dts/chromebox_panther.dts
View file

@ -4,6 +4,7 @@
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/include/ "coreboot_fb.dtsi"
/ {
model = "Google Panther";

5
arch/x86/dts/coreboot_fb.dtsi Normal file
View file

@ -0,0 +1,5 @@
/ {
coreboot-fb {
compatible = "coreboot-fb";
};
};

1
arch/x86/dts/minnowmax.dts
View file

@ -13,6 +13,7 @@
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/include/ "coreboot_fb.dtsi"
/ {
model = "Intel Minnowboard Max";

12
arch/x86/include/asm/arch-ivybridge/bd82x6x.h
View file

@ -1,12 +0,0 @@
/*
* Copyright (C) 2014 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_BD82X6X_H
#define _ASM_ARCH_BD82X6X_H
int gma_func0_init(struct udevice *dev);
#endif

3
arch/x86/include/asm/bootparam.h
View file

@ -63,6 +63,9 @@ struct setup_header {
__u32 payload_offset;
__u32 payload_length;
__u64 setup_data;
__u64 pref_address;
__u32 init_size;
__u32 handover_offset;
} __attribute__((packed));
struct sys_desc_table {

1
arch/x86/include/asm/cpu.h
View file

@ -53,7 +53,6 @@ enum {
enum {
X86_NONE,
X86_SYSCON_ME, /* Intel Management Engine */
X86_SYSCON_GMA, /* Intel Graphics Media Accelerator */
X86_SYSCON_PINCONF, /* Intel x86 pin configuration */
};

2
arch/x86/include/asm/init_helpers.h
View file

@ -9,7 +9,5 @@
#define _INIT_HELPERS_H_
int init_cache_f_r(void);
int init_bd_struct_r(void);
int init_func_spi(void);
#endif /* !_INIT_HELPERS_H_ */

2
arch/x86/include/asm/string.h
View file

@ -17,7 +17,7 @@ extern char * strchr(const char * s, int c);
#define __HAVE_ARCH_MEMCPY
extern void * memcpy(void *, const void *, __kernel_size_t);
#undef __HAVE_ARCH_MEMMOVE
#define __HAVE_ARCH_MEMMOVE
extern void * memmove(void *, const void *, __kernel_size_t);
#undef __HAVE_ARCH_MEMCHR

10
arch/x86/lib/init_helpers.c
View file

@ -30,13 +30,3 @@ int init_cache_f_r(void)
/* Initialise the CPU cache(s) */
return init_cache();
}
bd_t bd_data;
int init_bd_struct_r(void)
{
gd->bd = &bd_data;
memset(gd->bd, 0, sizeof(bd_t));
return 0;
}

8
arch/x86/lib/mrccache.c
View file

@ -198,11 +198,13 @@ int mrccache_get_region(struct udevice **devp, struct mrc_region *entry)
/* Find the flash chip within the SPI controller node */
node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH);
if (node < 0)
if (node < 0) {
debug("%s: Cannot find SPI flash\n", __func__);
return -ENOENT;
}
if (fdtdec_get_int_array(blob, node, "memory-map", reg, 2))
return -FDT_ERR_NOTFOUND;
return -EINVAL;
entry->base = reg[0];
/* Find the place where we put the MRC cache */
@ -211,7 +213,7 @@ int mrccache_get_region(struct udevice **devp, struct mrc_region *entry)
return -EPERM;
if (fdtdec_get_int_array(blob, mrc_node, "reg", reg, 2))
return -FDT_ERR_NOTFOUND;
return -EINVAL;
entry->offset = reg[0];
entry->length = reg[1];

161
arch/x86/lib/string.c
View file

@ -130,3 +130,164 @@ void *memcpy(void *dstpp, const void *srcpp, size_t len)
return dstpp;
}
void *memmove(void *dest, const void *src, size_t n)
{
int d0, d1, d2, d3, d4, d5;
char *ret = dest;
__asm__ __volatile__(
/* Handle more 16 bytes in loop */
"cmp $0x10, %0\n\t"
"jb 1f\n\t"
/* Decide forward/backward copy mode */
"cmp %2, %1\n\t"
"jb 2f\n\t"
/*
* movs instruction have many startup latency
* so we handle small size by general register.
*/
"cmp $680, %0\n\t"
"jb 3f\n\t"
/* movs instruction is only good for aligned case */
"mov %1, %3\n\t"
"xor %2, %3\n\t"
"and $0xff, %3\n\t"
"jz 4f\n\t"
"3:\n\t"
"sub $0x10, %0\n\t"
/* We gobble 16 bytes forward in each loop */
"3:\n\t"
"sub $0x10, %0\n\t"
"mov 0*4(%1), %3\n\t"
"mov 1*4(%1), %4\n\t"
"mov %3, 0*4(%2)\n\t"
"mov %4, 1*4(%2)\n\t"
"mov 2*4(%1), %3\n\t"
"mov 3*4(%1), %4\n\t"
"mov %3, 2*4(%2)\n\t"
"mov %4, 3*4(%2)\n\t"
"lea 0x10(%1), %1\n\t"
"lea 0x10(%2), %2\n\t"
"jae 3b\n\t"
"add $0x10, %0\n\t"
"jmp 1f\n\t"
/* Handle data forward by movs */
".p2align 4\n\t"
"4:\n\t"
"mov -4(%1, %0), %3\n\t"
"lea -4(%2, %0), %4\n\t"
"shr $2, %0\n\t"
"rep movsl\n\t"
"mov %3, (%4)\n\t"
"jmp 11f\n\t"
/* Handle data backward by movs */
".p2align 4\n\t"
"6:\n\t"
"mov (%1), %3\n\t"
"mov %2, %4\n\t"
"lea -4(%1, %0), %1\n\t"
"lea -4(%2, %0), %2\n\t"
"shr $2, %0\n\t"
"std\n\t"
"rep movsl\n\t"
"mov %3,(%4)\n\t"
"cld\n\t"
"jmp 11f\n\t"
/* Start to prepare for backward copy */
".p2align 4\n\t"
"2:\n\t"
"cmp $680, %0\n\t"
"jb 5f\n\t"
"mov %1, %3\n\t"
"xor %2, %3\n\t"
"and $0xff, %3\n\t"
"jz 6b\n\t"
/* Calculate copy position to tail */
"5:\n\t"
"add %0, %1\n\t"
"add %0, %2\n\t"
"sub $0x10, %0\n\t"
/* We gobble 16 bytes backward in each loop */
"7:\n\t"
"sub $0x10, %0\n\t"
"mov -1*4(%1), %3\n\t"
"mov -2*4(%1), %4\n\t"
"mov %3, -1*4(%2)\n\t"
"mov %4, -2*4(%2)\n\t"
"mov -3*4(%1), %3\n\t"
"mov -4*4(%1), %4\n\t"
"mov %3, -3*4(%2)\n\t"
"mov %4, -4*4(%2)\n\t"
"lea -0x10(%1), %1\n\t"
"lea -0x10(%2), %2\n\t"
"jae 7b\n\t"
/* Calculate copy position to head */
"add $0x10, %0\n\t"
"sub %0, %1\n\t"
"sub %0, %2\n\t"
/* Move data from 8 bytes to 15 bytes */
".p2align 4\n\t"
"1:\n\t"
"cmp $8, %0\n\t"
"jb 8f\n\t"
"mov 0*4(%1), %3\n\t"
"mov 1*4(%1), %4\n\t"
"mov -2*4(%1, %0), %5\n\t"
"mov -1*4(%1, %0), %1\n\t"
"mov %3, 0*4(%2)\n\t"
"mov %4, 1*4(%2)\n\t"
"mov %5, -2*4(%2, %0)\n\t"
"mov %1, -1*4(%2, %0)\n\t"
"jmp 11f\n\t"
/* Move data from 4 bytes to 7 bytes */
".p2align 4\n\t"
"8:\n\t"
"cmp $4, %0\n\t"
"jb 9f\n\t"
"mov 0*4(%1), %3\n\t"
"mov -1*4(%1, %0), %4\n\t"
"mov %3, 0*4(%2)\n\t"
"mov %4, -1*4(%2, %0)\n\t"
"jmp 11f\n\t"
/* Move data from 2 bytes to 3 bytes */
".p2align 4\n\t"
"9:\n\t"
"cmp $2, %0\n\t"
"jb 10f\n\t"
"movw 0*2(%1), %%dx\n\t"
"movw -1*2(%1, %0), %%bx\n\t"
"movw %%dx, 0*2(%2)\n\t"
"movw %%bx, -1*2(%2, %0)\n\t"
"jmp 11f\n\t"
/* Move data for 1 byte */
".p2align 4\n\t"
"10:\n\t"
"cmp $1, %0\n\t"
"jb 11f\n\t"
"movb (%1), %%cl\n\t"
"movb %%cl, (%2)\n\t"
".p2align 4\n\t"
"11:"
: "=&c" (d0), "=&S" (d1), "=&D" (d2),
"=r" (d3), "=r" (d4), "=r"(d5)
: "0" (n),
"1" (src),
"2" (dest)
: "memory");
return ret;
}

23
board/congatec/conga-qeval20-qa3-e3845/README Normal file
View file

@ -0,0 +1,23 @@
------------------------------
U-Boot console UART selection:
------------------------------
The U-Boot port for this congatec board currently supports two different
configurations (defconfig files). The only difference is the UART that
is used as the U-Boot console UART. The default defconfig file:
conga-qeval20-qa3-e3845_defconfig
provides this console on the UART0 which is provided via a Winbond
Super-IO chip connected on the congatec Qseven 2.0 evaluation carrier
board (conga-QEVAL). This UART is the one provided with a SubD9
connector on the mainboard (the low one). The 2nd defconfig file:
conga-qeval20-qa3-e3845-internal-uart_defconfig
provides the U-Boot console on the BayTrail internal legacy UART,
which is routed from the QSeven SoM to the X300 connector on the
baseboard. Here is called COM2. The baseboard already provides the
RS232 level shifters. So a TTL-USB UART adapter does not work in
this case. The signals need to get connected directly to the
RS232 level signals of the PC UART via some adapter cable.

3
common/board_f.c
View file

@ -911,9 +911,6 @@ static init_fnc_t init_sequence_f[] = {
console_init_f, /* stage 1 init of console */
#ifdef CONFIG_SANDBOX
sandbox_early_getopt_check,
#endif
#ifdef CONFIG_OF_CONTROL
fdtdec_prepare_fdt,
#endif
display_options, /* say that we are here */
display_text_info, /* show debugging info if required */

87
common/stdio.c
View file

@ -121,19 +121,87 @@ struct list_head* stdio_get_list(void)
return &(devs.list);
}
#ifdef CONFIG_DM_VIDEO
/**
* stdio_probe_device() - Find a device which provides the given stdio device
*
* This looks for a device of the given uclass which provides a particular
* stdio device. It is currently really only useful for UCLASS_VIDEO.
*
* Ultimately we want to be able to probe a device by its stdio name. At
* present devices register in their probe function (for video devices this
* is done in vidconsole_post_probe()) and we don't know what name they will
* use until they do so.
* TODO(sjg@chromium.org): We should be able to determine the name before
* probing, and probe the required device.
*
* @name: stdio device name (e.g. "vidconsole")
* id: Uclass ID of device to look for (e.g. UCLASS_VIDEO)
* @sdevp: Returns stdout device, if found, else NULL
* @return 0 if found, -ENOENT if no device found with that name, other -ve
* on other error
*/
static int stdio_probe_device(const char *name, enum uclass_id id,
struct stdio_dev **sdevp)
{
struct stdio_dev *sdev;
struct udevice *dev;
int seq, ret;
*sdevp = NULL;
seq = trailing_strtoln(name, NULL);
if (seq == -1)
ret = uclass_first_device_err(id, &dev);
else
ret = uclass_get_device_by_seq(id, seq, &dev);
if (ret) {
debug("No %s device for seq %d (%s)\n", uclass_get_name(id),
seq, name);
return ret;
}
/* The device should be be the last one registered */
sdev = list_empty(&devs.list) ? NULL :
list_last_entry(&devs.list, struct stdio_dev, list);
if (!sdev || strcmp(sdev->name, name)) {
debug("Device '%s' did not register with stdio as '%s'\n",
dev->name, name);
return -ENOENT;
}
*sdevp = sdev;
return 0;
}
#endif
struct stdio_dev* stdio_get_by_name(const char *name)
{
struct list_head *pos;
struct stdio_dev *dev;
struct stdio_dev *sdev;
if(!name)
return NULL;
list_for_each(pos, &(devs.list)) {
dev = list_entry(pos, struct stdio_dev, list);
if(strcmp(dev->name, name) == 0)
return dev;
sdev = list_entry(pos, struct stdio_dev, list);
if (strcmp(sdev->name, name) == 0)
return sdev;
}
#ifdef CONFIG_DM_VIDEO
/*
* We did not find a suitable stdio device. If there is a video
* driver with a name starting with 'vidconsole', we can try probing
* that in the hope that it will produce the required stdio device.
*
* This function is sometimes called with the entire value of
* 'stdout', which may include a list of devices separate by commas.
* Obviously this is not going to work, so we ignore that case. The
* call path in that case is console_init_r() -> search_device() ->
* stdio_get_by_name().
*/
if (!strncmp(name, "vidconsole", 10) && !strchr(name, ',') &&
!stdio_probe_device(name, UCLASS_VIDEO, &sdev))
return sdev;
#endif
return NULL;
}
@ -282,6 +350,16 @@ int stdio_add_devices(void)
#endif
#endif
#ifdef CONFIG_DM_VIDEO
/*
* If the console setting is not in environment variables then
* console_init_r() will not be calling iomux_doenv() (which calls
* search_device()). So we will not dynamically add devices by
* calling stdio_probe_device().
*
* So just probe all video devices now so that whichever one is
* required will be available.
*/
#ifndef CONFIG_SYS_CONSOLE_IS_IN_ENV
struct udevice *vdev;
# ifndef CONFIG_DM_KEYBOARD
int ret;
@ -293,6 +371,7 @@ int stdio_add_devices(void)
;
if (ret)
printf("%s: Video device failed (ret=%d)\n", __func__, ret);
#endif /* !CONFIG_SYS_CONSOLE_IS_IN_ENV */
#else
# if defined(CONFIG_LCD)
drv_lcd_init ();

1
configs/bayleybay_defconfig
View file

@ -53,6 +53,7 @@ CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y

2
configs/chromebook_link_defconfig
View file

@ -57,8 +57,10 @@ CONFIG_TPM_TIS_LPC=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_VIDEO_IVYBRIDGE_IGD=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TPM=y

1
configs/chromebox_panther_defconfig
View file

@ -49,6 +49,7 @@ CONFIG_TPM_TIS_LPC=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y

1
configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
View file

@ -61,6 +61,7 @@ CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_114=y

1
configs/conga-qeval20-qa3-e3845_defconfig
View file

@ -60,6 +60,7 @@ CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_114=y

2
configs/coreboot-x86_defconfig
View file

@ -40,5 +40,7 @@ CONFIG_TPM_TIS_LPC=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_COREBOOT=y
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TPM=y

1
configs/crownbay_defconfig
View file

@ -47,6 +47,7 @@ CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_USE_PRIVATE_LIBGCC=y

1
configs/dfi-bt700-q7x-151_defconfig
View file

@ -58,6 +58,7 @@ CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_114=y

1
configs/minnowmax_defconfig
View file

@ -57,6 +57,7 @@ CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y

1
configs/qemu-x86_defconfig
View file

@ -44,6 +44,7 @@ CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_111=y

1
configs/qemu-x86_efi_payload32_defconfig
View file

@ -41,6 +41,7 @@ CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_111=y

1
configs/qemu-x86_efi_payload64_defconfig
View file

@ -41,6 +41,7 @@ CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_111=y

1
configs/som-db5800-som-6867_defconfig
View file

@ -55,6 +55,7 @@ CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y

1
configs/theadorable-x86-dfi-bt700_defconfig
View file

@ -55,6 +55,7 @@ CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_114=y

9
doc/README.x86
View file

@ -381,10 +381,17 @@ To enable video you must enable these options in coreboot:
- Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5))
- Keep VESA framebuffer
And include coreboot_fb.dtsi in your board's device tree source file, like:
/include/ "coreboot_fb.dtsi"
At present it seems that for Minnowboard Max, coreboot does not pass through
the video information correctly (it always says the resolution is 0x0). This
works correctly for link though.
Note: coreboot framebuffer driver does not work on QEMU. The reason is unknown
at this point. Patches are welcome if you figure out anything wrong.
Test with QEMU for bare mode
----------------------------
QEMU is a fancy emulator that can enable us to test U-Boot without access to
@ -446,7 +453,7 @@ loading kernel to address 01000000 size 5d9d30 initrd 04000000 size 1b1ab50
Here the kernel (bzImage) is loaded to 01000000 and initrd is to 04000000. Then,
'zboot' can be used to boot the kernel:
=> zboot 02000000 - 04000000 1b1ab50
=> zboot 01000000 - 04000000 1b1ab50
CPU Microcode
-------------

2
drivers/bios_emulator/atibios.c
View file

@ -599,7 +599,7 @@ int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
if (clean_up) {
BE_exit();
if (vga_info->BIOSImage &&
(u32)(vga_info->BIOSImage) != 0xc0000)
(ulong)(vga_info->BIOSImage) != 0xc0000)
free(vga_info->BIOSImage);
free(vga_info);
vga_info = NULL;

9
drivers/core/uclass.c
View file

@ -148,6 +148,15 @@ int uclass_get(enum uclass_id id, struct uclass **ucp)
return 0;
}
const char *uclass_get_name(enum uclass_id id)
{
struct uclass *uc;
if (uclass_get(id, &uc))
return NULL;
return uc->uc_drv->name;
}
int uclass_find_device(enum uclass_id id, int index, struct udevice **devp)
{
struct uclass *uc;

7
drivers/gpio/intel_broadwell_gpio.c
View file

@ -9,6 +9,7 @@
#include <fdtdec.h>
#include <pch.h>
#include <pci.h>
#include <syscon.h>
#include <asm/cpu.h>
#include <asm/gpio.h>
#include <asm/io.h>
@ -118,6 +119,12 @@ static int broadwell_gpio_probe(struct udevice *dev)
struct broadwell_bank_platdata *plat = dev_get_platdata(dev);
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct broadwell_bank_priv *priv = dev_get_priv(dev);
struct udevice *pinctrl;
int ret;
/* Set up pin control if available */
ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &pinctrl);
debug("%s, pinctrl=%p, ret=%d\n", __func__, pinctrl, ret);
uc_priv->gpio_count = GPIO_PER_BANK;
uc_priv->bank_name = plat->bank_name;

6
drivers/i2c/intel_i2c.c
View file

@ -248,11 +248,11 @@ static int intel_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
static int intel_i2c_probe(struct udevice *dev)
{
struct intel_i2c *priv = dev_get_priv(dev);
u32 base;
ulong base;
/* Save base address from PCI BAR */
priv->base = (u32)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4,
PCI_REGION_IO);
priv->base = (ulong)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4,
PCI_REGION_IO);
base = priv->base;
/* Set SMBus enable. */

62
drivers/pci/pci_rom.c
View file

@ -31,6 +31,7 @@
#include <pci.h>
#include <pci_rom.h>
#include <vbe.h>
#include <video.h>
#include <video_fb.h>
#include <linux/screen_info.h>
@ -348,3 +349,64 @@ err:
free(ram);
return ret;
}
#ifdef CONFIG_DM_VIDEO
int vbe_setup_video_priv(struct vesa_mode_info *vesa,
struct video_priv *uc_priv,
struct video_uc_platdata *plat)
{
if (!vesa->x_resolution)
return -ENXIO;
uc_priv->xsize = vesa->x_resolution;
uc_priv->ysize = vesa->y_resolution;
switch (vesa->bits_per_pixel) {
case 32:
case 24:
uc_priv->bpix = VIDEO_BPP32;
break;
case 16:
uc_priv->bpix = VIDEO_BPP16;
break;
default:
return -EPROTONOSUPPORT;
}
plat->base = vesa->phys_base_ptr;
plat->size = vesa->bytes_per_scanline * vesa->y_resolution;
return 0;
}
int vbe_setup_video(struct udevice *dev, int (*int15_handler)(void))
{
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
int ret;
printf("Video: ");
/* If we are running from EFI or coreboot, this can't work */
if (!ll_boot_init()) {
printf("Not available (previous bootloader prevents it)\n");
return -EPERM;
}
bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
ret = dm_pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE |
PCI_ROM_ALLOW_FALLBACK);
bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
if (ret) {
debug("failed to run video BIOS: %d\n", ret);
return ret;
}
ret = vbe_setup_video_priv(&mode_info.vesa, uc_priv, plat);
if (ret) {
debug("No video mode configured\n");
return ret;
}
printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
mode_info.vesa.bits_per_pixel);
return 0;
}
#endif

2
drivers/rtc/mc146818.c
View file

@ -14,7 +14,7 @@
#include <dm.h>
#include <rtc.h>
#if defined(__I386__) || defined(CONFIG_MALTA)
#if defined(CONFIG_X86) || defined(CONFIG_MALTA)
#include <asm/io.h>
#define in8(p) inb(p)
#define out8(p, v) outb(v, p)

4
drivers/tpm/tpm_tis_lpc.c
View file

@ -204,7 +204,7 @@ static int tis_senddata(struct udevice *dev, const u8 *data, size_t len)
/* Wait till the device is ready to accept more data. */
while (!burst) {
if (max_cycles++ == MAX_DELAY_US) {
printf("%s:%d failed to feed %d bytes of %d\n",
printf("%s:%d failed to feed %zd bytes of %zd\n",
__FILE__, __LINE__, len - offset, len);
return -ETIMEDOUT;
}
@ -224,7 +224,7 @@ static int tis_senddata(struct udevice *dev, const u8 *data, size_t len)
* changes to zero exactly after the last byte is fed into the
* FIFO.
*/
count = min((u32)burst, len - offset - 1);
count = min((size_t)burst, len - offset - 1);
while (count--)
tpm_write_byte(priv, data[offset++],
&regs[locality].data);

4
drivers/usb/host/ehci-pci.c
View file

@ -32,8 +32,8 @@ static void ehci_pci_init(struct udevice *dev, struct ehci_hccr **ret_hccr,
hcor = (struct ehci_hcor *)((uintptr_t) hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
debug("EHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n",
(u32)hccr, (u32)hcor,
debug("EHCI-PCI init hccr %#lx and hcor %#lx hc_length %d\n",
(ulong)hccr, (ulong)hcor,
(u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
*ret_hccr = hccr;

23
drivers/video/Kconfig
View file

@ -101,6 +101,15 @@ config VIDCONSOLE_AS_LCD
to update the environment, the breakage may be confusing for users.
This option will be removed around the end of 2016.
config VIDEO_COREBOOT
bool "Enable coreboot framebuffer driver support"
depends on X86 && SYS_COREBOOT
help
Turn on this option to enable a framebuffer driver when U-Boot is
loaded by coreboot where the graphics device is configured by
coreboot already. This can in principle be used with any platform
that coreboot supports.
config VIDEO_VESA
bool "Enable VESA video driver support"
default n
@ -366,7 +375,19 @@ config VIDEO_BROADWELL_IGD
bool "Enable Intel Broadwell integrated graphics device"
depends on X86
help
This enabled support for integrated graphics on Intel broadwell
This enables support for integrated graphics on Intel broadwell
devices. Initialisation is mostly performed by a VGA boot ROM, with
some setup handled by U-Boot itself. The graphics adaptor works as
a VESA device and supports LCD panels, eDP and LVDS outputs.
Configuration of most aspects of device operation is performed using
a special tool which configures the VGA ROM, but the graphics
resolution can be selected in U-Boot.
config VIDEO_IVYBRIDGE_IGD
bool "Enable Intel Ivybridge integration graphics support"
depends on X86
help
This enables support for integrated graphics on Intel ivybridge
devices. Initialisation is mostly performed by a VGA boot ROM, with
some setup handled by U-Boot itself. The graphics adaptor works as
a VESA device and supports LCD panels, eDP and LVDS outputs.

5
drivers/video/Makefile
View file

@ -20,6 +20,7 @@ obj-$(CONFIG_CONSOLE_TRUETYPE) += console_truetype.o fonts/
endif
obj-$(CONFIG_VIDEO_BROADWELL_IGD) += broadwell_igd.o
obj-$(CONFIG_VIDEO_IVYBRIDGE_IGD) += ivybridge_igd.o
obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
@ -36,7 +37,7 @@ obj-$(CONFIG_S6E63D6) += s6e63d6.o
obj-$(CONFIG_LD9040) += ld9040.o
obj-$(CONFIG_SED156X) += sed156x.o
obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o
obj-$(CONFIG_VIDEO_COREBOOT) += coreboot_fb.o
obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o
obj-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o
obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
obj-$(CONFIG_VIDEO_IMX25LCDC) += imx25lcdc.o videomodes.o
@ -57,7 +58,7 @@ obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o videomodes.o
obj-$(CONFIG_VIDEO_TEGRA20) += tegra.o
obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
obj-$(CONFIG_VIDEO_VESA) += vesa_fb.o
obj-$(CONFIG_VIDEO_VESA) += vesa.o
obj-$(CONFIG_FORMIKE) += formike.o
obj-$(CONFIG_LG4573) += lg4573.o
obj-$(CONFIG_AM335X_LCD) += am335x-fb.o

39
drivers/video/broadwell_igd.c
View file

@ -9,10 +9,8 @@
#include <common.h>
#include <bios_emul.h>
#include <dm.h>
#include <pci_rom.h>
#include <vbe.h>
#include <video.h>
#include <video_fb.h>
#include <asm/cpu.h>
#include <asm/intel_regs.h>
#include <asm/io.h>
@ -20,11 +18,9 @@
#include <asm/arch/cpu.h>
#include <asm/arch/iomap.h>
#include <asm/arch/pch.h>
#include <linux/log2.h>
#include "i915_reg.h"
struct broadwell_igd_priv {
GraphicDevice ctfb;
u8 *regs;
};
@ -664,10 +660,7 @@ static int broadwell_igd_probe(struct udevice *dev)
{
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct broadwell_igd_priv *priv = dev_get_priv(dev);
bool is_broadwell;
GraphicDevice *gdev = &priv->ctfb;
int bits_per_pixel;
int ret;
if (!ll_boot_init()) {
@ -683,13 +676,9 @@ static int broadwell_igd_probe(struct udevice *dev)
debug("%s: is_broadwell=%d\n", __func__, is_broadwell);
ret = igd_pre_init(dev, is_broadwell);
if (!ret) {
ret = dm_pci_run_vga_bios(dev, broadwell_igd_int15_handler,
PCI_ROM_USE_NATIVE |
PCI_ROM_ALLOW_FALLBACK);
if (ret) {
printf("failed to run video BIOS: %d\n", ret);
ret = -EIO;
}
ret = vbe_setup_video(dev, broadwell_igd_int15_handler);
if (ret)
debug("failed to run video BIOS: %d\n", ret);
}
if (!ret)
ret = igd_post_init(dev, is_broadwell);
@ -697,13 +686,8 @@ static int broadwell_igd_probe(struct udevice *dev)
if (ret)
return ret;
if (vbe_get_video_info(gdev)) {
printf("No video mode configured\n");
return -ENXIO;
}
/* Use write-through for the graphics memory, 256MB */
ret = mtrr_add_request(MTRR_TYPE_WRTHROUGH, gdev->pciBase, 256 << 20);
/* Use write-combining for the graphics memory, 256MB */
ret = mtrr_add_request(MTRR_TYPE_WRCOMB, plat->base, 256 << 20);
if (!ret)
ret = mtrr_commit(true);
if (ret && ret != -ENOSYS) {
@ -711,17 +695,8 @@ static int broadwell_igd_probe(struct udevice *dev)
ret);
}
bits_per_pixel = gdev->gdfBytesPP * 8;
sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY,
bits_per_pixel);
printf("%s\n", gdev->modeIdent);
uc_priv->xsize = gdev->winSizeX;
uc_priv->ysize = gdev->winSizeY;
uc_priv->bpix = ilog2(bits_per_pixel);
plat->base = gdev->pciBase;
plat->size = gdev->memSize;
debug("fb=%x, size %x, display size=%d %d %d\n", gdev->pciBase,
gdev->memSize, uc_priv->xsize, uc_priv->ysize, uc_priv->bpix);
debug("fb=%lx, size %x, display size=%d %d %d\n", plat->base,
plat->size, uc_priv->xsize, uc_priv->ysize, uc_priv->bpix);
return 0;
}

79
drivers/video/coreboot.c Normal file
View file

@ -0,0 +1,79 @@
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <vbe.h>
#include <video.h>
#include <asm/arch/sysinfo.h>
static int save_vesa_mode(struct cb_framebuffer *fb,
struct vesa_mode_info *vesa)
{
/*
* If there is no framebuffer structure, bail out and keep
* running on the serial console.
*/
if (!fb)
return -ENXIO;
vesa->x_resolution = fb->x_resolution;
vesa->y_resolution = fb->y_resolution;
vesa->bits_per_pixel = fb->bits_per_pixel;
vesa->bytes_per_scanline = fb->bytes_per_line;
vesa->phys_base_ptr = fb->physical_address;
vesa->red_mask_size = fb->red_mask_size;
vesa->red_mask_pos = fb->red_mask_pos;
vesa->green_mask_size = fb->green_mask_size;
vesa->green_mask_pos = fb->green_mask_pos;
vesa->blue_mask_size = fb->blue_mask_size;
vesa->blue_mask_pos = fb->blue_mask_pos;
vesa->reserved_mask_size = fb->reserved_mask_size;
vesa->reserved_mask_pos = fb->reserved_mask_pos;
return 0;
}
static int coreboot_video_probe(struct udevice *dev)
{
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct cb_framebuffer *fb = lib_sysinfo.framebuffer;
struct vesa_mode_info *vesa = &mode_info.vesa;
int ret;
printf("Video: ");
/* Initialize vesa_mode_info structure */
ret = save_vesa_mode(fb, vesa);
if (ret)
goto err;
ret = vbe_setup_video_priv(vesa, uc_priv, plat);
if (ret)
goto err;
printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
vesa->bits_per_pixel);
return 0;
err:
printf("No video mode configured in coreboot!\n");
return ret;
}
static const struct udevice_id coreboot_video_ids[] = {
{ .compatible = "coreboot-fb" },
{ }
};
U_BOOT_DRIVER(coreboot_video) = {
.name = "coreboot_video",
.id = UCLASS_VIDEO,
.of_match = coreboot_video_ids,
.probe = coreboot_video_probe,
};

108
drivers/video/coreboot_fb.c
View file

@ -1,108 +0,0 @@
/*
* coreboot Framebuffer driver.
*
* Copyright (C) 2011 The Chromium OS authors
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/sysinfo.h>
#include <vbe.h>
#include <video_fb.h>
#include "videomodes.h"
/*
* The Graphic Device
*/
GraphicDevice ctfb;
static void save_vesa_mode(void)
{
struct vesa_mode_info *vesa = &mode_info.vesa;
struct cb_framebuffer *fb = lib_sysinfo.framebuffer;
vesa->x_resolution = fb->x_resolution;
vesa->y_resolution = fb->y_resolution;
vesa->bits_per_pixel = fb->bits_per_pixel;
vesa->bytes_per_scanline = fb->bytes_per_line;
vesa->phys_base_ptr = fb->physical_address;
vesa->red_mask_size = fb->red_mask_size;
vesa->red_mask_pos = fb->red_mask_pos;
vesa->green_mask_size = fb->green_mask_size;
vesa->green_mask_pos = fb->green_mask_pos;
vesa->blue_mask_size = fb->blue_mask_size;
vesa->blue_mask_pos = fb->blue_mask_pos;
vesa->reserved_mask_size = fb->reserved_mask_size;
vesa->reserved_mask_pos = fb->reserved_mask_pos;
}
static int parse_coreboot_table_fb(GraphicDevice *gdev)
{
struct cb_framebuffer *fb = lib_sysinfo.framebuffer;
/* If there is no framebuffer structure, bail out and keep
* running on the serial console.
*/
if (!fb)
return 0;
gdev->winSizeX = fb->x_resolution;
gdev->winSizeY = fb->y_resolution;
gdev->plnSizeX = fb->x_resolution;
gdev->plnSizeY = fb->y_resolution;
gdev->gdfBytesPP = fb->bits_per_pixel / 8;
switch (fb->bits_per_pixel) {
case 24:
gdev->gdfIndex = GDF_32BIT_X888RGB;
break;
case 16:
gdev->gdfIndex = GDF_16BIT_565RGB;
break;
default:
gdev->gdfIndex = GDF__8BIT_INDEX;
break;
}
gdev->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS;
gdev->pciBase = (unsigned int)fb->physical_address;
gdev->frameAdrs = (unsigned int)fb->physical_address;
gdev->memSize = fb->bytes_per_line * fb->y_resolution;
gdev->vprBase = (unsigned int)fb->physical_address;
gdev->cprBase = (unsigned int)fb->physical_address;
return 1;
}
void *video_hw_init(void)
{
GraphicDevice *gdev = &ctfb;
int bits_per_pixel;
printf("Video: ");
if (!parse_coreboot_table_fb(gdev)) {
printf("No video mode configured in coreboot!\n");
return NULL;
}
bits_per_pixel = gdev->gdfBytesPP * 8;
/* fill in Graphic device struct */
sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY,
bits_per_pixel);
printf("%s\n", gdev->modeIdent);
memset((void *)gdev->pciBase, 0,
gdev->winSizeX * gdev->winSizeY * gdev->gdfBytesPP);
/* Initialize vesa_mode_info structure */
save_vesa_mode();
return (void *)gdev;
}

77
arch/x86/cpu/ivybridge/gma.c → drivers/video/ivybridge_igd.c
View file

@ -1,7 +1,5 @@
/*
* From Coreboot file of the same name
*
* Copyright (C) 2011 Chromium OS Authors
* Copyright (C) 2016 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0
*/
@ -12,6 +10,7 @@
#include <errno.h>
#include <fdtdec.h>
#include <pci_rom.h>
#include <vbe.h>
#include <asm/intel_regs.h>
#include <asm/io.h>
#include <asm/mtrr.h>
@ -24,6 +23,7 @@ struct gt_powermeter {
u32 value;
};
/* These are magic values - unfortunately the meaning is unknown */
static const struct gt_powermeter snb_pm_gt1[] = {
{ 0xa200, 0xcc000000 },
{ 0xa204, 0x07000040 },
@ -294,33 +294,6 @@ static const struct gt_powermeter ivb_pm_gt2_35w[] = {
{ 0 }
};
/*
* Some vga option roms are used for several chipsets but they only have one
* PCI ID in their header. If we encounter such an option rom, we need to do
* the mapping ourselves.
*/
u32 map_oprom_vendev(u32 vendev)
{
u32 new_vendev = vendev;
switch (vendev) {
case 0x80860102: /* GT1 Desktop */
case 0x8086010a: /* GT1 Server */
case 0x80860112: /* GT2 Desktop */
case 0x80860116: /* GT2 Mobile */
case 0x80860122: /* GT2 Desktop >=1.3GHz */
case 0x80860126: /* GT2 Mobile >=1.3GHz */
case 0x80860156: /* IVB */
case 0x80860166: /* IVB */
/* Set to GT1 Mobile */
new_vendev = 0x80860106;
break;
}
return new_vendev;
}
static inline u32 gtt_read(void *bar, u32 reg)
{
return readl(bar + reg);
@ -539,7 +512,7 @@ static int gma_pm_init_pre_vbios(void *gtt_bar, int rev)
return 0;
}
int gma_pm_init_post_vbios(struct udevice *dev, int rev, void *gtt_bar)
static int gma_pm_init_post_vbios(struct udevice *dev, int rev, void *gtt_bar)
{
const void *blob = gd->fdt_blob;
int node = dev->of_offset;
@ -731,7 +704,8 @@ static int int15_handler(void)
return res;
}
void sandybridge_setup_graphics(struct udevice *dev, struct udevice *video_dev)
static void sandybridge_setup_graphics(struct udevice *dev,
struct udevice *video_dev)
{
u32 reg32;
u16 reg16;
@ -797,11 +771,8 @@ void sandybridge_setup_graphics(struct udevice *dev, struct udevice *video_dev)
writel(reg32, MCHBAR_REG(0x5418));
}
int gma_func0_init(struct udevice *dev)
static int gma_func0_init(struct udevice *dev)
{
#ifdef CONFIG_VIDEO
ulong start;
#endif
struct udevice *nbridge;
void *gtt_bar;
ulong base;
@ -835,16 +806,38 @@ int gma_func0_init(struct udevice *dev)
if (ret)
return ret;
#ifdef CONFIG_VIDEO
start = get_timer(0);
ret = dm_pci_run_vga_bios(dev, int15_handler,
PCI_ROM_USE_NATIVE | PCI_ROM_ALLOW_FALLBACK);
debug("BIOS ran in %lums\n", get_timer(start));
#endif
return rev;
}
static int bd82x6x_video_probe(struct udevice *dev)
{
void *gtt_bar;
int ret, rev;
rev = gma_func0_init(dev);
if (rev < 0)
return rev;
ret = vbe_setup_video(dev, int15_handler);
if (ret)
return ret;
/* Post VBIOS init */
gtt_bar = (void *)dm_pci_read_bar32(dev, 0);
ret = gma_pm_init_post_vbios(dev, rev, gtt_bar);
if (ret)
return ret;
return 0;
}
static const struct udevice_id bd82x6x_video_ids[] = {
{ .compatible = "intel,gma" },
{ }
};
U_BOOT_DRIVER(bd82x6x_video) = {
.name = "bd82x6x_video",
.id = UCLASS_VIDEO,
.of_match = bd82x6x_video_ids,
.probe = bd82x6x_video_probe,
};

34
drivers/video/vesa.c Normal file
View file

@ -0,0 +1,34 @@
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <pci.h>
#include <vbe.h>
static int vesa_video_probe(struct udevice *dev)
{
return vbe_setup_video(dev, NULL);
}
static const struct udevice_id vesa_video_ids[] = {
{ .compatible = "vesa-fb" },
{ }
};
U_BOOT_DRIVER(vesa_video) = {
.name = "vesa_video",
.id = UCLASS_VIDEO,
.of_match = vesa_video_ids,
.probe = vesa_video_probe,
};
static struct pci_device_id vesa_video_supported[] = {
{ PCI_DEVICE_CLASS(PCI_CLASS_DISPLAY_VGA << 8, ~0) },
{ },
};
U_BOOT_PCI_DEVICE(vesa_video, vesa_video_supported);

63
drivers/video/vesa_fb.c
View file

@ -1,63 +0,0 @@
/*
* VESA frame buffer driver
*
* Copyright (C) 2014 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <pci_rom.h>
#include <video_fb.h>
#include <vbe.h>
/*
* The Graphic Device
*/
GraphicDevice ctfb;
void *video_hw_init(void)
{
GraphicDevice *gdev = &ctfb;
struct udevice *dev;
int bits_per_pixel;
int ret;
printf("Video: ");
if (!ll_boot_init()) {
/*
* If we are running from EFI or coreboot, this driver can't
* work.
*/
printf("Not available (previous bootloader prevents it)\n");
return NULL;
}
if (vbe_get_video_info(gdev)) {
ret = dm_pci_find_class(PCI_CLASS_DISPLAY_VGA << 8, 0, &dev);
if (ret) {
printf("no card detected\n");
return NULL;
}
bootstage_start(BOOTSTAGE_ID_ACCUM_LCD, "vesa display");
ret = dm_pci_run_vga_bios(dev, NULL, PCI_ROM_USE_NATIVE |
PCI_ROM_ALLOW_FALLBACK);
bootstage_accum(BOOTSTAGE_ID_ACCUM_LCD);
if (ret) {
printf("failed to run video BIOS: %d\n", ret);
return NULL;
}
}
if (vbe_get_video_info(gdev)) {
printf("No video mode configured\n");
return NULL;
}
bits_per_pixel = gdev->gdfBytesPP * 8;
sprintf(gdev->modeIdent, "%dx%dx%d", gdev->winSizeX, gdev->winSizeY,
bits_per_pixel);
printf("%s\n", gdev->modeIdent);
debug("Frame buffer at %x\n", gdev->pciBase);
return (void *)gdev;
}

3
drivers/video/video-uclass.c
View file

@ -54,6 +54,9 @@ static ulong alloc_fb(struct udevice *dev, ulong *addrp)
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
ulong base, align, size;
if (!plat->size)
return 0;
align = plat->align ? plat->align : 1 << 20;
base = *addrp - plat->size;
base &= ~(align - 1);

2
include/_exports.h
View file

@ -13,7 +13,7 @@
EXPORT_FUNC(putc, void, putc, const char)
EXPORT_FUNC(puts, void, puts, const char *)
EXPORT_FUNC(printf, int, printf, const char*, ...)
#if defined(CONFIG_X86) || defined(CONFIG_PPC)
#if (defined(CONFIG_X86) && !defined(CONFIG_X86_64)) || defined(CONFIG_PPC)
EXPORT_FUNC(irq_install_handler, void, install_hdlr,
int, interrupt_handler_t, void*)

1
include/asm-generic/sections.h
View file

@ -82,6 +82,7 @@ extern ulong __data_end;
extern ulong __rel_dyn_start;
extern ulong __rel_dyn_end;
extern ulong __bss_end;
extern ulong _image_binary_end;
extern ulong _TEXT_BASE; /* code start */

6
include/configs/bayleybay.h
View file

@ -18,9 +18,9 @@
#define CONFIG_PCI_PNP
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga,usbkbd\0" \
"stdout=serial,vga\0" \
"stderr=serial,vga\0"
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \

4
include/configs/cougarcanyon2.h
View file

@ -27,8 +27,4 @@
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0x5ff000
/* Video is not supported for now */
#undef CONFIG_VIDEO
#undef CONFIG_CFB_CONSOLE
#endif /* __CONFIG_H */

4
include/configs/crownbay.h
View file

@ -22,8 +22,8 @@
#define CONFIG_PCI_PNP
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \
"stdout=serial,vga\0" \
"stderr=serial,vga\0"
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA}

2
include/configs/efi-x86.h
View file

@ -15,8 +15,6 @@
#undef CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_IS_NOWHERE
#undef CONFIG_VIDEO
#undef CONFIG_CFB_CONSOLE
#undef CONFIG_SCSI_AHCI
#undef CONFIG_SCSI
#undef CONFIG_INTEL_ICH6_GPIO

4
include/configs/galileo.h
View file

@ -31,10 +31,6 @@
#undef CONFIG_SCSI_AHCI
#undef CONFIG_SCSI
/* Video is not supported in Quark SoC */
#undef CONFIG_VIDEO
#undef CONFIG_CFB_CONSOLE
/* SD/MMC support */
#define CONFIG_MMC
#define CONFIG_SDHCI

6
include/configs/minnowmax.h
View file

@ -20,9 +20,9 @@
#define CONFIG_SMSC_LPC47M
#define CONFIG_PCI_PNP
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
"stdout=vga,serial\0" \
"stderr=vga,serial\0"
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,serial\0" \
"stdout=vidconsole,serial\0" \
"stderr=vidconsole,serial\0"
#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \

4
include/configs/qemu-x86.h
View file

@ -19,8 +19,8 @@
#define CONFIG_PCI_PNP
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd\0" \
"stdout=serial,vga\0" \
"stderr=serial,vga\0"
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
/*
* ATA/SATA support for QEMU x86 targets

6
include/configs/som-6896.h
View file

@ -27,9 +27,9 @@
#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga,usbkbd\0" \
"stdout=serial,vga\0" \
"stderr=serial,vga\0"
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0x00ff0000

6
include/configs/som-db5800-som-6867.h
View file

@ -19,9 +19,9 @@
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_PCI_PNP
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd,vga\0" \
"stdout=serial,vga\0" \
"stderr=serial,vga\0"
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \

6
include/configs/x86-chromebook.h
View file

@ -53,8 +53,8 @@
#define CONFIG_SYS_WHITE_ON_BLACK
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \
"stdout=vga,serial\0" \
"stderr=vga,serial\0"
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \
"stdout=vidconsole,serial\0" \
"stderr=vidconsole,serial\0"
#endif

5
include/configs/x86-common.h
View file

@ -130,11 +130,6 @@
/*-----------------------------------------------------------------------
* Video Configuration
*/
#define CONFIG_VIDEO
#define CONFIG_VIDEO_SW_CURSOR
#define VIDEO_FB_16BPP_WORD_SWAP
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_CFB_CONSOLE
#define CONFIG_CONSOLE_SCROLL_LINES 5
/*-----------------------------------------------------------------------

8
include/dm/uclass.h
View file

@ -118,6 +118,14 @@ struct uclass_driver {
*/
int uclass_get(enum uclass_id key, struct uclass **ucp);
/**
* uclass_get_name() - Get the name of a uclass driver
*
* @id: ID to look up
* @returns the name of the uclass driver for that ID, or NULL if none
*/
const char *uclass_get_name(enum uclass_id id);
/**
* uclass_get_device() - Get a uclass device based on an ID and index
*

6
include/elf.h
View file

@ -394,6 +394,12 @@ typedef struct {
Elf64_Xword r_info; /* index and type of relocation */
} Elf64_Rel;
typedef struct {
Elf64_Addr r_offset; /* Location at which to apply the action */
Elf64_Xword r_info; /* index and type of relocation */
Elf64_Sxword r_addend; /* Constant addend used to compute value */
} Elf64_Rela;
/* Extract relocation info - r_info */
#define ELF32_R_SYM(i) ((i) >> 8)
#define ELF32_R_TYPE(i) ((unsigned char) (i))

11
include/linux/list.h
View file

@ -337,6 +337,17 @@ static inline void list_splice_tail_init(struct list_head *list,
#define list_first_entry(ptr, type, member) \
list_entry((ptr)->next, type, member)
/**
* list_last_entry - get the last element from a list
* @ptr: the list head to take the element from.
* @type: the type of the struct this is embedded in.
* @member: the name of the list_struct within the struct.
*
* Note, that list is expected to be not empty.
*/
#define list_last_entry(ptr, type, member) \
list_entry((ptr)->prev, type, member)
/**
* list_for_each - iterate over a list
* @pos: the &struct list_head to use as a loop cursor.

5
include/pci_ids.h
View file

@ -2599,13 +2599,14 @@
#define PCI_DEVICE_ID_INTEL_I960 0x0960
#define PCI_DEVICE_ID_INTEL_I960RM 0x0962
#define PCI_DEVICE_ID_INTEL_CENTERTON_ILB 0x0c60
#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO 0x0f15
#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD 0x0f16
#define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15
#define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16
#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC 0x0f1c
#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IDE 0x0f20
#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IDE_ALT 0x0f21
#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA 0x0f22
#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT 0x0f23
#define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50
#define PCI_DEVICE_ID_INTEL_82541ER 0x1078
#define PCI_DEVICE_ID_INTEL_82541GI_LF 0x107c
#define PCI_DEVICE_ID_INTEL_82542 0x1000

6
include/vbe.h
View file

@ -106,5 +106,11 @@ extern struct vbe_mode_info mode_info;
struct graphic_device;
int vbe_get_video_info(struct graphic_device *gdev);
struct video_priv;
struct video_uc_platdata;
int vbe_setup_video_priv(struct vesa_mode_info *vesa,
struct video_priv *uc_priv,
struct video_uc_platdata *plat);
int vbe_setup_video(struct udevice *dev, int (*int15_handler)(void));
#endif

8
lib/strto.c
View file

@ -160,9 +160,11 @@ long trailing_strtoln(const char *str, const char *end)
if (!end)
end = str + strlen(str);
for (p = end - 1; p > str; p--) {
if (!isdigit(*p))
return simple_strtoul(p + 1, NULL, 10);
if (isdigit(end[-1])) {
for (p = end - 1; p > str; p--) {
if (!isdigit(*p))
return simple_strtoul(p + 1, NULL, 10);
}
}
return -1;