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boards: ls1088a: Add support of I2C driver model
DM_I2C_COMPAT is a compatibility layer that allows using the non-DM I2C API when DM_I2C is used.When DM_I2C_COMPAT is not enabled for compilation, a compilation error will be generated. This patch solves the problem that the i2c-related api of the ls1088a platform does not support dm. Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
Chuanhua Han
Prabhakar Kushwaha
parent
292370df1c
commit
5dd043a082
3 changed files with 151 additions and 2 deletions
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@ -374,7 +374,15 @@ int select_i2c_ch_pca9547(u8 ch)
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{
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int ret;
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#ifndef CONFIG_DM_I2C
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ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
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#else
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struct udevice *dev;
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ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
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if (!ret)
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ret = dm_i2c_write(dev, 0, &ch, 1);
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#endif
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if (ret) {
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puts("PCA: failed to select proper channel\n");
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return ret;
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@ -393,38 +401,89 @@ void board_retimer_init(void)
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/* Access to Control/Shared register */
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reg = 0x0;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
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#else
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struct udevice *dev;
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i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR, 1, &dev);
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dm_i2c_write(dev, 0xff, ®, 1);
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#endif
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/* Read device revision and ID */
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#ifndef CONFIG_DM_I2C
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i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
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#else
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dm_i2c_read(dev, 1, ®, 1);
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#endif
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debug("Retimer version id = 0x%x\n", reg);
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/* Enable Broadcast. All writes target all channel register sets */
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reg = 0x0c;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
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#else
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dm_i2c_write(dev, 0xff, ®, 1);
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#endif
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/* Reset Channel Registers */
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#ifndef CONFIG_DM_I2C
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i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
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#else
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dm_i2c_read(dev, 0, ®, 1);
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#endif
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reg |= 0x4;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
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#else
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dm_i2c_write(dev, 0, ®, 1);
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#endif
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/* Set data rate as 10.3125 Gbps */
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reg = 0x90;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
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#else
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dm_i2c_write(dev, 0x60, ®, 1);
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#endif
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reg = 0xb3;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
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#else
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dm_i2c_write(dev, 0x61, ®, 1);
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#endif
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reg = 0x90;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
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#else
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dm_i2c_write(dev, 0x62, ®, 1);
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#endif
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reg = 0xb3;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
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#else
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dm_i2c_write(dev, 0x63, ®, 1);
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#endif
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reg = 0xcd;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
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#else
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dm_i2c_write(dev, 0x64, ®, 1);
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#endif
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/* Select VCO Divider to full rate (000) */
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#ifndef CONFIG_DM_I2C
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i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
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#else
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dm_i2c_read(dev, 0x2F, ®, 1);
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#endif
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reg &= 0x0f;
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reg |= 0x70;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
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#else
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dm_i2c_write(dev, 0x2F, ®, 1);
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#endif
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#ifdef CONFIG_TARGET_LS1088AQDS
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/* Retimer is connected to I2C1_CH5 */
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@ -432,38 +491,88 @@ void board_retimer_init(void)
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/* Access to Control/Shared register */
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reg = 0x0;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
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#else
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i2c_get_chip_for_busnum(0, I2C_RETIMER_ADDR2, 1, &dev);
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dm_i2c_write(dev, 0xff, ®, 1);
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#endif
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/* Read device revision and ID */
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#ifndef CONFIG_DM_I2C
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i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1);
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#else
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dm_i2c_read(dev, 1, ®, 1);
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#endif
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debug("Retimer version id = 0x%x\n", reg);
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/* Enable Broadcast. All writes target all channel register sets */
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reg = 0x0c;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
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#else
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dm_i2c_write(dev, 0xff, ®, 1);
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#endif
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/* Reset Channel Registers */
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#ifndef CONFIG_DM_I2C
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i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
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#else
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dm_i2c_read(dev, 0, ®, 1);
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#endif
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reg |= 0x4;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
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#else
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dm_i2c_write(dev, 0, ®, 1);
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#endif
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/* Set data rate as 10.3125 Gbps */
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reg = 0x90;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1);
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#else
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dm_i2c_write(dev, 0x60, ®, 1);
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#endif
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reg = 0xb3;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1);
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#else
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dm_i2c_write(dev, 0x61, ®, 1);
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#endif
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reg = 0x90;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1);
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#else
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dm_i2c_write(dev, 0x62, ®, 1);
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#endif
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reg = 0xb3;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1);
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#else
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dm_i2c_write(dev, 0x63, ®, 1);
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#endif
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reg = 0xcd;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1);
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#else
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dm_i2c_write(dev, 0x64, ®, 1);
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#endif
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/* Select VCO Divider to full rate (000) */
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#ifndef CONFIG_DM_I2C
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i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
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#else
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dm_i2c_read(dev, 0x2F, ®, 1);
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#endif
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reg &= 0x0f;
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reg |= 0x70;
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#ifndef CONFIG_DM_I2C
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i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
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#else
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dm_i2c_write(dev, 0x2F, ®, 1);
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#endif
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#endif
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/*return the default channel*/
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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@ -500,16 +609,30 @@ int get_serdes_volt(void)
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u8 chan = PWM_CHANNEL0;
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/* Select the PAGE 0 using PMBus commands PAGE for VDD */
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#ifndef CONFIG_DM_I2C
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ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
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PMBUS_CMD_PAGE, 1, &chan, 1);
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#else
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struct udevice *dev;
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ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
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if (!ret)
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ret = dm_i2c_write(dev, PMBUS_CMD_PAGE,
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&chan, 1);
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#endif
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if (ret) {
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printf("VID: failed to select VDD Page 0\n");
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return ret;
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}
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/* Read the output voltage using PMBus command READ_VOUT */
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#ifndef CONFIG_DM_I2C
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ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
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PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
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#else
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dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);
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#endif
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if (ret) {
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printf("VID: failed to read the volatge\n");
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return ret;
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@ -525,8 +648,17 @@ int set_serdes_volt(int svdd)
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svdd & 0xFF, (svdd & 0xFF00) >> 8};
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/* Write the desired voltage code to the SVDD regulator */
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#ifndef CONFIG_DM_I2C
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ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
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PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
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#else
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struct udevice *dev;
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ret = i2c_get_chip_for_busnum(0, I2C_SVDD_MONITOR_ADDR, 1, &dev);
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if (!ret)
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ret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,
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(void *)&buff, 5);
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#endif
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if (ret) {
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printf("VID: I2C failed to write to the volatge regulator\n");
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return -1;
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@ -557,8 +689,18 @@ int set_serdes_volt(int svdd)
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printf("SVDD changing of RDB\n");
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/* Read the BRDCFG54 via CLPD */
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#ifndef CONFIG_DM_I2C
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ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
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QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
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#else
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struct udevice *dev;
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ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev);
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if (!ret)
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ret = dm_i2c_read(dev, QIXIS_BRDCFG4_OFFSET,
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(void *)&brdcfg4, 1);
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#endif
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if (ret) {
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printf("VID: I2C failed to read the CPLD BRDCFG4\n");
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return -1;
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@ -567,8 +709,14 @@ int set_serdes_volt(int svdd)
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brdcfg4 = brdcfg4 | 0x08;
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/* Write to the BRDCFG4 */
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#ifndef CONFIG_DM_I2C
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ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
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QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
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#else
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ret = dm_i2c_write(dev, QIXIS_BRDCFG4_OFFSET,
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(void *)&brdcfg4, 1);
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#endif
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if (ret) {
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debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
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return -1;
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@ -67,7 +67,10 @@
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
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/* I2C */
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#ifndef CONFIG_DM_I2C
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#define CONFIG_SYS_I2C
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#endif
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/* Serial Port */
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#define CONFIG_SYS_NS16550_SERIAL
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@ -269,9 +269,7 @@
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* RTC configuration
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*/
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#define RTC
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#define CONFIG_RTC_PCF8563 1
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
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#define CONFIG_CMD_DATE
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#endif
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/* EEPROM */
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