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imx: Add 2GB lpddr support for i.MX8MN Beacon EmbeddedWorks devkit.

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There is a second lpddr configuration with 2GB of RAM, but this requires
different RAM timings, so in addition to adding the timing file, a
separate defconfig is necessary.

Signed-off-by: Adam Ford <aford173@gmail.com>
This commit is contained in:
Adam Ford 2021-02-16 08:19:52 -06:00 committed by Stefano Babic
parent e8e2703a30
commit 5d9b166401
6 changed files with 1587 additions and 2 deletions
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4
board/beacon/imx8mn/Kconfig
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@ -13,6 +13,10 @@ config IMX8MN_FORCE_NOM_SOC
bool "Force to use nominal mode for SOC and ARM"
default n
config IMX8MN_BEACON_2GB_LPDDR
bool "Enable 2GB LPDDR"
default n
source "board/freescale/common/Kconfig"
endif

1
board/beacon/imx8mn/MAINTAINERS
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@ -4,3 +4,4 @@ S: Maintained
F: board/beacon/imx8mn/
F: include/configs/imx8mn_beacon.h
F: configs/imx8mn_beacon_defconfig
F: configs/imx8mn_beacon_2g_defconfig

7
board/beacon/imx8mn/Makefile
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@ -8,6 +8,9 @@ obj-y += imx8mn_beacon.o
obj-y += ../../freescale/common/
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o
ifdef CONFIG_IMX8MN_BEACON_2GB_LPDDR
obj-y += lpddr4_2g_timing.o
else
obj-y += lpddr4_timing.o
endif
endif

1440
board/beacon/imx8mn/lpddr4_2g_timing.c Normal file
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File diff suppressed because it is too large Load diff

133
configs/imx8mn_beacon_2g_defconfig Normal file
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@ -0,0 +1,133 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x44000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0x912000
CONFIG_TARGET_IMX8MN_BEACON=y
CONFIG_IMX8MN_BEACON_2GB_LPDDR=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_DEFAULT_DEVICE_TREE="imx8mn-beacon-kit"
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg"
CONFIG_DEFAULT_FDT_FILE="imx8mn-beacon-kit.dtb"
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot=> "
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_ERASEENV=y
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent interrupts"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=2
CONFIG_SYS_MMC_ENV_PART=2
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MN=y
CONFIG_CLK_IMX8MN=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x42800000
CONFIG_FASTBOOT_BUF_SIZE=0x40000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_MXC_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_PMIC_BD71837=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_BD71837=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RESET=y
CONFIG_DM_SERIAL=y
# CONFIG_SPL_DM_SERIAL is not set
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_DM_THERMAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
# CONFIG_SPL_DM_USB is not set
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_SDP_LOADADDR=0x0
CONFIG_OF_LIBFDT_OVERLAY=y

4
include/configs/imx8mn_beacon.h
View file

@ -126,7 +126,11 @@
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#if CONFIG_IS_ENABLED(IMX8MN_BEACON_2GB_LPDDR)
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#else
#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */
#endif
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR