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imx6ul/imx6ull: synchronise device trees with linux

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Synchronise device trees with linux v5.19-rc5.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
This commit is contained in:
Marcel Ziswiler 2022-07-21 15:27:30 +02:00 committed by Stefano Babic
parent 091a03f8f3
commit 5d7a95f499
26 changed files with 1695 additions and 944 deletions
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161
arch/arm/dts/imx6ul-14x14-evk.dtsi
View file

@ -3,10 +3,6 @@
// Copyright (C) 2015 Freescale Semiconductor, Inc.
/ {
aliases {
spi5 = &{/spi4};
};
chosen {
stdout-path = &uart1;
};
@ -34,6 +30,28 @@
enable-active-high;
};
reg_peri_3v3: regulator-peri-3v3 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_peri_3v3>;
regulator-name = "VPERI_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
/*
* If you want to want to make this dynamic please
* check schematics and test all affected peripherals:
*
* - sensors
* - ethernet phy
* - can
* - bluetooth
* - wm8960 audio codec
* - ov5640 camera
*/
regulator-always-on;
};
reg_can_3v3: regulator-can-3v3 {
compatible = "regulator-fixed";
regulator-name = "can-3v3";
@ -42,6 +60,28 @@
gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
};
sound-wm8960 {
compatible = "fsl,imx-audio-wm8960";
model = "wm8960-audio";
audio-cpu = <&sai2>;
audio-codec = <&codec>;
audio-asrc = <&asrc>;
hp-det-gpio = <&gpio5 4 0>;
audio-routing =
"Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Ext Spk", "SPK_LP",
"Ext Spk", "SPK_LN",
"Ext Spk", "SPK_RP",
"Ext Spk", "SPK_RN",
"LINPUT2", "Mic Jack",
"LINPUT3", "Mic Jack",
"RINPUT1", "AMIC",
"RINPUT2", "AMIC",
"Mic Jack", "MICB",
"AMIC", "MICB";
};
spi4 {
compatible = "spi-gpio";
pinctrl-names = "default";
@ -49,7 +89,7 @@
status = "okay";
gpio-sck = <&gpio5 11 0>;
gpio-mosi = <&gpio5 10 0>;
cs-gpios = <&gpio5 7 0>;
cs-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
num-chipselects = <1>;
#address-cells = <1>;
#size-cells = <0>;
@ -61,6 +101,7 @@
reg = <0>;
registers-number = <1>;
spi-max-frequency = <100000>;
enable-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
};
};
@ -82,7 +123,7 @@
};
&i2c2 {
clock_frequency = <100000>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
@ -92,6 +133,45 @@
compatible = "wlf,wm8960";
reg = <0x1a>;
wlf,shared-lrclk;
wlf,hp-cfg = <3 2 3>;
wlf,gpio-cfg = <1 3>;
clocks = <&clks IMX6UL_CLK_SAI2>;
clock-names = "mclk";
};
camera@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_camera_clock>;
clocks = <&clks IMX6UL_CLK_CSI>;
clock-names = "xclk";
powerdown-gpios = <&gpio_spi 6 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio_spi 5 GPIO_ACTIVE_LOW>;
port {
ov5640_to_parallel: endpoint {
remote-endpoint = <&parallel_from_ov5640>;
bus-width = <8>;
data-shift = <2>; /* lines 9:2 are used */
hsync-active = <0>;
vsync-active = <0>;
pclk-sample = <1>;
};
};
};
};
&csi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_csi1>;
status = "okay";
port {
parallel_from_ov5640: endpoint {
remote-endpoint = <&ov5640_to_parallel>;
bus-type = <5>; /* Parallel bus */
};
};
};
@ -100,6 +180,7 @@
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
phy-supply = <&reg_peri_3v3>;
status = "okay";
};
@ -108,6 +189,7 @@
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
phy-supply = <&reg_peri_3v3>;
status = "okay";
mdio {
@ -115,13 +197,16 @@
#size-cells = <0>;
ethphy0: ethernet-phy@2 {
compatible = "ethernet-phy-id0022.1560";
reg = <2>;
micrel,led-mode = <1>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0022.1560";
reg = <1>;
micrel,led-mode = <1>;
clocks = <&clks IMX6UL_CLK_ENET2_REF>;
@ -144,18 +229,33 @@
status = "okay";
};
&gpio_spi {
eth0-phy-hog {
gpio-hog;
gpios = <1 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "eth0-phy";
};
eth1-phy-hog {
gpio-hog;
gpios = <2 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "eth1-phy";
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
status = "okay";
mag3110@e {
magnetometer@e {
compatible = "fsl,mag3110";
reg = <0x0e>;
vdd-supply = <&reg_peri_3v3>;
vddio-supply = <&reg_peri_3v3>;
};
};
@ -175,6 +275,7 @@
};
&pwm1 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
@ -185,13 +286,13 @@
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
flash0: n25q256a@0 {
flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q256a";
compatible = "micron,n25q256a", "jedec,spi-nor";
spi-max-frequency = <29000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
spi-tx-bus-width = <1>;
reg = <0>;
};
};
@ -211,6 +312,10 @@
status = "okay";
};
&snvs_pwrkey {
status = "okay";
};
&tsc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
@ -235,6 +340,8 @@
&usbotg1 {
dr_mode = "otg";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1>;
status = "okay";
};
@ -283,9 +390,14 @@
&iomuxc {
pinctrl-names = "default";
pinctrl_csi1: csi1grp {
pinctrl_camera_clock: cameraclockgrp {
fsl,pins = <
MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
>;
};
pinctrl_csi1: csi1grp {
fsl,pins = <
MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
@ -349,13 +461,6 @@
>;
};
pinctrl_i2c1_gpio: i2c1grp_gpio {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
@ -425,6 +530,12 @@
>;
};
pinctrl_peri_3v3: peri3v3grp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
@ -476,6 +587,12 @@
>;
};
pinctrl_usb_otg1: usbotg1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059

363
arch/arm/dts/imx6ul-geam.dts
View file

@ -1,43 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
@ -47,22 +11,129 @@
#include "imx6ul.dtsi"
/ {
model = "Engicam GEAM6UL";
model = "Engicam GEAM6UL Starter Kit";
compatible = "engicam,imx6ul-geam", "fsl,imx6ul";
memory {
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x08000000>;
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm8 0 100000>;
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <100>;
};
chosen {
stdout-path = &uart1;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "imx6ul-geam-sgtl5000";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&dailink_master>;
simple-audio-card,frame-master = <&dailink_master>;
simple-audio-card,widgets =
"Microphone", "Mic Jack",
"Line", "Line In",
"Line", "Line Out",
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
simple-audio-card,cpu {
sound-dai = <&sai2>;
};
dailink_master: simple-audio-card,codec {
sound-dai = <&sgtl5000>;
clocks = <&clks IMX6UL_CLK_SAI2>;
};
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_3p3v>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_3p3v>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
status = "okay";
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
};
@ -71,21 +142,105 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
#sound-dai-cells = <0>;
clocks = <&clks IMX6UL_CLK_OSC>;
clock-names = "mclk";
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
VDDD-supply = <&reg_1p8v>;
};
};
&i2c2 {
clock_frequency = <100000>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat
&pinctrl_lcdif_ctrl>;
display = <&display0>;
status = "okay";
display0: display0 {
bits-per-pixel = <16>;
bus-width = <18>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <28000000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <30>;
hback-porch = <30>;
hsync-len = <64>;
vback-porch = <5>;
vfront-porch = <5>;
vsync-len = <20>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&pwm8 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm8>;
status = "okay";
};
&tsc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
};
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
status = "okay";
};
&tsc {
measure-delay-time = <0x1ffff>;
pre-charge-time = <0x1fff>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbotg1 {
dr_mode = "peripheral";
status = "okay";
};
&usbotg2 {
dr_mode = "host";
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
@ -100,8 +255,6 @@
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
@ -112,6 +265,55 @@
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* ENET_nRST */
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x4001b031
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
@ -126,6 +328,63 @@
>;
};
pinctrl_lcdif_ctrl: lcdifctrlgrp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
>;
};
pinctrl_lcdif_dat: lcdifdatgrp {
fsl,pins = <
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
>;
};
pinctrl_pwm8: pwm8grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
>;
};
pinctrl_tsc: tscgrp {
fsl,pin = <
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0
MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x4001b031
MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
@ -133,6 +392,15 @@
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
@ -165,4 +433,15 @@
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17070
MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x10070
MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17070
MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17070
MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17070
MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17070
>;
};
};

148
arch/arm/dts/imx6ul-imx6ull-opos6ul.dtsi Normal file
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@ -0,0 +1,148 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
//
// Copyright 2019 Armadeus Systems <support@armadeus.com>
/ {
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0>; /* will be filled by U-Boot */
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
usdhc3_pwrseq: usdhc3-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-reset-duration = <1>;
phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
phy-handle = <&ethphy1>;
phy-supply = <&reg_3v3>;
status = "okay";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&gpio4>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
};
};
};
/* Bluetooth */
&uart8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart8>;
uart-has-rtscts;
status = "okay";
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <8>;
no-1-8-v;
non-removable;
status = "okay";
};
/* WiFi */
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>;
no-1-8-v;
non-removable;
mmc-pwrseq = <&usdhc3_pwrseq>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio2>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "host-wake";
};
};
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x130b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x130b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x130b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x130b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
/* INT# */
MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0
/* RST# */
MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x130b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
>;
};
pinctrl_uart8: uart8grp {
fsl,pins = <
MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x1b0b0
/* BT_REG_ON */
MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x130b0
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x1b0b0
MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x100b0
MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x1b0b0
MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x1b0b0
MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x1b0b0
MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x1b0b0
/* WL_REG_ON */
MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x130b0
/* WL_IRQ */
MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0
>;
};
};

327
arch/arm/dts/imx6ul-imx6ull-opos6uldev.dtsi Normal file
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@ -0,0 +1,327 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
//
// Copyright 2019 Armadeus Systems <support@armadeus.com>
/ {
chosen {
stdout-path = &uart1;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 191000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
power-supply = <&reg_5v>;
status = "okay";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
user-button {
label = "User button";
gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
linux,code = <BTN_MISC>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
user-led {
label = "User";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
onewire {
compatible = "w1-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_w1>;
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
};
panel: panel {
compatible = "armadeus,st0700-adapt";
power-supply = <&reg_3v3>;
backlight = <&backlight>;
port {
panel_in: endpoint {
remote-endpoint = <&lcdif_out>;
};
};
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usbotg1_vbus: regulator-usbotg1vbus {
compatible = "regulator-fixed";
regulator-name = "usbotg1vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1_vbus>;
gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usbotg2_vbus: regulator-usbotg2vbus {
compatible = "regulator-fixed";
regulator-name = "usbotg2vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg2_vbus>;
gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&adc1 {
vref-supply = <&reg_3v3>;
status = "okay";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_5v>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_5v>;
status = "okay";
};
&ecspi4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clock-frequency = <400000>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clock-frequency = <400000>;
status = "okay";
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif>;
status = "okay";
port {
lcdif_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
&pwm3 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&snvs_pwrkey {
status = "disabled";
};
&tsc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
measure-delay-time = <0xffff>;
pre-charge-time = <0xffff>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1_id>;
vbus-supply = <&reg_usbotg1_vbus>;
dr_mode = "otg";
disable-over-current;
status = "okay";
};
&usbotg2 {
vbus-supply = <&reg_usbotg2_vbus>;
dr_mode = "host";
disable-over-current;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpios>;
pinctrl_ecspi4: ecspi4grp {
fsl,pins = <
MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x1b0b0
MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x1b0b0
MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x1b0b0
MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x1b0b0
MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x1b0b0
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0
>;
};
pinctrl_gpios: gpiosgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0b0b0
MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x0b0b0
MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x0b0b0
MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0b0b0
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x0b0b0
MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0b0b0
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0b0b0
MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x0b0b0
>;
};
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <
MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
>;
};
pinctrl_lcdif: lcdifgrp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x100b1
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x100b1
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x100b1
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x100b1
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x100b1
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x100b1
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x100b1
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x100b1
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x100b1
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x100b1
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x100b1
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x100b1
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x100b1
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x100b1
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x100b1
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x100b1
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x100b1
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x100b1
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x100b1
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x100b1
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x100b1
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x100b1
>;
};
pinctrl_led: ledgrp {
fsl,pins = <
MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6UL_PAD_NAND_ALE__PWM3_OUT 0x1b0b0
>;
};
pinctrl_tsc: tscgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
>;
};
pinctrl_usbotg1_id: usbotg1idgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x1b0b0
>;
};
pinctrl_usbotg1_vbus: usbotg1vbusgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1b0b0
>;
};
};

42
arch/arm/dts/imx6ul-isiot-emmc.dts
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@ -1,56 +1,18 @@
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6ul.dtsi"
#include "imx6ul-isiot.dtsi"
/ {
model = "Engicam Is.IoT MX6UL eMMC Starterkit";
model = "Engicam Is.IoT MX6UL eMMC Starter kit";
compatible = "engicam,imx6ul-isiot", "fsl,imx6ul";
};
&usdhc2 {
u-boot,dm-spl;
status = "okay";
};

45
arch/arm/dts/imx6ul-isiot-nand.dts
View file

@ -1,51 +1,18 @@
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6ul.dtsi"
#include "imx6ul-isiot.dtsi"
/ {
model = "Engicam Is.IoT MX6UL NAND Starterkit";
model = "Engicam Is.IoT MX6UL NAND Starter kit";
compatible = "engicam,imx6ul-isiot", "fsl,imx6ul";
};
&gpmi {
status = "okay";
};

330
arch/arm/dts/imx6ul-isiot.dtsi
View file

@ -1,63 +1,108 @@
// SPDX-License-Identifier: GPL-2.0 OR X11
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx6ul.dtsi"
/ {
memory {
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
chosen {
stdout-path = &uart1;
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm8 0 100000>;
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <100>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "imx6ul-isiot-sgtl5000";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&dailink_master>;
simple-audio-card,frame-master = <&dailink_master>;
simple-audio-card,widgets =
"Microphone", "Mic Jack",
"Line", "Line In",
"Line", "Line Out",
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
simple-audio-card,cpu {
sound-dai = <&sai2>;
};
dailink_master: simple-audio-card,codec {
sound-dai = <&sgtl5000>;
clocks = <&clks IMX6UL_CLK_SAI2>;
};
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "disabled";
};
&i2c1 {
@ -65,15 +110,95 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
sgtl5000: codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
#sound-dai-cells = <0>;
clocks = <&clks IMX6UL_CLK_OSC>;
clock-names = "mclk";
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
VDDD-supply = <&reg_1p8v>;
};
stmpe811: gpio-expander@44 {
compatible = "st,stmpe811";
reg = <0x44>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_stmpe>;
interrupt-parent = <&gpio1>;
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
stmpe: touchscreen {
compatible = "st,stmpe-ts";
st,sample-time = <4>;
st,mod-12b = <1>;
st,ref-sel = <0>;
st,adc-freq = <1>;
st,ave-ctrl = <1>;
st,touch-det-delay = <2>;
st,settling = <2>;
st,fraction-z = <7>;
st,i-drive = <1>;
};
};
};
&i2c2 {
clock_frequency = <100000>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat
&pinctrl_lcdif_ctrl>;
display = <&display0>;
status = "okay";
display0: display0 {
bits-per-pixel = <16>;
bus-width = <18>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <28000000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <30>;
hback-porch = <30>;
hsync-len = <64>;
vback-porch = <5>;
vfront-porch = <5>;
vsync-len = <20>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&pwm8 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm8>;
status = "okay";
};
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
@ -81,8 +206,10 @@
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
bus-width = <4>;
no-1-8-v;
@ -101,16 +228,36 @@
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x1b0b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x1b0b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
>;
};
@ -122,9 +269,63 @@
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
fsl,pins = <
MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0
MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0
>;
};
pinctrl_lcdif_ctrl: lcdifctrlgrp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
>;
};
pinctrl_lcdif_dat: lcdifdatgrp {
fsl,pins = <
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
>;
};
pinctrl_pwm8: pwm8grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0
MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x4001b031
MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0
>;
};
pinctrl_stmpe: stmpegrp {
fsl,pins = <
MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0
>;
};
@ -146,8 +347,29 @@
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
>;
};
pinctrl_usdhc2: usdhc2grp {
u-boot,dm-spl;
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17070
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x10070

20
arch/arm/dts/imx6ul-kontron-n6x1x-s.dtsi
View file

@ -84,7 +84,7 @@
};
&ecspi1 {
cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
@ -153,6 +153,7 @@
};
&pwm8 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm8>;
status = "okay";
@ -177,7 +178,7 @@
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
fsl,uart-has-rtscts;
uart-has-rtscts;
status = "okay";
};
@ -214,7 +215,6 @@
wakeup-source;
vmmc-supply = <&reg_3v3>;
voltage-ranges = <3300 3300>;
bus-width = <4>;
no-1-8-v;
status = "okay";
};
@ -229,18 +229,10 @@
wakeup-source;
vmmc-supply = <&reg_3v3>;
voltage-ranges = <3300 3300>;
bus-width = <4>;
no-1-8-v;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
@ -411,10 +403,4 @@
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0
>;
};
};

30
arch/arm/dts/imx6ul-kontron-n6x1x-som-common.dtsi
View file

@ -11,20 +11,15 @@
chosen {
stdout-path = &uart4;
};
memory@80000000 {
reg = <0x80000000 0x10000000>;
device_type = "memory";
};
};
&ecspi2 {
cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
spi-flash@0 {
flash@0 {
compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
@ -60,16 +55,13 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
};
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
spi-max-frequency = <104000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
reg = <0>;
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
@ -121,4 +113,10 @@
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x18b0
>;
};
};

1
arch/arm/dts/imx6ul-litesom.dtsi
View file

@ -48,6 +48,7 @@
compatible = "grinn,imx6ul-litesom", "fsl,imx6ul";
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
};

194
arch/arm/dts/imx6ul-opos6ul.dtsi
View file

@ -1,192 +1,6 @@
/*
* Copyright 2018 Armadeus Systems <support@armadeus.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
// SPDX-License-Identifier: GPL-2.0 OR MIT
//
// Copyright 2017 Armadeus Systems <support@armadeus.com>
#include "imx6ul.dtsi"
/ {
memory {
reg = <0x80000000 0>; /* will be filled by U-Boot */
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
usdhc3_pwrseq: usdhc3-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-reset-duration = <1>;
phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
phy-handle = <&ethphy1>;
phy-supply = <&reg_3v3>;
status = "okay";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
interrupt-parent = <&gpio4>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
status = "okay";
};
};
};
/* Bluetooth */
&uart8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart8>;
uart-has-rtscts;
status = "okay";
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <8>;
no-1-8-v;
non-removable;
status = "okay";
};
/* WiFi */
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>;
no-1-8-v;
non-removable;
mmc-pwrseq = <&usdhc3_pwrseq>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
brcmf: bcrmf@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio2>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "host-wake";
};
};
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x130b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x130b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x130b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x130b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
/* INT# */
MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0
/* RST# */
MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x130b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
>;
};
pinctrl_uart8: uart8grp {
fsl,pins = <
MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x1b0b0
/* BT_REG_ON */
MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x130b0
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x1b0b0
MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x100b0
MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x1b0b0
MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x1b0b0
MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x1b0b0
MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x1b0b0
/* WL_REG_ON */
MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x130b0
/* WL_IRQ */
MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0
>;
};
};
#include "imx6ul-imx6ull-opos6ul.dtsi"

387
arch/arm/dts/imx6ul-opos6uldev.dts
View file

@ -1,298 +1,21 @@
/*
* Copyright 2017 Armadeus Systems <support@armadeus.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
// SPDX-License-Identifier: GPL-2.0 OR MIT
//
// Copyright 2017 Armadeus Systems <support@armadeus.com>
/dts-v1/;
#include "imx6ul-opos6ul.dtsi"
#include "imx6ul-imx6ull-opos6uldev.dtsi"
/ {
model = "Armadeus Systems OPOS6UL SoM on OPOS6ULDev board";
compatible = "armadeus,opos6uldev", "armadeus,opos6ul", "fsl,imx6ul";
chosen {
stdout-path = &uart1;
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 191000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
power-supply = <&reg_5v>;
status = "okay";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
user-button {
label = "User button";
gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
linux,code = <BTN_MISC>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
user-led {
label = "User";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
onewire {
compatible = "w1-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_w1>;
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usbotg1_vbus: regulator-usbotg1vbus {
compatible = "regulator-fixed";
regulator-name = "usbotg1vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1_vbus>;
gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usbotg2_vbus: regulator-usbotg2vbus {
compatible = "regulator-fixed";
regulator-name = "usbotg2vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg2_vbus>;
gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&adc1 {
vref-supply = <&reg_3v3>;
status = "okay";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_5v>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_5v>;
status = "okay";
};
&ecspi4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>;
status = "okay";
spidev0: spi@0 {
compatible = "spidev";
reg = <0>;
spi-max-frequency = <5000000>;
};
spidev1: spi@1 {
compatible = "spidev";
reg = <1>;
spi-max-frequency = <5000000>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clock_frequency = <400000>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clock_frequency = <400000>;
status = "okay";
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif>;
display = <&display0>;
lcd-supply = <&reg_3v3>;
status = "okay";
display0: display0 {
bits-per-pixel = <18>;
bus-width = <18>;
display-timings {
timing0: timing0 {
clock-frequency = <33000033>;
hactive = <800>;
vactive = <480>;
hback-porch = <96>;
hfront-porch = <96>;
vback-porch = <20>;
vfront-porch = <21>;
hsync-len = <64>;
vsync-len = <4>;
de-active = <1>;
pixelclk-active = <1>;
};
};
};
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&snvs_pwrkey {
status = "disabled";
};
&tsc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
measure-delay-time = <0xffff>;
pre-charge-time = <0xffff>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1_id>;
vbus-supply = <&reg_usbotg1_vbus>;
dr_mode = "otg";
disable-over-current;
status = "okay";
};
&usbotg2 {
vbus-supply = <&reg_usbotg2_vbus>;
dr_mode = "host";
disable-over-current;
status = "okay";
model = "Armadeus Systems OPOS6UL SoM (i.MX6UL) on OPOS6ULDev board";
compatible = "armadeus,imx6ul-opos6uldev", "armadeus,imx6ul-opos6ul", "fsl,imx6ul";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpios>;
pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_tamper_gpios>;
pinctrl_ecspi4: ecspi4grp {
pinctrl_tamper_gpios: tampergpiosgrp {
fsl,pins = <
MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x1b0b0
MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x1b0b0
MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x1b0b0
MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x1b0b0
MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x1b0b0
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0
>;
};
pinctrl_gpios: gpiosgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0b0b0
MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x0b0b0
MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x0b0b0
MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0b0b0
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x0b0b0
MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0b0b0
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0b0b0
MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x0b0b0
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0b0b0
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0
@ -304,100 +27,6 @@
>;
};
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <
MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0b0b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
>;
};
pinctrl_lcdif: lcdifgrp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x100b1
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x100b1
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x100b1
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x100b1
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x100b1
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x100b1
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x100b1
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x100b1
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x100b1
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x100b1
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x100b1
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x100b1
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x100b1
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x100b1
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x100b1
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x100b1
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x100b1
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x100b1
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x100b1
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x100b1
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x100b1
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x100b1
>;
};
pinctrl_led: ledgrp {
fsl,pins = <
MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6UL_PAD_NAND_ALE__PWM3_OUT 0x1b0b0
>;
};
pinctrl_tsc: tscgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
>;
};
pinctrl_usbotg1_id: usbotg1idgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x1b0b0
>;
};
pinctrl_usbotg1_vbus: usbotg1vbusgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1b0b0
>;
};
pinctrl_usbotg2_vbus: usbotg2vbusgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0

21
arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
View file

@ -16,9 +16,13 @@
stdout-path = &uart1;
};
memory {
/*
* Set the minimum memory size here and
* let the bootloader set the real size.
*/
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>;
reg = <0x80000000 0x8000000>;
};
gpio_leds_som: leds {
@ -64,13 +68,17 @@
};
&i2c1 {
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
clock-frequency = <100000>;
status = "okay";
eeprom@52 {
compatible = "catalyst,24c32", "atmel,24c32";
pagesize = <32>;
reg = <0x52>;
};
};
@ -142,6 +150,13 @@
>;
};
pinctrl_i2c1_gpio: i2cgpiogrp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0
MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1

2
arch/arm/dts/imx6ul-phytec-segin-ff-rdk-nand.dts
View file

@ -9,6 +9,8 @@
#include "imx6ul-phytec-phycore-som.dtsi"
#include "imx6ul-phytec-segin.dtsi"
#include "imx6ul-phytec-segin-peb-eval-01.dtsi"
#include "imx6ul-phytec-segin-peb-av-02.dtsi"
#include "imx6ul-phytec-segin-peb-wlbt-05.dtsi"
/ {
model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND";

150
arch/arm/dts/imx6ul-phytec-segin-peb-av-02.dtsi Normal file
View file

@ -0,0 +1,150 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (C) 2016, 2020 PHYTEC Messtechnik
* Author: Christian Hemp <c.hemp@phytec.de>
* Author: Stefan Riedmueller <s.riedmueller@phytec.de>
*/
/ {
backlight_lcd: backlight-lcd {
compatible = "pwm-backlight";
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <5>;
power-supply = <&reg_backlight_en>;
pwms = <&pwm3 0 5000000 0>;
status = "disabled";
};
lcd_panel: lcd-panel {
compatible = "edt,etm0700g0edh6";
backlight = <&backlight_lcd>;
status = "disabled";
port {
lcd_panel_in: endpoint {
remote-endpoint = <&lcdif_parallel_out>;
};
};
};
reg_backlight_en: regulator-backlight-en {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight_en>;
regulator-name = "backlight-lcd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&i2c1 {
edt_ft5406: touchscreen@38 {
compatible = "edt,edt-ft5406";
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_edt_ft5406>;
interrupt-parent = <&gpio5>;
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
wakeup-source;
status = "disabled";
};
stmpe: touchscreen@44 {
compatible = "st,stmpe811";
reg = <0x44>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_stmpe>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio5>;
wakeup-source;
status = "disabled";
stmpe_touchscreen {
compatible = "st,stmpe-ts";
st,sample-time = <4>;
st,mod-12b = <1>;
st,ref-sel = <0>;
st,adc-freq = <1>;
st,ave-ctrl = <1>;
st,touch-det-delay = <2>;
st,settling = <2>;
st,fraction-z = <7>;
st,i-drive = <1>;
touchscreen-inverted-x;
touchscreen-inverted-y;
};
};
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat>;
status = "disabled";
port {
lcdif_parallel_out: endpoint {
remote-endpoint = <&lcd_panel_in>;
};
};
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "disabled";
};
&iomuxc {
pinctrl_edt_ft5406: edtft5406grp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0
>;
};
pinctrl_backlight_en: bachlightengrp {
fsl,pins = <
MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0
>;
};
pinctrl_lcdif_dat: lcdifdatgrp {
fsl,pins = <
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x59
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x59
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x59
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x59
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x59
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x59
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x59
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x59
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x59
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x59
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x59
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x59
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x59
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x59
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x59
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x59
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x59
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x59
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x59
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x59
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x59
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x59
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0
>;
};
pinctrl_stmpe: stmpegrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059
>;
};
};

90
arch/arm/dts/imx6ul-phytec-segin-peb-wlbt-05.dtsi Normal file
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@ -0,0 +1,90 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2021 PHYTEC Messtechnik GmbH
* Author: Yunus Bas <y.bas@phytec.de>
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
reg_wl_en: regulator-wl-en {
compatible = "regulator-fixed";
regulator-name = "wlan_en";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wl>;
gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100>;
status = "disabled";
};
};
&iomuxc {
pinctrl_bt: btgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3031 /* BT ENABLE */
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x3031 /* HOST WAKEUP */
MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x3031 /* DEV WAKEUP */
>;
};
pinctrl_uart2_bt: uart2grp-bt {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x17059
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x17059
MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x17059
MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x17059
>;
};
pinctrl_usdhc2_wl: usdhc2grp-wl {
fsl,pins = <
MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x10051
MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x10061
MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x10051
MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x10051
MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x10051
MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x10051
>;
};
pinctrl_wl: wlgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x3031 /* WLAN ENABLE */
>;
};
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_bt &pinctrl_bt>;
uart-has-rtscts;
status = "disabled";
bluetooth {
compatible = "brcm,bcm43438-bt";
shutdown-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
device-wakeup-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
};
};
&usdhc2 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_wl>;
vmmc-supply = <&reg_wl_en>;
bus-width = <4>;
non-removable;
no-1-8-v;
status = "disabled";
brmcf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
};
};

46
arch/arm/dts/imx6ul-phytec-segin.dtsi
View file

@ -106,7 +106,7 @@
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
status = "disabled";
};
@ -130,31 +130,6 @@
status = "disabled";
};
stmpe: touchscreen@44 {
compatible = "st,stmpe811";
reg = <0x44>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_stmpe>;
status = "disabled";
touchscreen {
compatible = "st,stmpe-ts";
st,sample-time = <4>;
st,mod-12b = <1>;
st,ref-sel = <0>;
st,adc-freq = <1>;
st,ave-ctrl = <1>;
st,touch-det-delay = <2>;
st,settling = <2>;
st,fraction-z = <7>;
st,i-drive = <1>;
touchscreen-inverted-x = <1>;
touchscreen-inverted-y = <1>;
};
};
i2c_rtc: rtc@68 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc_int>;
@ -176,12 +151,6 @@
};
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "disabled";
};
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
@ -222,6 +191,7 @@
no-1-8-v;
keep-power-in-suspend;
wakeup-source;
disable-wp;
status = "disabled";
};
@ -267,12 +237,6 @@
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x0b0b0
>;
};
pinctrl_rtc_int: rtcintgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059
@ -289,12 +253,6 @@
>;
};
pinctrl_stmpe: stmpegrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1

2
arch/arm/dts/imx6ul-pico-hobbit.dts
View file

@ -43,7 +43,7 @@
};
&i2c2 {
clock_frequency = <100000>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";

4
arch/arm/dts/imx6ul-pico-pi.dts
View file

@ -43,7 +43,7 @@
};
&i2c2 {
clock_frequency = <100000>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
@ -58,7 +58,7 @@
};
&i2c3 {
clock_frequency = <100000>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";

40
arch/arm/dts/imx6ul-pico.dtsi
View file

@ -20,7 +20,7 @@
stdout-path = &uart6;
};
backlight {
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
@ -72,6 +72,17 @@
regulator-max-microvolt = <3300000>;
startup-delay-us = <200000>;
};
panel {
compatible = "vxt,vl050-8048nt-c01";
backlight = <&backlight>;
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
};
};
&can1 {
@ -154,36 +165,17 @@
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>;
display = <&display0>;
status = "okay";
display0: display0 {
bits-per-pixel = <32>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <33200000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <210>;
hback-porch = <46>;
hsync-len = <1>;
vback-porch = <22>;
vfront-porch = <23>;
vsync-len = <1>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
port {
display_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
&pwm3 {
#pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";

186
arch/arm/dts/imx6ul.dtsi
View file

@ -43,15 +43,14 @@
sai1 = &sai1;
sai2 = &sai2;
sai3 = &sai3;
spi0 = &qspi;
spi1 = &ecspi1;
spi2 = &ecspi2;
spi3 = &ecspi3;
spi4 = &ecspi4;
usbphy0 = &usbphy1;
usbphy1 = &usbphy2;
spi0 = &ecspi1;
spi1 = &ecspi2;
spi2 = &ecspi3;
spi3 = &ecspi4;
usb0 = &usbotg1;
usb1 = &usbotg2;
usbphy0 = &usbphy1;
usbphy1 = &usbphy2;
};
cpus {
@ -62,6 +61,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
clock-frequency = <696000000>;
clock-latency = <61036>; /* two CLK32 periods */
#cooling-cells = <2>;
operating-points = <
@ -95,18 +95,6 @@
};
};
intc: interrupt-controller@a01000 {
compatible = "arm,gic-400", "arm,cortex-a7-gic";
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
interrupt-controller;
interrupt-parent = <&intc>;
reg = <0x00a01000 0x1000>,
<0x00a02000 0x2000>,
<0x00a04000 0x2000>,
<0x00a06000 0x2000>;
};
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
@ -145,16 +133,6 @@
clock-output-names = "ipp_di1";
};
tempmon: tempmon {
compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
interrupt-parent = <&gpc>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
fsl,tempmon = <&anatop>;
nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
};
pmu {
compatible = "arm,cortex-a7-pmu";
interrupt-parent = <&gpc>;
@ -173,6 +151,18 @@
reg = <0x00900000 0x20000>;
};
intc: interrupt-controller@a01000 {
compatible = "arm,gic-400", "arm,cortex-a7-gic";
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
interrupt-controller;
interrupt-parent = <&intc>;
reg = <0x00a01000 0x1000>,
<0x00a02000 0x2000>,
<0x00a04000 0x2000>,
<0x00a06000 0x2000>;
};
dma_apbh: dma-apbh@1804000 {
compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
reg = <0x01804000 0x2000>;
@ -186,7 +176,7 @@
clocks = <&clks IMX6UL_CLK_APBHDMA>;
};
gpmi: gpmi-nand@1806000 {
gpmi: nand-controller@1806000 {
compatible = "fsl,imx6q-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
@ -229,6 +219,8 @@
clocks = <&clks IMX6UL_CLK_ECSPI1>,
<&clks IMX6UL_CLK_ECSPI1>;
clock-names = "ipg", "per";
dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -241,6 +233,8 @@
clocks = <&clks IMX6UL_CLK_ECSPI2>,
<&clks IMX6UL_CLK_ECSPI2>;
clock-names = "ipg", "per";
dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -253,6 +247,8 @@
clocks = <&clks IMX6UL_CLK_ECSPI3>,
<&clks IMX6UL_CLK_ECSPI3>;
clock-names = "ipg", "per";
dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -265,6 +261,8 @@
clocks = <&clks IMX6UL_CLK_ECSPI4>,
<&clks IMX6UL_CLK_ECSPI4>;
clock-names = "ipg", "per";
dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -345,6 +343,31 @@
dma-names = "rx", "tx";
status = "disabled";
};
asrc: asrc@2034000 {
compatible = "fsl,imx6ul-asrc", "fsl,imx53-asrc";
reg = <0x2034000 0x4000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_ASRC_IPG>,
<&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>,
<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
<&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>,
<&clks IMX6UL_CLK_SPBA>;
clock-names = "mem", "ipg", "asrck_0",
"asrck_1", "asrck_2", "asrck_3", "asrck_4",
"asrck_5", "asrck_6", "asrck_7", "asrck_8",
"asrck_9", "asrck_a", "asrck_b", "asrck_c",
"asrck_d", "asrck_e", "asrck_f", "spba";
dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
<&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
dma-names = "rxa", "rxb", "rxc",
"txa", "txb", "txc";
fsl,asrc-rate = <48000>;
fsl,asrc-width = <16>;
status = "okay";
};
};
tsc: tsc@2040000 {
@ -365,7 +388,7 @@
clocks = <&clks IMX6UL_CLK_PWM1>,
<&clks IMX6UL_CLK_PWM1>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -376,7 +399,7 @@
clocks = <&clks IMX6UL_CLK_PWM2>,
<&clks IMX6UL_CLK_PWM2>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -387,7 +410,7 @@
clocks = <&clks IMX6UL_CLK_PWM3>,
<&clks IMX6UL_CLK_PWM3>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -398,33 +421,33 @@
clocks = <&clks IMX6UL_CLK_PWM4>,
<&clks IMX6UL_CLK_PWM4>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
can1: flexcan@2090000 {
can1: can@2090000 {
compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
reg = <0x02090000 0x4000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
<&clks IMX6UL_CLK_CAN1_SERIAL>;
clock-names = "ipg", "per";
fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
fsl,stop-mode = <&gpr 0x10 1>;
status = "disabled";
};
can2: flexcan@2094000 {
can2: can@2094000 {
compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
reg = <0x02094000 0x4000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
<&clks IMX6UL_CLK_CAN2_SERIAL>;
clock-names = "ipg", "per";
fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
fsl,stop-mode = <&gpr 0x10 2>;
status = "disabled";
};
gpt1: gpt@2098000 {
gpt1: timer@2098000 {
compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
reg = <0x02098000 0x4000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
@ -512,12 +535,14 @@
<&clks IMX6UL_CLK_ENET2_REF_125M>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
fsl,num-tx-queues=<1>;
fsl,num-rx-queues=<1>;
fsl,num-tx-queues = <1>;
fsl,num-rx-queues = <1>;
fsl,stop-mode = <&gpr 0x10 4>;
fsl,magic-packet;
status = "disabled";
};
kpp: kpp@20b8000 {
kpp: keypad@20b8000 {
compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
reg = <0x020b8000 0x4000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
@ -525,14 +550,14 @@
status = "disabled";
};
wdog1: wdog@20bc000 {
wdog1: watchdog@20bc000 {
compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
reg = <0x020bc000 0x4000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_WDOG1>;
};
wdog2: wdog@20c0000 {
wdog2: watchdog@20c0000 {
compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
reg = <0x020c0000 0x4000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
@ -540,7 +565,7 @@
status = "disabled";
};
clks: ccm@20c4000 {
clks: clock-controller@20c4000 {
compatible = "fsl,imx6ul-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
@ -552,7 +577,7 @@
anatop: anatop@20c8000 {
compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
"syscon", "simple-bus";
"syscon", "simple-mfd";
reg = <0x020c8000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
@ -605,6 +630,16 @@
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
tempmon: tempmon {
compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
interrupt-parent = <&gpc>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
fsl,tempmon = <&anatop>;
nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
nvmem-cell-names = "calib", "temp_grade";
clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
};
};
usbphy1: usbphy@20c9000 {
@ -652,6 +687,7 @@
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
linux,keycode = <KEY_POWER>;
wakeup-source;
status = "disabled";
};
snvs_lpgpr: snvs-lpgpr {
@ -669,7 +705,7 @@
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
};
src: src@20d8000 {
src: reset-controller@20d8000 {
compatible = "fsl,imx6ul-src", "fsl,imx51-src";
reg = <0x020d8000 0x4000>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
@ -686,7 +722,7 @@
interrupt-parent = <&intc>;
};
iomuxc: iomuxc@20e0000 {
iomuxc: pinctrl@20e0000 {
compatible = "fsl,imx6ul-iomuxc";
reg = <0x020e0000 0x4000>;
};
@ -697,13 +733,14 @@
reg = <0x020e4000 0x4000>;
};
gpt2: gpt@20e8000 {
gpt2: timer@20e8000 {
compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
reg = <0x020e8000 0x4000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
<&clks IMX6UL_CLK_GPT2_SERIAL>;
clock-names = "ipg", "per";
status = "disabled";
};
sdma: sdma@20ec000 {
@ -725,7 +762,7 @@
clocks = <&clks IMX6UL_CLK_PWM5>,
<&clks IMX6UL_CLK_PWM5>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -736,7 +773,7 @@
clocks = <&clks IMX6UL_CLK_PWM6>,
<&clks IMX6UL_CLK_PWM6>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -747,7 +784,7 @@
clocks = <&clks IMX6UL_CLK_PWM7>,
<&clks IMX6UL_CLK_PWM7>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
@ -758,7 +795,7 @@
clocks = <&clks IMX6UL_CLK_PWM8>,
<&clks IMX6UL_CLK_PWM8>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
#pwm-cells = <3>;
status = "disabled";
};
};
@ -770,7 +807,7 @@
reg = <0x02100000 0x100000>;
ranges;
crypto: caam@2140000 {
crypto: crypto@2140000 {
compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
@ -781,19 +818,19 @@
<&clks IMX6UL_CLK_CAAM_MEM>;
clock-names = "ipg", "aclk", "mem";
sec_jr0: jr0@1000 {
sec_jr0: jr@1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr1@2000 {
sec_jr1: jr@2000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr2: jr2@3000 {
sec_jr2: jr@3000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x3000 0x1000>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
@ -846,12 +883,14 @@
<&clks IMX6UL_CLK_ENET_REF>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
fsl,num-tx-queues=<1>;
fsl,num-rx-queues=<1>;
fsl,num-tx-queues = <1>;
fsl,num-rx-queues = <1>;
fsl,stop-mode = <&gpr 0x10 3>;
fsl,magic-packet;
status = "disabled";
};
usdhc1: usdhc@2190000 {
usdhc1: mmc@2190000 {
compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
@ -859,11 +898,13 @@
<&clks IMX6UL_CLK_USDHC1>,
<&clks IMX6UL_CLK_USDHC1>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-step = <2>;
fsl,tuning-start-tap = <20>;
bus-width = <4>;
status = "disabled";
};
usdhc2: usdhc@2194000 {
usdhc2: mmc@2194000 {
compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
@ -872,6 +913,8 @@
<&clks IMX6UL_CLK_USDHC2>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
fsl,tuning-step = <2>;
fsl,tuning-start-tap = <20>;
status = "disabled";
};
@ -934,7 +977,7 @@
status = "disabled";
};
ocotp: ocotp-ctrl@21bc000 {
ocotp: efuse@21bc000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,imx6ul-ocotp", "syscon";
@ -954,6 +997,15 @@
};
};
csi: csi@21c4000 {
compatible = "fsl,imx6ul-csi", "fsl,imx7-csi";
reg = <0x021c4000 0x4000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_CSI>;
clock-names = "mclk";
status = "disabled";
};
lcdif: lcdif@21c8000 {
compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
reg = <0x021c8000 0x4000>;
@ -965,6 +1017,14 @@
status = "disabled";
};
pxp: pxp@21cc000 {
compatible = "fsl,imx6ul-pxp";
reg = <0x021cc000 0x4000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_PXP>;
clock-names = "axi";
};
qspi: spi@21e0000 {
#address-cells = <1>;
#size-cells = <0>;
@ -978,7 +1038,7 @@
status = "disabled";
};
wdog3: wdog@21e4000 {
wdog3: watchdog@21e4000 {
compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
reg = <0x021e4000 0x4000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

2
arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts
View file

@ -7,7 +7,6 @@
/dts-v1/;
#include "imx6ull.dtsi"
#include "imx6ull-myir-mys-6ulx.dtsi"
#include "imx6ull-mys-6ulx-u-boot.dtsi"
/ {
model = "MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND";
@ -15,5 +14,6 @@
};
&gpmi {
fsl,use-minimum-ecc;
status = "okay";
};

1
arch/arm/dts/imx6ull-phytec-segin-ff-rdk-emmc.dts
View file

@ -9,6 +9,7 @@
#include "imx6ull-phytec-phycore-som.dtsi"
#include "imx6ull-phytec-segin.dtsi"
#include "imx6ull-phytec-segin-peb-eval-01.dtsi"
#include "imx6ull-phytec-segin-peb-av-02.dtsi"
/ {
model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with eMMC";

26
arch/arm/dts/imx6ull-phytec-segin-peb-av-02.dtsi Normal file
View file

@ -0,0 +1,26 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
* Copyright (C) 2018 PHYTEC Messtechnik GmbH
* Author: Stefan Riedmueller <s.riedmueller@phytec.de>
*/
#include "imx6ul-phytec-segin-peb-av-02.dtsi"
&iomuxc {
/delete-node/ edtft5406grp;
/delete-node/ stmpegrp;
};
&iomuxc_snvs {
pinctrl_edt_ft5406: edtft5406grp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0
>;
};
pinctrl_stmpe: stmpegrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059
>;
};
};

7
arch/arm/dts/imx6ull-phytec-segin.dtsi
View file

@ -14,7 +14,6 @@
&iomuxc {
/delete-node/ flexcan1engrp;
/delete-node/ rtcintgrp;
/delete-node/ stmpegrp;
};
&iomuxc_snvs {
@ -29,10 +28,4 @@
MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059
>;
};
pinctrl_stmpe: stmpegrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x17059
>;
};
};

14
arch/arm/dts/imx6ull.dtsi
View file

@ -12,6 +12,7 @@
/delete-node/ &crypto;
&cpu0 {
clock-frequency = <900000000>;
operating-points = <
/* kHz uV */
900000 1275000
@ -34,6 +35,12 @@
compatible = "fsl,imx6ull-ocotp", "syscon";
};
&pxp {
compatible = "fsl,imx6ull-pxp";
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
};
&usdhc1 {
compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc";
};
@ -61,6 +68,13 @@
clock-names = "dcp";
};
rngb: rng@2284000 {
compatible = "fsl,imx6ull-rngb", "fsl,imx25-rngb";
reg = <0x02284000 0x4000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_DUMMY>;
};
iomuxc_snvs: iomuxc-snvs@2290000 {
compatible = "fsl,imx6ull-iomuxc-snvs";
reg = <0x02290000 0x4000>;