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net: dw_eth_qos: Add 64-bit addressing

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Set upper 32bit address for DMA descriptors and buffer address to support
64-bit addressing.

Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
This commit is contained in:
Ley Foon Tan 2022-12-09 14:33:14 +08:00 committed by Tom Rini
parent a4c83bda17
commit 5d260d0800
1 changed files with 20 additions and 16 deletions
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36
drivers/net/dwc_eth_qos.c
View file

@ -746,6 +746,7 @@ static int eqos_start(struct udevice *dev)
u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
ulong last_rx_desc;
ulong desc_pad;
ulong addr64;
debug("%s(dev=%p):\n", __func__, dev);
@ -1039,25 +1040,25 @@ static int eqos_start(struct udevice *dev)
for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) {
struct eqos_desc *rx_desc = eqos_get_desc(eqos, i, true);
rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
(i * EQOS_MAX_PACKET_SIZE));
addr64 = (ulong)(eqos->rx_dma_buf + (i * EQOS_MAX_PACKET_SIZE));
rx_desc->des0 = lower_32_bits(addr64);
rx_desc->des1 = upper_32_bits(addr64);
rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
mb();
eqos->config->ops->eqos_flush_desc(rx_desc);
eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf +
(i * EQOS_MAX_PACKET_SIZE),
EQOS_MAX_PACKET_SIZE);
eqos->config->ops->eqos_inval_buffer((void *)addr64, EQOS_MAX_PACKET_SIZE);
}
writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress);
writel((ulong)eqos_get_desc(eqos, 0, false),
&eqos->dma_regs->ch0_txdesc_list_address);
addr64 = (ulong)eqos_get_desc(eqos, 0, false);
writel(upper_32_bits(addr64), &eqos->dma_regs->ch0_txdesc_list_haddress);
writel(lower_32_bits(addr64), &eqos->dma_regs->ch0_txdesc_list_address);
writel(EQOS_DESCRIPTORS_TX - 1,
&eqos->dma_regs->ch0_txdesc_ring_length);
writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress);
writel((ulong)eqos_get_desc(eqos, 0, true),
&eqos->dma_regs->ch0_rxdesc_list_address);
addr64 = (ulong)eqos_get_desc(eqos, 0, true);
writel(upper_32_bits(addr64), &eqos->dma_regs->ch0_rxdesc_list_haddress);
writel(lower_32_bits(addr64), &eqos->dma_regs->ch0_rxdesc_list_address);
writel(EQOS_DESCRIPTORS_RX - 1,
&eqos->dma_regs->ch0_rxdesc_ring_length);
@ -1162,8 +1163,8 @@ static int eqos_send(struct udevice *dev, void *packet, int length)
eqos->tx_desc_idx++;
eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX;
tx_desc->des0 = (ulong)eqos->tx_dma_buf;
tx_desc->des1 = 0;
tx_desc->des0 = lower_32_bits((ulong)eqos->tx_dma_buf);
tx_desc->des1 = upper_32_bits((ulong)eqos->tx_dma_buf);
tx_desc->des2 = length;
/*
* Make sure that if HW sees the _OWN write below, it will see all the
@ -1234,14 +1235,17 @@ static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
for (idx = eqos->rx_desc_idx - idx_mask;
idx <= eqos->rx_desc_idx;
idx++) {
ulong addr64;
rx_desc = eqos_get_desc(eqos, idx, true);
rx_desc->des0 = 0;
rx_desc->des1 = 0;
mb();
eqos->config->ops->eqos_flush_desc(rx_desc);
eqos->config->ops->eqos_inval_buffer(packet, length);
rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
(idx * EQOS_MAX_PACKET_SIZE));
rx_desc->des1 = 0;
addr64 = (ulong)(eqos->rx_dma_buf + (idx * EQOS_MAX_PACKET_SIZE));
rx_desc->des0 = lower_32_bits(addr64);
rx_desc->des1 = upper_32_bits(addr64);
rx_desc->des2 = 0;
/*
* Make sure that if HW sees the _OWN write below,