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imx9: simplify clk settings

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Simplify the clk root settings with an array

Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan 2023-04-28 12:08:19 +08:00 committed by Stefano Babic
parent 532e73fdda
commit 5d09fcf24d
2 changed files with 28 additions and 16 deletions
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6
arch/arm/include/asm/arch-imx9/clock.h
View file

@ -205,6 +205,12 @@ struct clk_root_map {
u32 mux_type; u32 mux_type;
}; };
struct imx_clk_setting {
u32 clk_root;
enum ccm_clk_src src;
u32 div;
};
int clock_init(void); int clock_init(void);
u32 get_clk_src_rate(enum ccm_clk_src source); u32 get_clk_src_rate(enum ccm_clk_src source);
u32 get_lpuart_clk(void); u32 get_lpuart_clk(void);

38
arch/arm/mach-imx/imx9/clock.c
View file

@ -680,36 +680,42 @@ void set_arm_clk(ulong freq)
#endif #endif
int clock_init(void) struct imx_clk_setting imx_clk_settings[] = {
{
int i;
/* Set A55 periphal to 333M */ /* Set A55 periphal to 333M */
ccm_clk_root_cfg(ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3); {ARM_A55_PERIPH_CLK_ROOT, SYS_PLL_PFD0, 3},
/* Set A55 mtr bus to 133M */ /* Set A55 mtr bus to 133M */
ccm_clk_root_cfg(ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); {ARM_A55_MTR_BUS_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* Sentinel to 200M */ /* Sentinel to 200M */
ccm_clk_root_cfg(SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2); {SENTINEL_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2},
/* Bus_wakeup to 133M */ /* Bus_wakeup to 133M */
ccm_clk_root_cfg(BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); {BUS_WAKEUP_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* Bus_AON to 133M */ /* Bus_AON to 133M */
ccm_clk_root_cfg(BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); {BUS_AON_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* M33 to 200M */ /* M33 to 200M */
ccm_clk_root_cfg(M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2); {M33_CLK_ROOT, SYS_PLL_PFD1_DIV2, 2},
/* /*
* WAKEUP_AXI to 312.5M, because of FEC only can support to 320M for * WAKEUP_AXI to 312.5M, because of FEC only can support to 320M for
* generating MII clock at 2.5M * generating MII clock at 2.5M
*/ */
ccm_clk_root_cfg(WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2); {WAKEUP_AXI_CLK_ROOT, SYS_PLL_PFD2, 2},
/* SWO TRACE to 133M */ /* SWO TRACE to 133M */
ccm_clk_root_cfg(SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); {SWO_TRACE_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3},
/* M33 systetick to 24M */ /* M33 systetick to 24M */
ccm_clk_root_cfg(M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1); {M33_SYSTICK_CLK_ROOT, OSC_24M_CLK, 1},
/* NIC to 400M */ /* NIC to 400M */
ccm_clk_root_cfg(NIC_CLK_ROOT, SYS_PLL_PFD1, 2); {NIC_CLK_ROOT, SYS_PLL_PFD1, 2},
/* NIC_APB to 133M */ /* NIC_APB to 133M */
ccm_clk_root_cfg(NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3); {NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}
};
int clock_init(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(imx_clk_settings); i++) {
ccm_clk_root_cfg(imx_clk_settings[i].clk_root,
imx_clk_settings[i].src, imx_clk_settings[i].div);
}
/* allow for non-secure access */ /* allow for non-secure access */
for (i = 0; i < OSCPLL_END; i++) for (i = 0; i < OSCPLL_END; i++)