mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-22 19:23:07 +00:00
Merge with git+ssh://sr@pollux.denx.org/home/sr/git/u-boot/denx/.git
This commit is contained in:
commit
5c97aeb8d8
31 changed files with 10344 additions and 40 deletions
165
CHANGELOG
165
CHANGELOG
|
@ -1,3 +1,85 @@
|
|||
commit 726e90aacf0b1ecb0e7055be574622fbe3e450ba
|
||||
Author: Grant Likely <grant.likely@secretlab.ca>
|
||||
Date: Wed Nov 29 16:23:42 2006 +0100
|
||||
|
||||
[PATCH] [MPC52xx] Use IPB bus frequency for SOC peripherals
|
||||
|
||||
The soc node of the mpc52xx needs to be loaded with the IPB bus frequency,
|
||||
not the XLB frequency.
|
||||
|
||||
This patch depends on the previous patches for MPC52xx device tree support
|
||||
|
||||
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
|
||||
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
|
||||
|
||||
commit 1eac2a71417b6675b11aace72102a2e7fde8f5c6
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Wed Nov 29 15:42:37 2006 +0100
|
||||
|
||||
[PATCH] Add support for Prodrive P3M750 & P3M7448 (P3Mx) boards
|
||||
|
||||
This patch adds support for the Prodrive P3M750 (PPC750 & MV64460)
|
||||
and the P3M7448 (MPC7448 & MV64460) PMC modules. Both modules are
|
||||
quite similar and share the same board directory "prodrive/p3mx"
|
||||
and the same config file "p3mx.h".
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 1bdd46832aeb569f5e04b1f20f64318525b6525a
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Wed Nov 29 12:53:15 2006 +0100
|
||||
|
||||
[PATCH] common/cmd_elf.c: Enable loadaddr as parameter in bootvx command
|
||||
|
||||
In the bootvx command the load address was only read from the env
|
||||
variable "loadaddr" and not optionally passed as paramter as described
|
||||
in the help. This is fixed with this patch. The behaviour is now the
|
||||
same as in the bootelf command.
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 4e26f1074c3ac1bd8fd094f0dc4a1c4a0b15a592
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Wed Nov 29 12:03:57 2006 +0100
|
||||
|
||||
[PATCH] include/ppc440.h minor error affecting interrupts
|
||||
|
||||
Fixed include/ppc440.c for UIC address Bug
|
||||
|
||||
Corrects bug affecting the addresses for the universal interrupt
|
||||
controller UIC2 and UIC3 on the PPC440 Epx, GRx, and SPE chips.
|
||||
|
||||
Signed-off-by: Jeff Mann <mannj@embeddedplanet.com>
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit e59581c56ab5d6e0207ddac3b2c1d55cb36ec706
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Tue Nov 28 17:55:49 2006 +0100
|
||||
|
||||
[PATCH] Enable the IceCube/lite5200 variants to pass a device tree to Linux.
|
||||
|
||||
This patch adds the code and configuration necessary to boot with an
|
||||
arch/powerpc Linux kernel.
|
||||
|
||||
Signed-off-by: Grant Likely <grant.likely@gmail.com>
|
||||
Acked-by: Jon Loeliger <jdl@freescale.com>
|
||||
|
||||
commit e732faec95a83cb468b4850ae807c8301dde8f6a
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Tue Nov 28 16:09:24 2006 +0100
|
||||
|
||||
[PATCH] PPC4xx: 440SP Rev. C detection added
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit e7f3e9ff01fbd7fa72eb42a9675fbed6bc4736b0
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Tue Nov 28 11:04:45 2006 +0100
|
||||
|
||||
[PATCH] nand: Fix patch merge problem
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 4f4b602ec7524a032bdf3c6d28c7f525a4a67eaa
|
||||
Author: Wolfgang Denk <wd@pollux.denx.de>
|
||||
Date: Mon Nov 27 22:53:53 2006 +0100
|
||||
|
@ -67,6 +149,46 @@ Date: Mon Nov 27 15:32:42 2006 +0100
|
|||
|
||||
Minor code cleanup. Update CHANGELOG.
|
||||
|
||||
commit 1729b92cde575476684bffe819d0b7791b57bff2
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Mon Nov 27 14:52:04 2006 +0100
|
||||
|
||||
[PATCH] 4xx: Fix problem with board specific reset code (now for real)
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit cc5ee8a92a0e3ca6f727af71b8fd206460c7afd7
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Mon Nov 27 14:49:51 2006 +0100
|
||||
|
||||
[PATCH] alpr: remove unused board specific flash driver
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 1f94d162e2b5f0edc28d9fb11482502c44d218e1
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Mon Nov 27 14:48:41 2006 +0100
|
||||
|
||||
[PATCH] 4xx: Fix problem with board specific reset code
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit ec0c2ec725aec9524a177a77ce75559e644a931a
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Mon Nov 27 14:46:06 2006 +0100
|
||||
|
||||
[PATCH] Remove testing 4xx enet PHY setup
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 1c2ce2262069510f31c7d3fd7efd3d58b8c0c148
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Mon Nov 27 14:12:17 2006 +0100
|
||||
|
||||
[PATCH] Update Prodrive ALPR board support (440GX)
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 78d620ebb5871d252270dedfad60c6568993b780
|
||||
Author: Wolfgang Denk <wd@atlas.denx.de>
|
||||
Date: Thu Nov 23 22:58:58 2006 +0100
|
||||
|
@ -641,6 +763,34 @@ Date: Tue Oct 10 17:02:22 2006 -0500
|
|||
|
||||
Fix whitespace and 80-col issues.
|
||||
|
||||
commit 5c912cb1c31266c66ca59b36f9b6f87296421d75
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Sat Oct 7 11:36:51 2006 +0200
|
||||
|
||||
CFG_NAND_QUIET_TEST added to not warn upon missing NAND device
|
||||
Patch by Stefan Roese, 07 Oct 2006
|
||||
|
||||
commit 5bc528fa4da751d472397b308137238a6465afd2
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Sat Oct 7 11:35:25 2006 +0200
|
||||
|
||||
Update ALPR code (NAND support working now)
|
||||
Patch by Stefan Roese, 07 Oct 2006
|
||||
|
||||
commit 77d5034847d328753b80c46b83f960a14a26f40e
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Sat Oct 7 11:33:03 2006 +0200
|
||||
|
||||
Remove compile warnings in fpga code
|
||||
Patch by Stefan Roese, 07 Oct 2006
|
||||
|
||||
commit f3443867e90d2979a7dd1c65b0d537777e1f9850
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Sat Oct 7 11:30:52 2006 +0200
|
||||
|
||||
Add CONFIG_BOARD_RESET to configure board specific reset function
|
||||
Patch by Stefan Roese, 07 Oct 2006
|
||||
|
||||
commit f55df18187e7a45cb73fec4370d12135e6691ae1
|
||||
Author: John Traill <john.traill@freescale.com>
|
||||
Date: Fri Sep 29 08:23:12 2006 +0100
|
||||
|
@ -873,6 +1023,21 @@ Date: Wed Aug 16 10:54:09 2006 -0500
|
|||
|
||||
Signed-off-by: Matthew McClintock <msm@freescale.com>
|
||||
|
||||
commit 899620c2d66d4eef3b2a0034d062e71d45d886c9
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Tue Aug 15 14:22:35 2006 +0200
|
||||
|
||||
Add initial support for the ALPR board from Prodrive
|
||||
NAND needs some additional testing
|
||||
Patch by Heiko Schocher, 15 Aug 2006
|
||||
|
||||
commit f0ff4692ff3372dec55074a8eb444943ab095abb
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Tue Aug 15 14:15:51 2006 +0200
|
||||
|
||||
Add FPGA Altera Cyclone 2 support
|
||||
Patch by Heiko Schocher, 15 Aug 2006
|
||||
|
||||
commit fecf1c7e4de1b2779edc18742b91c22bdc32b68b
|
||||
Author: Jon Loeliger <jdl@freescale.com>
|
||||
Date: Mon Aug 14 15:33:38 2006 -0500
|
||||
|
|
|
@ -277,6 +277,8 @@ Daniel Poirot <dan.poirot@windriver.com>
|
|||
|
||||
Stefan Roese <sr@denx.de>
|
||||
|
||||
P3M7448 MPC7448
|
||||
|
||||
uc100 MPC857
|
||||
|
||||
TQM85xx MPC8540/8541/8555/8560
|
||||
|
@ -294,6 +296,8 @@ Stefan Roese <sr@denx.de>
|
|||
yellowstone PPC440GR
|
||||
yosemite PPC440EP
|
||||
|
||||
P3M750 PPC750FX/GX/GL
|
||||
|
||||
Yusdi Santoso <yusdi_santoso@adaptec.com>
|
||||
|
||||
HIDDEN_DRAGON MPC8241/MPC8245
|
||||
|
|
5
MAKEALL
5
MAKEALL
|
@ -151,11 +151,12 @@ LIST_85xx=" \
|
|||
|
||||
LIST_74xx=" \
|
||||
DB64360 DB64460 EVB64260 P3G4 \
|
||||
PCIPPC2 PCIPPC6 ZUMA \
|
||||
p3m7448 PCIPPC2 PCIPPC6 ZUMA \
|
||||
"
|
||||
|
||||
LIST_7xx=" \
|
||||
BAB7xx CPCI750 ELPPC ppmc7xx \
|
||||
BAB7xx CPCI750 ELPPC p3m750 \
|
||||
ppmc7xx \
|
||||
"
|
||||
|
||||
LIST_ppc="${LIST_5xx} ${LIST_5xxx} \
|
||||
|
|
10
Makefile
10
Makefile
|
@ -1724,6 +1724,16 @@ EVB64260_750CX_config: unconfig
|
|||
P3G4_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc 74xx_7xx evb64260
|
||||
|
||||
p3m750_config \
|
||||
p3m7448_config: unconfig
|
||||
@mkdir -p $(obj)include
|
||||
@if [ "$(findstring 750_,$@)" ] ; then \
|
||||
echo "#define CONFIG_P3M750" >>$(obj)include/config.h ; \
|
||||
else \
|
||||
echo "#define CONFIG_P3M7448" >>$(obj)include/config.h ; \
|
||||
fi
|
||||
@$(MKCONFIG) -a p3mx ppc 74xx_7xx p3mx prodrive
|
||||
|
||||
PCIPPC2_config \
|
||||
PCIPPC6_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc 74xx_7xx pcippc2
|
||||
|
|
52
board/prodrive/p3mx/64460.h
Normal file
52
board/prodrive/p3mx/64460.h
Normal file
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Ingo Assmus <ingo.assmus@keymile.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* main board support/init for the Galileo Eval board DB64460.
|
||||
*/
|
||||
|
||||
#ifndef __64460_H__
|
||||
#define __64460_H__
|
||||
|
||||
/* CPU Configuration bits */
|
||||
#define CPU_CONF_ADDR_MISS_EN (1 << 8)
|
||||
#define CPU_CONF_SINGLE_CPU (1 << 11)
|
||||
#define CPU_CONF_ENDIANESS (1 << 12)
|
||||
#define CPU_CONF_PIPELINE (1 << 13)
|
||||
#define CPU_CONF_STOP_RETRY (1 << 17)
|
||||
#define CPU_CONF_MULTI_DECODE (1 << 18)
|
||||
#define CPU_CONF_DP_VALID (1 << 19)
|
||||
#define CPU_CONF_PERR_PROP (1 << 22)
|
||||
#define CPU_CONF_AACK_DELAY_2 (1 << 25)
|
||||
#define CPU_CONF_AP_VALID (1 << 26)
|
||||
#define CPU_CONF_REMAP_WR_DIS (1 << 27)
|
||||
|
||||
/* CPU Master Control bits */
|
||||
#define CPU_MAST_CTL_ARB_EN (1 << 8)
|
||||
#define CPU_MAST_CTL_MASK_BR_1 (1 << 9)
|
||||
#define CPU_MAST_CTL_M_WR_TRIG (1 << 10)
|
||||
#define CPU_MAST_CTL_M_RD_TRIG (1 << 11)
|
||||
#define CPU_MAST_CTL_CLEAN_BLK (1 << 12)
|
||||
#define CPU_MAST_CTL_FLUSH_BLK (1 << 13)
|
||||
|
||||
#endif /* __64460_H__ */
|
55
board/prodrive/p3mx/Makefile
Normal file
55
board/prodrive/p3mx/Makefile
Normal file
|
@ -0,0 +1,55 @@
|
|||
#
|
||||
# (C) Copyright 2002-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../../Marvell/common)
|
||||
endif
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
SOBJS = misc.o
|
||||
COBJS = $(BOARD).o mpsc.o mv_eth.o pci.o sdram_init.o serial.o \
|
||||
../../Marvell/common/i2c.o ../../Marvell/common/memory.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend *~
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
28
board/prodrive/p3mx/config.mk
Normal file
28
board/prodrive/p3mx/config.mk
Normal file
|
@ -0,0 +1,28 @@
|
|||
#
|
||||
# (C) Copyright 2002-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# p3mx boards (P3M750 & P3M7448)
|
||||
#
|
||||
|
||||
TEXT_BASE = 0xfff00000
|
43
board/prodrive/p3mx/eth.h
Normal file
43
board/prodrive/p3mx/eth.h
Normal file
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* eth.h - header file for the polled mode GT ethernet driver
|
||||
*/
|
||||
|
||||
#ifndef __EVB64360_ETH_H__
|
||||
#define __EVB64360_ETH_H__
|
||||
|
||||
#include <asm/types.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/byteorder.h>
|
||||
#include <common.h>
|
||||
|
||||
|
||||
int db64360_eth0_poll(void);
|
||||
int db64360_eth0_transmit(unsigned int s, volatile char *p);
|
||||
void db64360_eth0_disable(void);
|
||||
bool network_start(bd_t *bis);
|
||||
|
||||
|
||||
#endif /* __EVB64360_ETH_H__ */
|
245
board/prodrive/p3mx/misc.S
Normal file
245
board/prodrive/p3mx/misc.S
Normal file
|
@ -0,0 +1,245 @@
|
|||
#include <config.h>
|
||||
#include <74xx_7xx.h>
|
||||
#include "version.h"
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <ppc_defs.h>
|
||||
|
||||
#include <asm/cache.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
#include "../../Marvell/include/mv_gen_reg.h"
|
||||
|
||||
#ifdef CONFIG_ECC
|
||||
/* Galileo specific asm code for initializing ECC */
|
||||
.globl board_relocate_rom
|
||||
board_relocate_rom:
|
||||
mflr r7
|
||||
/* update the location of the GT registers */
|
||||
lis r11, CFG_GT_REGS@h
|
||||
/* if we're using ECC, we must use the DMA engine to copy ourselves */
|
||||
bl start_idma_transfer_0
|
||||
bl wait_for_idma_0
|
||||
bl stop_idma_engine_0
|
||||
|
||||
mtlr r7
|
||||
blr
|
||||
|
||||
.globl board_init_ecc
|
||||
board_init_ecc:
|
||||
mflr r7
|
||||
/* NOTE: r10 still contains the location we've been relocated to
|
||||
* which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */
|
||||
|
||||
/* now that we're running from ram, init the rest of main memory
|
||||
* for ECC use */
|
||||
lis r8, CFG_MONITOR_LEN@h
|
||||
ori r8, r8, CFG_MONITOR_LEN@l
|
||||
|
||||
divw r3, r10, r8
|
||||
|
||||
/* set up the counter, and init the starting address */
|
||||
mtctr r3
|
||||
li r12, 0
|
||||
|
||||
/* bytes per transfer */
|
||||
mr r5, r8
|
||||
about_to_init_ecc:
|
||||
1: mr r3, r12
|
||||
mr r4, r12
|
||||
bl start_idma_transfer_0
|
||||
bl wait_for_idma_0
|
||||
bl stop_idma_engine_0
|
||||
add r12, r12, r8
|
||||
bdnz 1b
|
||||
|
||||
mtlr r7
|
||||
blr
|
||||
|
||||
/* r3: dest addr
|
||||
* r4: source addr
|
||||
* r5: byte count
|
||||
* r11: gt regbase
|
||||
* trashes: r6, r5
|
||||
*/
|
||||
start_idma_transfer_0:
|
||||
/* set the byte count, including the OWN bit */
|
||||
mr r6, r11
|
||||
ori r6, r6, CHANNEL0_DMA_BYTE_COUNT
|
||||
stwbrx r5, 0, (r6)
|
||||
|
||||
/* set the source address */
|
||||
mr r6, r11
|
||||
ori r6, r6, CHANNEL0_DMA_SOURCE_ADDRESS
|
||||
stwbrx r4, 0, (r6)
|
||||
|
||||
/* set the dest address */
|
||||
mr r6, r11
|
||||
ori r6, r6, CHANNEL0_DMA_DESTINATION_ADDRESS
|
||||
stwbrx r3, 0, (r6)
|
||||
|
||||
/* set the next record pointer */
|
||||
li r5, 0
|
||||
mr r6, r11
|
||||
ori r6, r6, CHANNEL0NEXT_RECORD_POINTER
|
||||
stwbrx r5, 0, (r6)
|
||||
|
||||
/* set the low control register */
|
||||
/* bit 9 is NON chained mode, bit 31 is new style descriptors.
|
||||
bit 12 is channel enable */
|
||||
ori r5, r5, (1 << 12) | (1 << 12) | (1 << 11)
|
||||
/* 15 shifted by 16 (oris) == bit 31 */
|
||||
oris r5, r5, (1 << 15)
|
||||
mr r6, r11
|
||||
ori r6, r6, CHANNEL0CONTROL
|
||||
stwbrx r5, 0, (r6)
|
||||
|
||||
blr
|
||||
|
||||
/* this waits for the bytecount to return to zero, indicating
|
||||
* that the trasfer is complete */
|
||||
wait_for_idma_0:
|
||||
mr r5, r11
|
||||
lis r6, 0xff
|
||||
ori r6, r6, 0xffff
|
||||
ori r5, r5, CHANNEL0_DMA_BYTE_COUNT
|
||||
1: lwbrx r4, 0, (r5)
|
||||
and. r4, r4, r6
|
||||
bne 1b
|
||||
|
||||
blr
|
||||
|
||||
/* this turns off channel 0 of the idma engine */
|
||||
stop_idma_engine_0:
|
||||
/* shut off the DMA engine */
|
||||
li r5, 0
|
||||
mr r6, r11
|
||||
ori r6, r6, CHANNEL0CONTROL
|
||||
stwbrx r5, 0, (r6)
|
||||
|
||||
blr
|
||||
#endif
|
||||
|
||||
#ifdef CFG_BOARD_ASM_INIT
|
||||
/* NOTE: trashes r3-r7 */
|
||||
.globl board_asm_init
|
||||
board_asm_init:
|
||||
/* just move the GT registers to where they belong */
|
||||
lis r3, CFG_DFL_GT_REGS@h
|
||||
ori r3, r3, CFG_DFL_GT_REGS@l
|
||||
lis r4, CFG_GT_REGS@h
|
||||
ori r4, r4, CFG_GT_REGS@l
|
||||
li r5, INTERNAL_SPACE_DECODE
|
||||
|
||||
/* test to see if we've already moved */
|
||||
lwbrx r6, r5, r4
|
||||
andi. r6, r6, 0xffff
|
||||
/* check loading of R7 is: 0x0F80 should: 0xf800: DONE */
|
||||
/* rlwinm r7, r4, 8, 16, 31
|
||||
rlwinm r7, r4, 12, 16, 31 */ /* original */
|
||||
rlwinm r7, r4, 16, 16, 31
|
||||
/* -----------------------------------------------------*/
|
||||
cmp cr0, r7, r6
|
||||
beqlr
|
||||
|
||||
/* nope, have to move the registers */
|
||||
lwbrx r6, r5, r3
|
||||
andis. r6, r6, 0xffff
|
||||
or r6, r6, r7
|
||||
stwbrx r6, r5, r3
|
||||
|
||||
/* now, poll for the change */
|
||||
1: lwbrx r7, r5, r4
|
||||
cmp cr0, r7, r6
|
||||
bne 1b
|
||||
|
||||
lis r3, CFG_INT_SRAM_BASE@h
|
||||
ori r3, r3, CFG_INT_SRAM_BASE@l
|
||||
rlwinm r3, r3, 16, 16, 31
|
||||
lis r4, CFG_GT_REGS@h
|
||||
ori r4, r4, CFG_GT_REGS@l
|
||||
li r5, INTEGRATED_SRAM_BASE_ADDR
|
||||
stwbrx r3, r5, r4
|
||||
|
||||
2: lwbrx r6, r5, r4
|
||||
cmp cr0, r3, r6
|
||||
bne 2b
|
||||
|
||||
/* done! */
|
||||
blr
|
||||
#endif
|
||||
|
||||
/* For use of the debug LEDs */
|
||||
.global led_on0_relocated
|
||||
led_on0_relocated:
|
||||
xor r21, r21, r21
|
||||
xor r18, r18, r18
|
||||
lis r18, 0xFC80
|
||||
ori r18, r18, 0x8000
|
||||
/* stw r21, 0x0(r18) */
|
||||
sync
|
||||
blr
|
||||
|
||||
.global led_off0_relocated
|
||||
led_off0_relocated:
|
||||
xor r21, r21, r21
|
||||
xor r18, r18, r18
|
||||
lis r18, 0xFC81
|
||||
ori r18, r18, 0x4000
|
||||
/* stw r21, 0x0(r18) */
|
||||
sync
|
||||
blr
|
||||
|
||||
.global led_on0
|
||||
led_on0:
|
||||
xor r18, r18, r18
|
||||
lis r18, 0x1c80
|
||||
ori r18, r18, 0x8000
|
||||
/* stw r18, 0x0(r18) */
|
||||
sync
|
||||
blr
|
||||
|
||||
.global led_off0
|
||||
led_off0:
|
||||
xor r18, r18, r18
|
||||
lis r18, 0x1c81
|
||||
ori r18, r18, 0x4000
|
||||
/* stw r18, 0x0(r18) */
|
||||
sync
|
||||
blr
|
||||
|
||||
.global led_on1
|
||||
led_on1:
|
||||
xor r18, r18, r18
|
||||
lis r18, 0x1c80
|
||||
ori r18, r18, 0xc000
|
||||
/* stw r18, 0x0(r18) */
|
||||
sync
|
||||
blr
|
||||
|
||||
.global led_off1
|
||||
led_off1:
|
||||
xor r18, r18, r18
|
||||
lis r18, 0x1c81
|
||||
ori r18, r18, 0x8000
|
||||
/* stw r18, 0x0(r18) */
|
||||
sync
|
||||
blr
|
||||
|
||||
.global led_on2
|
||||
led_on2:
|
||||
xor r18, r18, r18
|
||||
lis r18, 0x1c81
|
||||
ori r18, r18, 0x0000
|
||||
/* stw r18, 0x0(r18) */
|
||||
sync
|
||||
blr
|
||||
|
||||
.global led_off2
|
||||
led_off2:
|
||||
xor r18, r18, r18
|
||||
lis r18, 0x1c81
|
||||
ori r18, r18, 0xc000
|
||||
/* stw r18, 0x0(r18) */
|
||||
sync
|
||||
blr
|
1013
board/prodrive/p3mx/mpsc.c
Normal file
1013
board/prodrive/p3mx/mpsc.c
Normal file
File diff suppressed because it is too large
Load diff
156
board/prodrive/p3mx/mpsc.h
Normal file
156
board/prodrive/p3mx/mpsc.h
Normal file
|
@ -0,0 +1,156 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* John Clemens <clemens@mclx.com>, Mission Critical Linux, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*************************************************************************
|
||||
* changes for Marvell DB64360 eval board 2003 by Ingo Assmus <ingo.assmus@keymile.com>
|
||||
*
|
||||
************************************************************************/
|
||||
|
||||
|
||||
/*
|
||||
* mpsc.h - header file for MPSC in uart mode (console driver)
|
||||
*/
|
||||
|
||||
#ifndef __MPSC_H__
|
||||
#define __MPSC_H__
|
||||
|
||||
/* include actual Galileo defines */
|
||||
#include "../../Marvell/include/mv_gen_reg.h"
|
||||
|
||||
/* driver related defines */
|
||||
|
||||
int mpsc_init(int baud);
|
||||
void mpsc_sdma_init(void);
|
||||
void mpsc_init2(void);
|
||||
int galbrg_set_baudrate(int channel, int rate);
|
||||
|
||||
int mpsc_putchar_early(char ch);
|
||||
char mpsc_getchar_debug(void);
|
||||
int mpsc_test_char_debug(void);
|
||||
|
||||
int mpsc_test_char_sdma(void);
|
||||
|
||||
extern int (*mpsc_putchar)(char ch);
|
||||
extern char (*mpsc_getchar)(void);
|
||||
extern int (*mpsc_test_char)(void);
|
||||
|
||||
#define CHANNEL CONFIG_MPSC_PORT
|
||||
|
||||
#define TX_DESC 5
|
||||
#define RX_DESC 20
|
||||
|
||||
#define DESC_FIRST 0x00010000
|
||||
#define DESC_LAST 0x00020000
|
||||
#define DESC_OWNER_BIT 0x80000000
|
||||
|
||||
#define TX_DEMAND 0x00800000
|
||||
#define TX_STOP 0x00010000
|
||||
#define RX_ENABLE 0x00000080
|
||||
|
||||
#define SDMA_RX_ABORT (1 << 15)
|
||||
#define SDMA_TX_ABORT (1 << 31)
|
||||
#define MPSC_TX_ABORT (1 << 7)
|
||||
#define MPSC_RX_ABORT (1 << 23)
|
||||
#define MPSC_ENTER_HUNT (1 << 31)
|
||||
|
||||
/* MPSC defines */
|
||||
|
||||
#define GALMPSC_CONNECT 0x1
|
||||
#define GALMPSC_DISCONNECT 0x0
|
||||
|
||||
#define GALMPSC_UART 0x1
|
||||
|
||||
#define GALMPSC_STOP_BITS_1 0x0
|
||||
#define GALMPSC_STOP_BITS_2 0x1
|
||||
#define GALMPSC_CHAR_LENGTH_8 0x3
|
||||
#define GALMPSC_CHAR_LENGTH_7 0x2
|
||||
|
||||
#define GALMPSC_PARITY_ODD 0x0
|
||||
#define GALMPSC_PARITY_EVEN 0x2
|
||||
#define GALMPSC_PARITY_MARK 0x3
|
||||
#define GALMPSC_PARITY_SPACE 0x1
|
||||
#define GALMPSC_PARITY_NONE -1
|
||||
|
||||
#define GALMPSC_SERIAL_MULTIPLEX SERIAL_PORT_MULTIPLEX /* 0xf010 */
|
||||
#define GALMPSC_ROUTING_REGISTER MAIN_ROUTING_REGISTER /* 0xb400 */
|
||||
#define GALMPSC_RxC_ROUTE RECEIVE_CLOCK_ROUTING_REGISTER /* 0xb404 */
|
||||
#define GALMPSC_TxC_ROUTE TRANSMIT_CLOCK_ROUTING_REGISTER /* 0xb408 */
|
||||
#define GALMPSC_MCONF_LOW MPSC0_MAIN_CONFIGURATION_LOW /* 0x8000 */
|
||||
#define GALMPSC_MCONF_HIGH MPSC0_MAIN_CONFIGURATION_HIGH /* 0x8004 */
|
||||
#define GALMPSC_PROTOCONF_REG MPSC0_PROTOCOL_CONFIGURATION /* 0x8008 */
|
||||
|
||||
#define GALMPSC_REG_GAP 0x1000
|
||||
|
||||
#define GALMPSC_MCONF_CHREG_BASE CHANNEL0_REGISTER1 /* 0x800c */
|
||||
#define GALMPSC_CHANNELREG_1 CHANNEL0_REGISTER1 /* 0x800c */
|
||||
#define GALMPSC_CHANNELREG_2 CHANNEL0_REGISTER2 /* 0x8010 */
|
||||
#define GALMPSC_CHANNELREG_3 CHANNEL0_REGISTER3 /* 0x8014 */
|
||||
#define GALMPSC_CHANNELREG_4 CHANNEL0_REGISTER4 /* 0x8018 */
|
||||
#define GALMPSC_CHANNELREG_5 CHANNEL0_REGISTER5 /* 0x801c */
|
||||
#define GALMPSC_CHANNELREG_6 CHANNEL0_REGISTER6 /* 0x8020 */
|
||||
#define GALMPSC_CHANNELREG_7 CHANNEL0_REGISTER7 /* 0x8024 */
|
||||
#define GALMPSC_CHANNELREG_8 CHANNEL0_REGISTER8 /* 0x8028 */
|
||||
#define GALMPSC_CHANNELREG_9 CHANNEL0_REGISTER9 /* 0x802c */
|
||||
#define GALMPSC_CHANNELREG_10 CHANNEL0_REGISTER10 /* 0x8030 */
|
||||
#define GALMPSC_CHANNELREG_11 CHANNEL0_REGISTER11 /* 0x8034 */
|
||||
|
||||
#define GALSDMA_COMMAND_FIRST (1 << 16)
|
||||
#define GALSDMA_COMMAND_LAST (1 << 17)
|
||||
#define GALSDMA_COMMAND_ENABLEINT (1 << 23)
|
||||
#define GALSDMA_COMMAND_AUTO (1 << 30)
|
||||
#define GALSDMA_COMMAND_OWNER (1 << 31)
|
||||
|
||||
#define GALSDMA_RX 0
|
||||
#define GALSDMA_TX 1
|
||||
|
||||
/* CHANNEL2 should be CHANNEL1, according to documentation,
|
||||
* but to work with the current GTREGS file...
|
||||
*/
|
||||
#define GALSDMA_0_CONF_REG CHANNEL0_CONFIGURATION_REGISTER /* 0x4000 */
|
||||
#define GALSDMA_1_CONF_REG CHANNEL2_CONFIGURATION_REGISTER /* 0x6000 */
|
||||
#define GALSDMA_0_COM_REG CHANNEL0_COMMAND_REGISTER /* 0x4008 */
|
||||
#define GALSDMA_1_COM_REG CHANNEL2_COMMAND_REGISTER /* 0x6008 */
|
||||
#define GALSDMA_0_CUR_RX_PTR CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER /* 0x4810 */
|
||||
#define GALSDMA_0_CUR_TX_PTR CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER /* 0x4c10 */
|
||||
#define GALSDMA_0_FIR_TX_PTR CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER /* 0x4c14 */
|
||||
#define GALSDMA_1_CUR_RX_PTR CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER /* 0x6810 */
|
||||
#define GALSDMA_1_CUR_TX_PTR CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER /* 0x6c10 */
|
||||
#define GALSDMA_1_FIR_TX_PTR CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER /* 0x6c14 */
|
||||
#define GALSDMA_REG_DIFF 0x2000
|
||||
|
||||
/* WRONG in gt64260R.h */
|
||||
#define GALSDMA_INT_CAUSE 0xb800 /* SDMA_CAUSE */
|
||||
#define GALSDMA_INT_MASK 0xb880 /* SDMA_MASK */
|
||||
#define GALMPSC_0_INT_CAUSE 0xb804
|
||||
#define GALMPSC_0_INT_MASK 0xb884
|
||||
|
||||
#define GALSDMA_MODE_UART 0
|
||||
#define GALSDMA_MODE_BISYNC 1
|
||||
#define GALSDMA_MODE_HDLC 2
|
||||
#define GALSDMA_MODE_TRANSPARENT 3
|
||||
|
||||
#define GALBRG_0_CONFREG BRG0_CONFIGURATION_REGISTER /* 0xb200 */
|
||||
#define GALBRG_REG_GAP 0x0008
|
||||
#define GALBRG_0_BTREG BRG0_BAUDE_TUNING_REGISTER /* 0xb204 */
|
||||
|
||||
#endif /* __MPSC_H__ */
|
3344
board/prodrive/p3mx/mv_eth.c
Normal file
3344
board/prodrive/p3mx/mv_eth.c
Normal file
File diff suppressed because it is too large
Load diff
840
board/prodrive/p3mx/mv_eth.h
Normal file
840
board/prodrive/p3mx/mv_eth.h
Normal file
|
@ -0,0 +1,840 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Ingo Assmus <ingo.assmus@keymile.com>
|
||||
*
|
||||
* based on - Driver for MV64460X ethernet ports
|
||||
* Copyright (C) 2002 rabeeh@galileo.co.il
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* mv_eth.h - header file for the polled mode GT ethernet driver
|
||||
*/
|
||||
|
||||
#ifndef __DB64460_ETH_H__
|
||||
#define __DB64460_ETH_H__
|
||||
|
||||
#include <asm/types.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/byteorder.h>
|
||||
#include <common.h>
|
||||
#include <net.h>
|
||||
#include "mv_regs.h"
|
||||
#include "ppc_error_no.h"
|
||||
#include "../../Marvell/include/core.h"
|
||||
|
||||
/*************************************************************************
|
||||
**************************************************************************
|
||||
**************************************************************************
|
||||
* The first part is the high level driver of the gigE ethernet ports. *
|
||||
**************************************************************************
|
||||
**************************************************************************
|
||||
*************************************************************************/
|
||||
#ifndef TRUE
|
||||
#define TRUE 1
|
||||
#endif
|
||||
#ifndef FALSE
|
||||
#define FALSE 0
|
||||
#endif
|
||||
|
||||
/* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
|
||||
#ifndef MAX_SKB_FRAGS
|
||||
#define MAX_SKB_FRAGS 0
|
||||
#endif
|
||||
|
||||
/* Port attributes */
|
||||
/*#define MAX_RX_QUEUE_NUM 8*/
|
||||
/*#define MAX_TX_QUEUE_NUM 8*/
|
||||
#define MAX_RX_QUEUE_NUM 1
|
||||
#define MAX_TX_QUEUE_NUM 1
|
||||
|
||||
|
||||
/* Use one TX queue and one RX queue */
|
||||
#define MV64460_TX_QUEUE_NUM 1
|
||||
#define MV64460_RX_QUEUE_NUM 1
|
||||
|
||||
/*
|
||||
* Number of RX / TX descriptors on RX / TX rings.
|
||||
* Note that allocating RX descriptors is done by allocating the RX
|
||||
* ring AND a preallocated RX buffers (skb's) for each descriptor.
|
||||
* The TX descriptors only allocates the TX descriptors ring,
|
||||
* with no pre allocated TX buffers (skb's are allocated by higher layers.
|
||||
*/
|
||||
|
||||
/* Default TX ring size is 10 descriptors */
|
||||
#ifdef CONFIG_MV64460_ETH_TXQUEUE_SIZE
|
||||
#define MV64460_TX_QUEUE_SIZE CONFIG_MV64460_ETH_TXQUEUE_SIZE
|
||||
#else
|
||||
#define MV64460_TX_QUEUE_SIZE 4
|
||||
#endif
|
||||
|
||||
/* Default RX ring size is 4 descriptors */
|
||||
#ifdef CONFIG_MV64460_ETH_RXQUEUE_SIZE
|
||||
#define MV64460_RX_QUEUE_SIZE CONFIG_MV64460_ETH_RXQUEUE_SIZE
|
||||
#else
|
||||
#define MV64460_RX_QUEUE_SIZE 4
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_RX_BUFFER_SIZE
|
||||
#define MV64460_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
|
||||
#else
|
||||
#define MV64460_RX_BUFFER_SIZE 1600
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TX_BUFFER_SIZE
|
||||
#define MV64460_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
|
||||
#else
|
||||
#define MV64460_TX_BUFFER_SIZE 1600
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Network device statistics. Akin to the 2.0 ether stats but
|
||||
* with byte counters.
|
||||
*/
|
||||
|
||||
struct net_device_stats
|
||||
{
|
||||
unsigned long rx_packets; /* total packets received */
|
||||
unsigned long tx_packets; /* total packets transmitted */
|
||||
unsigned long rx_bytes; /* total bytes received */
|
||||
unsigned long tx_bytes; /* total bytes transmitted */
|
||||
unsigned long rx_errors; /* bad packets received */
|
||||
unsigned long tx_errors; /* packet transmit problems */
|
||||
unsigned long rx_dropped; /* no space in linux buffers */
|
||||
unsigned long tx_dropped; /* no space available in linux */
|
||||
unsigned long multicast; /* multicast packets received */
|
||||
unsigned long collisions;
|
||||
|
||||
/* detailed rx_errors: */
|
||||
unsigned long rx_length_errors;
|
||||
unsigned long rx_over_errors; /* receiver ring buff overflow */
|
||||
unsigned long rx_crc_errors; /* recved pkt with crc error */
|
||||
unsigned long rx_frame_errors; /* recv'd frame alignment error */
|
||||
unsigned long rx_fifo_errors; /* recv'r fifo overrun */
|
||||
unsigned long rx_missed_errors; /* receiver missed packet */
|
||||
|
||||
/* detailed tx_errors */
|
||||
unsigned long tx_aborted_errors;
|
||||
unsigned long tx_carrier_errors;
|
||||
unsigned long tx_fifo_errors;
|
||||
unsigned long tx_heartbeat_errors;
|
||||
unsigned long tx_window_errors;
|
||||
|
||||
/* for cslip etc */
|
||||
unsigned long rx_compressed;
|
||||
unsigned long tx_compressed;
|
||||
};
|
||||
|
||||
|
||||
/* Private data structure used for ethernet device */
|
||||
struct mv64460_eth_priv {
|
||||
unsigned int port_num;
|
||||
struct net_device_stats *stats;
|
||||
|
||||
/* to buffer area aligned */
|
||||
char * p_eth_tx_buffer[MV64460_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */
|
||||
char * p_eth_rx_buffer[MV64460_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */
|
||||
|
||||
/* Size of Tx Ring per queue */
|
||||
unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
|
||||
|
||||
/* Size of Rx Ring per queue */
|
||||
unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
|
||||
|
||||
/* Magic Number for Ethernet running */
|
||||
unsigned int eth_running;
|
||||
|
||||
int first_init;
|
||||
};
|
||||
|
||||
int mv64460_eth_init (struct eth_device *dev);
|
||||
int mv64460_eth_stop (struct eth_device *dev);
|
||||
int mv64460_eth_start_xmit (struct eth_device*, volatile void* packet, int length);
|
||||
/* return db64460_eth0_poll(); */
|
||||
|
||||
int mv64460_eth_open (struct eth_device *dev);
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
**************************************************************************
|
||||
**************************************************************************
|
||||
* The second part is the low level driver of the gigE ethernet ports. *
|
||||
**************************************************************************
|
||||
**************************************************************************
|
||||
*************************************************************************/
|
||||
|
||||
|
||||
/********************************************************************************
|
||||
* Header File for : MV-643xx network interface header
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* This header file contains macros typedefs and function declaration for
|
||||
* the Marvell Gig Bit Ethernet Controller.
|
||||
*
|
||||
* DEPENDENCIES:
|
||||
* None.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
#ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
|
||||
#ifdef CONFIG_MV64460_SRAM_CACHEABLE
|
||||
/* In case SRAM is cacheable but not cache coherent */
|
||||
#define D_CACHE_FLUSH_LINE(addr, offset) \
|
||||
{ \
|
||||
__asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
|
||||
}
|
||||
#else
|
||||
/* In case SRAM is cache coherent or non-cacheable */
|
||||
#define D_CACHE_FLUSH_LINE(addr, offset) ;
|
||||
#endif
|
||||
#else
|
||||
#ifdef CONFIG_NOT_COHERENT_CACHE
|
||||
/* In case of descriptors on DDR but not cache coherent */
|
||||
#define D_CACHE_FLUSH_LINE(addr, offset) \
|
||||
{ \
|
||||
__asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
|
||||
}
|
||||
#else
|
||||
/* In case of descriptors on DDR and cache coherent */
|
||||
#define D_CACHE_FLUSH_LINE(addr, offset) ;
|
||||
#endif /* CONFIG_NOT_COHERENT_CACHE */
|
||||
#endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
|
||||
|
||||
|
||||
#define CPU_PIPE_FLUSH \
|
||||
{ \
|
||||
__asm__ __volatile__ ("eieio"); \
|
||||
}
|
||||
|
||||
|
||||
/* defines */
|
||||
|
||||
/* Default port configuration value */
|
||||
#define PORT_CONFIG_VALUE \
|
||||
ETH_UNICAST_NORMAL_MODE | \
|
||||
ETH_DEFAULT_RX_QUEUE_0 | \
|
||||
ETH_DEFAULT_RX_ARP_QUEUE_0 | \
|
||||
ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
|
||||
ETH_RECEIVE_BC_IF_IP | \
|
||||
ETH_RECEIVE_BC_IF_ARP | \
|
||||
ETH_CAPTURE_TCP_FRAMES_DIS | \
|
||||
ETH_CAPTURE_UDP_FRAMES_DIS | \
|
||||
ETH_DEFAULT_RX_TCP_QUEUE_0 | \
|
||||
ETH_DEFAULT_RX_UDP_QUEUE_0 | \
|
||||
ETH_DEFAULT_RX_BPDU_QUEUE_0
|
||||
|
||||
/* Default port extend configuration value */
|
||||
#define PORT_CONFIG_EXTEND_VALUE \
|
||||
ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
|
||||
ETH_PARTITION_DISABLE
|
||||
|
||||
|
||||
/* Default sdma control value */
|
||||
#ifdef CONFIG_NOT_COHERENT_CACHE
|
||||
#define PORT_SDMA_CONFIG_VALUE \
|
||||
ETH_RX_BURST_SIZE_16_64BIT | \
|
||||
GT_ETH_IPG_INT_RX(0) | \
|
||||
ETH_TX_BURST_SIZE_16_64BIT;
|
||||
#else
|
||||
#define PORT_SDMA_CONFIG_VALUE \
|
||||
ETH_RX_BURST_SIZE_4_64BIT | \
|
||||
GT_ETH_IPG_INT_RX(0) | \
|
||||
ETH_TX_BURST_SIZE_4_64BIT;
|
||||
#endif
|
||||
|
||||
#define GT_ETH_IPG_INT_RX(value) \
|
||||
((value & 0x3fff) << 8)
|
||||
|
||||
/* Default port serial control value */
|
||||
#define PORT_SERIAL_CONTROL_VALUE \
|
||||
ETH_FORCE_LINK_PASS | \
|
||||
ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
|
||||
ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
|
||||
ETH_ADV_SYMMETRIC_FLOW_CTRL | \
|
||||
ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
|
||||
ETH_FORCE_BP_MODE_NO_JAM | \
|
||||
BIT9 | \
|
||||
ETH_DO_NOT_FORCE_LINK_FAIL | \
|
||||
ETH_RETRANSMIT_16_ETTEMPTS | \
|
||||
ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
|
||||
ETH_DTE_ADV_0 | \
|
||||
ETH_DISABLE_AUTO_NEG_BYPASS | \
|
||||
ETH_AUTO_NEG_NO_CHANGE | \
|
||||
ETH_MAX_RX_PACKET_1552BYTE | \
|
||||
ETH_CLR_EXT_LOOPBACK | \
|
||||
ETH_SET_FULL_DUPLEX_MODE | \
|
||||
ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
|
||||
|
||||
#define RX_BUFFER_MAX_SIZE 0xFFFF
|
||||
#define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */
|
||||
|
||||
#define RX_BUFFER_MIN_SIZE 0x8
|
||||
#define TX_BUFFER_MIN_SIZE 0x8
|
||||
|
||||
/* Tx WRR confoguration macros */
|
||||
#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
|
||||
#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */
|
||||
#define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */
|
||||
|
||||
/* MAC accepet/reject macros */
|
||||
#define ACCEPT_MAC_ADDR 0
|
||||
#define REJECT_MAC_ADDR 1
|
||||
|
||||
/* Size of a Tx/Rx descriptor used in chain list data structure */
|
||||
#define RX_DESC_ALIGNED_SIZE 0x20
|
||||
#define TX_DESC_ALIGNED_SIZE 0x20
|
||||
|
||||
/* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
|
||||
#define TX_BUF_OFFSET_IN_DESC 0x18
|
||||
/* Buffer offset from buffer pointer */
|
||||
#define RX_BUF_OFFSET 0x2
|
||||
|
||||
/* Gap define */
|
||||
#define ETH_BAR_GAP 0x8
|
||||
#define ETH_SIZE_REG_GAP 0x8
|
||||
#define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4
|
||||
#define ETH_PORT_ACCESS_CTRL_GAP 0x4
|
||||
|
||||
/* Gigabit Ethernet Unit Global Registers */
|
||||
|
||||
/* MIB Counters register definitions */
|
||||
#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
|
||||
#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
|
||||
#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
|
||||
#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
|
||||
#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
|
||||
#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
|
||||
#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
|
||||
#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
|
||||
#define ETH_MIB_FRAMES_64_OCTETS 0x20
|
||||
#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
|
||||
#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
|
||||
#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
|
||||
#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
|
||||
#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
|
||||
#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
|
||||
#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
|
||||
#define ETH_MIB_GOOD_FRAMES_SENT 0x40
|
||||
#define ETH_MIB_EXCESSIVE_COLLISION 0x44
|
||||
#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
|
||||
#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
|
||||
#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
|
||||
#define ETH_MIB_FC_SENT 0x54
|
||||
#define ETH_MIB_GOOD_FC_RECEIVED 0x58
|
||||
#define ETH_MIB_BAD_FC_RECEIVED 0x5c
|
||||
#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
|
||||
#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
|
||||
#define ETH_MIB_OVERSIZE_RECEIVED 0x68
|
||||
#define ETH_MIB_JABBER_RECEIVED 0x6c
|
||||
#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
|
||||
#define ETH_MIB_BAD_CRC_EVENT 0x74
|
||||
#define ETH_MIB_COLLISION 0x78
|
||||
#define ETH_MIB_LATE_COLLISION 0x7c
|
||||
|
||||
/* Port serial status reg (PSR) */
|
||||
#define ETH_INTERFACE_GMII_MII 0
|
||||
#define ETH_INTERFACE_PCM BIT0
|
||||
#define ETH_LINK_IS_DOWN 0
|
||||
#define ETH_LINK_IS_UP BIT1
|
||||
#define ETH_PORT_AT_HALF_DUPLEX 0
|
||||
#define ETH_PORT_AT_FULL_DUPLEX BIT2
|
||||
#define ETH_RX_FLOW_CTRL_DISABLED 0
|
||||
#define ETH_RX_FLOW_CTRL_ENBALED BIT3
|
||||
#define ETH_GMII_SPEED_100_10 0
|
||||
#define ETH_GMII_SPEED_1000 BIT4
|
||||
#define ETH_MII_SPEED_10 0
|
||||
#define ETH_MII_SPEED_100 BIT5
|
||||
#define ETH_NO_TX 0
|
||||
#define ETH_TX_IN_PROGRESS BIT7
|
||||
#define ETH_BYPASS_NO_ACTIVE 0
|
||||
#define ETH_BYPASS_ACTIVE BIT8
|
||||
#define ETH_PORT_NOT_AT_PARTITION_STATE 0
|
||||
#define ETH_PORT_AT_PARTITION_STATE BIT9
|
||||
#define ETH_PORT_TX_FIFO_NOT_EMPTY 0
|
||||
#define ETH_PORT_TX_FIFO_EMPTY BIT10
|
||||
|
||||
|
||||
/* These macros describes the Port configuration reg (Px_cR) bits */
|
||||
#define ETH_UNICAST_NORMAL_MODE 0
|
||||
#define ETH_UNICAST_PROMISCUOUS_MODE BIT0
|
||||
#define ETH_DEFAULT_RX_QUEUE_0 0
|
||||
#define ETH_DEFAULT_RX_QUEUE_1 BIT1
|
||||
#define ETH_DEFAULT_RX_QUEUE_2 BIT2
|
||||
#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1)
|
||||
#define ETH_DEFAULT_RX_QUEUE_4 BIT3
|
||||
#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1)
|
||||
#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2)
|
||||
#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1)
|
||||
#define ETH_DEFAULT_RX_ARP_QUEUE_0 0
|
||||
#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4
|
||||
#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5
|
||||
#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4)
|
||||
#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6
|
||||
#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4)
|
||||
#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5)
|
||||
#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4)
|
||||
#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
|
||||
#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7
|
||||
#define ETH_RECEIVE_BC_IF_IP 0
|
||||
#define ETH_REJECT_BC_IF_IP BIT8
|
||||
#define ETH_RECEIVE_BC_IF_ARP 0
|
||||
#define ETH_REJECT_BC_IF_ARP BIT9
|
||||
#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12
|
||||
#define ETH_CAPTURE_TCP_FRAMES_DIS 0
|
||||
#define ETH_CAPTURE_TCP_FRAMES_EN BIT14
|
||||
#define ETH_CAPTURE_UDP_FRAMES_DIS 0
|
||||
#define ETH_CAPTURE_UDP_FRAMES_EN BIT15
|
||||
#define ETH_DEFAULT_RX_TCP_QUEUE_0 0
|
||||
#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16
|
||||
#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17
|
||||
#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16)
|
||||
#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18
|
||||
#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16)
|
||||
#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17)
|
||||
#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16)
|
||||
#define ETH_DEFAULT_RX_UDP_QUEUE_0 0
|
||||
#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19
|
||||
#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20
|
||||
#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19)
|
||||
#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21
|
||||
#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19)
|
||||
#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20)
|
||||
#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19)
|
||||
#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0
|
||||
#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22
|
||||
#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23
|
||||
#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
|
||||
#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
|
||||
#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
|
||||
#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
|
||||
#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
|
||||
|
||||
|
||||
/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
|
||||
#define ETH_CLASSIFY_EN BIT0
|
||||
#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
|
||||
#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1
|
||||
#define ETH_PARTITION_DISABLE 0
|
||||
#define ETH_PARTITION_ENABLE BIT2
|
||||
|
||||
|
||||
/* Tx/Rx queue command reg (RQCR/TQCR)*/
|
||||
#define ETH_QUEUE_0_ENABLE BIT0
|
||||
#define ETH_QUEUE_1_ENABLE BIT1
|
||||
#define ETH_QUEUE_2_ENABLE BIT2
|
||||
#define ETH_QUEUE_3_ENABLE BIT3
|
||||
#define ETH_QUEUE_4_ENABLE BIT4
|
||||
#define ETH_QUEUE_5_ENABLE BIT5
|
||||
#define ETH_QUEUE_6_ENABLE BIT6
|
||||
#define ETH_QUEUE_7_ENABLE BIT7
|
||||
#define ETH_QUEUE_0_DISABLE BIT8
|
||||
#define ETH_QUEUE_1_DISABLE BIT9
|
||||
#define ETH_QUEUE_2_DISABLE BIT10
|
||||
#define ETH_QUEUE_3_DISABLE BIT11
|
||||
#define ETH_QUEUE_4_DISABLE BIT12
|
||||
#define ETH_QUEUE_5_DISABLE BIT13
|
||||
#define ETH_QUEUE_6_DISABLE BIT14
|
||||
#define ETH_QUEUE_7_DISABLE BIT15
|
||||
|
||||
/* These macros describes the Port Sdma configuration reg (SDCR) bits */
|
||||
#define ETH_RIFB BIT0
|
||||
#define ETH_RX_BURST_SIZE_1_64BIT 0
|
||||
#define ETH_RX_BURST_SIZE_2_64BIT BIT1
|
||||
#define ETH_RX_BURST_SIZE_4_64BIT BIT2
|
||||
#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1)
|
||||
#define ETH_RX_BURST_SIZE_16_64BIT BIT3
|
||||
#define ETH_BLM_RX_NO_SWAP BIT4
|
||||
#define ETH_BLM_RX_BYTE_SWAP 0
|
||||
#define ETH_BLM_TX_NO_SWAP BIT5
|
||||
#define ETH_BLM_TX_BYTE_SWAP 0
|
||||
#define ETH_DESCRIPTORS_BYTE_SWAP BIT6
|
||||
#define ETH_DESCRIPTORS_NO_SWAP 0
|
||||
#define ETH_TX_BURST_SIZE_1_64BIT 0
|
||||
#define ETH_TX_BURST_SIZE_2_64BIT BIT22
|
||||
#define ETH_TX_BURST_SIZE_4_64BIT BIT23
|
||||
#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22)
|
||||
#define ETH_TX_BURST_SIZE_16_64BIT BIT24
|
||||
|
||||
/* These macros describes the Port serial control reg (PSCR) bits */
|
||||
#define ETH_SERIAL_PORT_DISABLE 0
|
||||
#define ETH_SERIAL_PORT_ENABLE BIT0
|
||||
#define ETH_FORCE_LINK_PASS BIT1
|
||||
#define ETH_DO_NOT_FORCE_LINK_PASS 0
|
||||
#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
|
||||
#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2
|
||||
#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
|
||||
#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3
|
||||
#define ETH_ADV_NO_FLOW_CTRL 0
|
||||
#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4
|
||||
#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
|
||||
#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5
|
||||
#define ETH_FORCE_BP_MODE_NO_JAM 0
|
||||
#define ETH_FORCE_BP_MODE_JAM_TX BIT7
|
||||
#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8
|
||||
#define ETH_FORCE_LINK_FAIL 0
|
||||
#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10
|
||||
#define ETH_RETRANSMIT_16_ETTEMPTS 0
|
||||
#define ETH_RETRANSMIT_FOREVER BIT11
|
||||
#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13
|
||||
#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
|
||||
#define ETH_DTE_ADV_0 0
|
||||
#define ETH_DTE_ADV_1 BIT14
|
||||
#define ETH_DISABLE_AUTO_NEG_BYPASS 0
|
||||
#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15
|
||||
#define ETH_AUTO_NEG_NO_CHANGE 0
|
||||
#define ETH_RESTART_AUTO_NEG BIT16
|
||||
#define ETH_MAX_RX_PACKET_1518BYTE 0
|
||||
#define ETH_MAX_RX_PACKET_1522BYTE BIT17
|
||||
#define ETH_MAX_RX_PACKET_1552BYTE BIT18
|
||||
#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17)
|
||||
#define ETH_MAX_RX_PACKET_9192BYTE BIT19
|
||||
#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17)
|
||||
#define ETH_SET_EXT_LOOPBACK BIT20
|
||||
#define ETH_CLR_EXT_LOOPBACK 0
|
||||
#define ETH_SET_FULL_DUPLEX_MODE BIT21
|
||||
#define ETH_SET_HALF_DUPLEX_MODE 0
|
||||
#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22
|
||||
#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
|
||||
#define ETH_SET_GMII_SPEED_TO_10_100 0
|
||||
#define ETH_SET_GMII_SPEED_TO_1000 BIT23
|
||||
#define ETH_SET_MII_SPEED_TO_10 0
|
||||
#define ETH_SET_MII_SPEED_TO_100 BIT24
|
||||
|
||||
|
||||
/* SMI reg */
|
||||
#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
|
||||
#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
|
||||
#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */
|
||||
#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
|
||||
|
||||
/* SDMA command status fields macros */
|
||||
|
||||
/* Tx & Rx descriptors status */
|
||||
#define ETH_ERROR_SUMMARY (BIT0)
|
||||
|
||||
/* Tx & Rx descriptors command */
|
||||
#define ETH_BUFFER_OWNED_BY_DMA (BIT31)
|
||||
|
||||
/* Tx descriptors status */
|
||||
#define ETH_LC_ERROR (0 )
|
||||
#define ETH_UR_ERROR (BIT1 )
|
||||
#define ETH_RL_ERROR (BIT2 )
|
||||
#define ETH_LLC_SNAP_FORMAT (BIT9 )
|
||||
|
||||
/* Rx descriptors status */
|
||||
#define ETH_CRC_ERROR (0 )
|
||||
#define ETH_OVERRUN_ERROR (BIT1 )
|
||||
#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
|
||||
#define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
|
||||
#define ETH_VLAN_TAGGED (BIT19)
|
||||
#define ETH_BPDU_FRAME (BIT20)
|
||||
#define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
|
||||
#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
|
||||
#define ETH_OTHER_FRAME_TYPE (BIT22)
|
||||
#define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
|
||||
#define ETH_FRAME_TYPE_IP_V_4 (BIT24)
|
||||
#define ETH_FRAME_HEADER_OK (BIT25)
|
||||
#define ETH_RX_LAST_DESC (BIT26)
|
||||
#define ETH_RX_FIRST_DESC (BIT27)
|
||||
#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
|
||||
#define ETH_RX_ENABLE_INTERRUPT (BIT29)
|
||||
#define ETH_LAYER_4_CHECKSUM_OK (BIT30)
|
||||
|
||||
/* Rx descriptors byte count */
|
||||
#define ETH_FRAME_FRAGMENTED (BIT2)
|
||||
|
||||
/* Tx descriptors command */
|
||||
#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10)
|
||||
#define ETH_FRAME_SET_TO_VLAN (BIT15)
|
||||
#define ETH_TCP_FRAME (0 )
|
||||
#define ETH_UDP_FRAME (BIT16)
|
||||
#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
|
||||
#define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
|
||||
#define ETH_ZERO_PADDING (BIT19)
|
||||
#define ETH_TX_LAST_DESC (BIT20)
|
||||
#define ETH_TX_FIRST_DESC (BIT21)
|
||||
#define ETH_GEN_CRC (BIT22)
|
||||
#define ETH_TX_ENABLE_INTERRUPT (BIT23)
|
||||
#define ETH_AUTO_MODE (BIT30)
|
||||
|
||||
/* Address decode parameters */
|
||||
/* Ethernet Base Address Register bits */
|
||||
#define EBAR_TARGET_DRAM 0x00000000
|
||||
#define EBAR_TARGET_DEVICE 0x00000001
|
||||
#define EBAR_TARGET_CBS 0x00000002
|
||||
#define EBAR_TARGET_PCI0 0x00000003
|
||||
#define EBAR_TARGET_PCI1 0x00000004
|
||||
#define EBAR_TARGET_CUNIT 0x00000005
|
||||
#define EBAR_TARGET_AUNIT 0x00000006
|
||||
#define EBAR_TARGET_GUNIT 0x00000007
|
||||
|
||||
/* Window attributes */
|
||||
#define EBAR_ATTR_DRAM_CS0 0x00000E00
|
||||
#define EBAR_ATTR_DRAM_CS1 0x00000D00
|
||||
#define EBAR_ATTR_DRAM_CS2 0x00000B00
|
||||
#define EBAR_ATTR_DRAM_CS3 0x00000700
|
||||
|
||||
/* DRAM Target interface */
|
||||
#define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000
|
||||
#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000
|
||||
#define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000
|
||||
|
||||
/* Device Bus Target interface */
|
||||
#define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00
|
||||
#define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00
|
||||
#define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00
|
||||
#define EBAR_ATTR_DEVICE_DEVCS3 0x00001700
|
||||
#define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00
|
||||
|
||||
/* PCI Target interface */
|
||||
#define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000
|
||||
#define EBAR_ATTR_PCI_NO_SWAP 0x00000100
|
||||
#define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200
|
||||
#define EBAR_ATTR_PCI_WORD_SWAP 0x00000300
|
||||
#define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
|
||||
#define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400
|
||||
#define EBAR_ATTR_PCI_IO_SPACE 0x00000000
|
||||
#define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800
|
||||
#define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000
|
||||
#define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000
|
||||
|
||||
/* CPU 60x bus or internal SRAM interface */
|
||||
#define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000
|
||||
#define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100
|
||||
#define EBAR_ATTR_CBS_SRAM 0x00000000
|
||||
#define EBAR_ATTR_CBS_CPU_BUS 0x00000800
|
||||
|
||||
/* Window access control */
|
||||
#define EWIN_ACCESS_NOT_ALLOWED 0
|
||||
#define EWIN_ACCESS_READ_ONLY BIT0
|
||||
#define EWIN_ACCESS_FULL (BIT1 | BIT0)
|
||||
#define EWIN0_ACCESS_MASK 0x0003
|
||||
#define EWIN1_ACCESS_MASK 0x000C
|
||||
#define EWIN2_ACCESS_MASK 0x0030
|
||||
#define EWIN3_ACCESS_MASK 0x00C0
|
||||
|
||||
/* typedefs */
|
||||
|
||||
typedef enum _eth_port
|
||||
{
|
||||
ETH_0 = 0,
|
||||
ETH_1 = 1,
|
||||
ETH_2 = 2
|
||||
}ETH_PORT;
|
||||
|
||||
typedef enum _eth_func_ret_status
|
||||
{
|
||||
ETH_OK, /* Returned as expected. */
|
||||
ETH_ERROR, /* Fundamental error. */
|
||||
ETH_RETRY, /* Could not process request. Try later. */
|
||||
ETH_END_OF_JOB, /* Ring has nothing to process. */
|
||||
ETH_QUEUE_FULL, /* Ring resource error. */
|
||||
ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
|
||||
}ETH_FUNC_RET_STATUS;
|
||||
|
||||
typedef enum _eth_queue
|
||||
{
|
||||
ETH_Q0 = 0,
|
||||
ETH_Q1 = 1,
|
||||
ETH_Q2 = 2,
|
||||
ETH_Q3 = 3,
|
||||
ETH_Q4 = 4,
|
||||
ETH_Q5 = 5,
|
||||
ETH_Q6 = 6,
|
||||
ETH_Q7 = 7
|
||||
} ETH_QUEUE;
|
||||
|
||||
typedef enum _addr_win
|
||||
{
|
||||
ETH_WIN0,
|
||||
ETH_WIN1,
|
||||
ETH_WIN2,
|
||||
ETH_WIN3,
|
||||
ETH_WIN4,
|
||||
ETH_WIN5
|
||||
} ETH_ADDR_WIN;
|
||||
|
||||
typedef enum _eth_target
|
||||
{
|
||||
ETH_TARGET_DRAM ,
|
||||
ETH_TARGET_DEVICE,
|
||||
ETH_TARGET_CBS ,
|
||||
ETH_TARGET_PCI0 ,
|
||||
ETH_TARGET_PCI1
|
||||
}ETH_TARGET;
|
||||
|
||||
typedef struct _eth_rx_desc
|
||||
{
|
||||
unsigned short byte_cnt ; /* Descriptor buffer byte count */
|
||||
unsigned short buf_size ; /* Buffer size */
|
||||
unsigned int cmd_sts ; /* Descriptor command status */
|
||||
unsigned int next_desc_ptr; /* Next descriptor pointer */
|
||||
unsigned int buf_ptr ; /* Descriptor buffer pointer */
|
||||
unsigned int return_info ; /* User resource return information */
|
||||
} ETH_RX_DESC;
|
||||
|
||||
|
||||
typedef struct _eth_tx_desc
|
||||
{
|
||||
unsigned short byte_cnt ; /* Descriptor buffer byte count */
|
||||
unsigned short l4i_chk ; /* CPU provided TCP Checksum */
|
||||
unsigned int cmd_sts ; /* Descriptor command status */
|
||||
unsigned int next_desc_ptr; /* Next descriptor pointer */
|
||||
unsigned int buf_ptr ; /* Descriptor buffer pointer */
|
||||
unsigned int return_info ; /* User resource return information */
|
||||
} ETH_TX_DESC;
|
||||
|
||||
/* Unified struct for Rx and Tx operations. The user is not required to */
|
||||
/* be familier with neither Tx nor Rx descriptors. */
|
||||
typedef struct _pkt_info
|
||||
{
|
||||
unsigned short byte_cnt ; /* Descriptor buffer byte count */
|
||||
unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */
|
||||
unsigned int cmd_sts ; /* Descriptor command status */
|
||||
unsigned int buf_ptr ; /* Descriptor buffer pointer */
|
||||
unsigned int return_info ; /* User resource return information */
|
||||
} PKT_INFO;
|
||||
|
||||
|
||||
typedef struct _eth_win_param
|
||||
{
|
||||
ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */
|
||||
ETH_TARGET target; /* System targets. See ETH_TARGET enum */
|
||||
unsigned short attributes; /* BAR attributes. See above macros. */
|
||||
unsigned int base_addr; /* Window base address in unsigned int form */
|
||||
unsigned int high_addr; /* Window high address in unsigned int form */
|
||||
unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
|
||||
bool enable; /* Enable/disable access to the window. */
|
||||
unsigned short access_ctrl; /* Access ctrl register. see above macros */
|
||||
} ETH_WIN_PARAM;
|
||||
|
||||
|
||||
/* Ethernet port specific infomation */
|
||||
|
||||
typedef struct _eth_port_ctrl
|
||||
{
|
||||
ETH_PORT port_num; /* User Ethernet port number */
|
||||
int port_phy_addr; /* User phy address of Ethrnet port */
|
||||
unsigned char port_mac_addr[6]; /* User defined port MAC address. */
|
||||
unsigned int port_config; /* User port configuration value */
|
||||
unsigned int port_config_extend; /* User port config extend value */
|
||||
unsigned int port_sdma_config; /* User port SDMA config value */
|
||||
unsigned int port_serial_control; /* User port serial control value */
|
||||
unsigned int port_tx_queue_command; /* Port active Tx queues summary */
|
||||
unsigned int port_rx_queue_command; /* Port active Rx queues summary */
|
||||
|
||||
/* User function to cast virtual address to CPU bus address */
|
||||
unsigned int (*port_virt_to_phys)(unsigned int addr);
|
||||
/* User scratch pad for user specific data structures */
|
||||
void *port_private;
|
||||
|
||||
bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
|
||||
bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
|
||||
|
||||
/* Tx/Rx rings managment indexes fields. For driver use */
|
||||
|
||||
/* Next available Rx resource */
|
||||
volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
|
||||
/* Returning Rx resource */
|
||||
volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
|
||||
|
||||
/* Next available Tx resource */
|
||||
volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
|
||||
/* Returning Tx resource */
|
||||
volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
|
||||
/* An extra Tx index to support transmit of multiple buffers per packet */
|
||||
volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
|
||||
|
||||
/* Tx/Rx rings size and base variables fields. For driver use */
|
||||
|
||||
volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
|
||||
unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM];
|
||||
char *p_rx_buffer_base[MAX_RX_QUEUE_NUM];
|
||||
|
||||
volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
|
||||
unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM];
|
||||
char *p_tx_buffer_base[MAX_TX_QUEUE_NUM];
|
||||
|
||||
} ETH_PORT_INFO;
|
||||
|
||||
|
||||
/* ethernet.h API list */
|
||||
|
||||
/* Port operation control routines */
|
||||
static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
|
||||
static void eth_port_reset(ETH_PORT eth_port_num);
|
||||
static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
|
||||
|
||||
|
||||
/* Port MAC address routines */
|
||||
static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
|
||||
unsigned char *p_addr,
|
||||
ETH_QUEUE queue);
|
||||
#if 0 /* FIXME */
|
||||
static void eth_port_mc_addr (ETH_PORT eth_port_num,
|
||||
unsigned char *p_addr,
|
||||
ETH_QUEUE queue,
|
||||
int option);
|
||||
#endif
|
||||
|
||||
/* PHY and MIB routines */
|
||||
static bool ethernet_phy_reset(ETH_PORT eth_port_num);
|
||||
|
||||
static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
|
||||
unsigned int phy_reg,
|
||||
unsigned int value);
|
||||
|
||||
static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
|
||||
unsigned int phy_reg,
|
||||
unsigned int* value);
|
||||
|
||||
static void eth_clear_mib_counters(ETH_PORT eth_port_num);
|
||||
|
||||
/* Port data flow control routines */
|
||||
static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl,
|
||||
ETH_QUEUE tx_queue,
|
||||
PKT_INFO *p_pkt_info);
|
||||
static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
|
||||
ETH_QUEUE tx_queue,
|
||||
PKT_INFO *p_pkt_info);
|
||||
static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
|
||||
ETH_QUEUE rx_queue,
|
||||
PKT_INFO *p_pkt_info);
|
||||
static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
|
||||
ETH_QUEUE rx_queue,
|
||||
PKT_INFO *p_pkt_info);
|
||||
|
||||
|
||||
static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
|
||||
ETH_QUEUE tx_queue,
|
||||
int tx_desc_num,
|
||||
int tx_buff_size,
|
||||
unsigned int tx_desc_base_addr,
|
||||
unsigned int tx_buff_base_addr);
|
||||
|
||||
static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
|
||||
ETH_QUEUE rx_queue,
|
||||
int rx_desc_num,
|
||||
int rx_buff_size,
|
||||
unsigned int rx_desc_base_addr,
|
||||
unsigned int rx_buff_base_addr);
|
||||
|
||||
#endif /* MV64460_ETH_ */
|
1125
board/prodrive/p3mx/mv_regs.h
Normal file
1125
board/prodrive/p3mx/mv_regs.h
Normal file
File diff suppressed because it is too large
Load diff
809
board/prodrive/p3mx/p3mx.c
Normal file
809
board/prodrive/p3mx/p3mx.c
Normal file
|
@ -0,0 +1,809 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* Based on original work by
|
||||
* Roel Loeffen, (C) Copyright 2006 Prodrive B.V.
|
||||
* Josh Huber, (C) Copyright 2001 Mission Critical Linux, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
* modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
|
||||
* modifications for the cpci750 by reinhard.arlt@esd-electronics.com
|
||||
* modifications for the P3M750 by roel.loeffen@prodrive.nl
|
||||
*/
|
||||
|
||||
/*
|
||||
* p3m750.c - main board support/init for the Prodrive p3m750/p3m7448.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <74xx_7xx.h>
|
||||
#include "../../Marvell/include/memory.h"
|
||||
#include "../../Marvell/include/pci.h"
|
||||
#include "../../Marvell/include/mv_gen_reg.h"
|
||||
#include <net.h>
|
||||
#include <i2c.h>
|
||||
|
||||
#include "eth.h"
|
||||
#include "mpsc.h"
|
||||
#include "64460.h"
|
||||
#include "mv_regs.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#undef DEBUG
|
||||
/*#define DEBUG */
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#define MAP_PCI
|
||||
#endif /* of CONFIG_PCI */
|
||||
|
||||
#ifdef DEBUG
|
||||
#define DP(x) x
|
||||
#else
|
||||
#define DP(x)
|
||||
#endif
|
||||
|
||||
extern void flush_data_cache (void);
|
||||
extern void invalidate_l1_instruction_cache (void);
|
||||
extern flash_info_t flash_info[];
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/* this is the current GT register space location */
|
||||
/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
|
||||
|
||||
/* Unfortunately, we cant change it while we are in flash, so we initialize it
|
||||
* to the "final" value. This means that any debug_led calls before
|
||||
* board_early_init_f wont work right (like in cpu_init_f).
|
||||
* See also my_remap_gt_regs below. (NTL)
|
||||
*/
|
||||
|
||||
void board_prebootm_init (void);
|
||||
unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
|
||||
int display_mem_map (void);
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* This is a version of the GT register space remapping function that
|
||||
* doesn't touch globals (meaning, it's ok to run from flash.)
|
||||
*
|
||||
* Unfortunately, this has the side effect that a writable
|
||||
* INTERNAL_REG_BASE_ADDR is impossible. Oh well.
|
||||
*/
|
||||
|
||||
void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
|
||||
{
|
||||
u32 temp;
|
||||
|
||||
/* check and see if it's already moved */
|
||||
temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
|
||||
if ((temp & 0xffff) == new_loc >> 16)
|
||||
return;
|
||||
|
||||
temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
|
||||
0xffff0000) | (new_loc >> 16);
|
||||
|
||||
out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
|
||||
|
||||
while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
|
||||
static void gt_pci_config (void)
|
||||
{
|
||||
unsigned int stat;
|
||||
unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, */
|
||||
/* FuncNum 10:8, RegNum 7:2 */
|
||||
|
||||
/*
|
||||
* In PCIX mode devices provide their own bus and device numbers.
|
||||
* We query the Discovery II's
|
||||
* config registers by writing ones to the bus and device.
|
||||
* We then update the Virtual register with the correct value for the
|
||||
* bus and device.
|
||||
*/
|
||||
if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /* if PCI-X */
|
||||
GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
|
||||
|
||||
GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
|
||||
|
||||
GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
|
||||
GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
|
||||
(stat & 0xffff0000) | CFG_PCI_IDSEL);
|
||||
|
||||
}
|
||||
if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /* if PCI-X */
|
||||
GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
|
||||
GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
|
||||
|
||||
GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
|
||||
GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
|
||||
(stat & 0xffff0000) | CFG_PCI_IDSEL);
|
||||
}
|
||||
|
||||
/* Enable master */
|
||||
PCI_MASTER_ENABLE (0, SELF);
|
||||
PCI_MASTER_ENABLE (1, SELF);
|
||||
|
||||
/* Enable PCI0/1 Mem0 and IO 0 disable all others */
|
||||
GT_REG_READ (BASE_ADDR_ENABLE, &stat);
|
||||
stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) |
|
||||
(1 << 18);
|
||||
stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
|
||||
GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
|
||||
|
||||
/* ronen:
|
||||
* add write to pci remap registers for 64460.
|
||||
* in 64360 when writing to pci base go and overide remap automaticaly,
|
||||
* in 64460 it doesn't
|
||||
*/
|
||||
GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_SPACE >> 16);
|
||||
GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_SPACE_PCI >> 16);
|
||||
GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
|
||||
|
||||
GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
|
||||
GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
|
||||
GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
|
||||
|
||||
GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_SPACE >> 16);
|
||||
GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_SPACE_PCI >> 16);
|
||||
GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
|
||||
|
||||
GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
|
||||
GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
|
||||
GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
|
||||
|
||||
/* PCI interface settings */
|
||||
/* Timeout set to retry forever */
|
||||
GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
|
||||
GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
|
||||
|
||||
/* ronen - enable only CS0 and Internal reg!! */
|
||||
GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
|
||||
GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
|
||||
|
||||
/* ronen:
|
||||
* update the pci internal registers base address.
|
||||
*/
|
||||
#ifdef MAP_PCI
|
||||
for (stat = 0; stat <= PCI_HOST1; stat++)
|
||||
pciWriteConfigReg (stat,
|
||||
PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
|
||||
SELF, CFG_GT_REGS);
|
||||
#endif
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Setup CPU interface paramaters */
|
||||
static void gt_cpu_config (void)
|
||||
{
|
||||
cpu_t cpu = get_cpu_type ();
|
||||
ulong tmp;
|
||||
|
||||
/* cpu configuration register */
|
||||
tmp = GTREGREAD (CPU_CONFIGURATION);
|
||||
/* set the SINGLE_CPU bit see MV64460 */
|
||||
#ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
|
||||
tmp |= CPU_CONF_SINGLE_CPU;
|
||||
#endif
|
||||
tmp &= ~CPU_CONF_AACK_DELAY_2;
|
||||
tmp |= CPU_CONF_DP_VALID;
|
||||
tmp |= CPU_CONF_AP_VALID;
|
||||
tmp |= CPU_CONF_PIPELINE;
|
||||
GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */
|
||||
|
||||
/* CPU master control register */
|
||||
tmp = GTREGREAD (CPU_MASTER_CONTROL);
|
||||
tmp |= CPU_MAST_CTL_ARB_EN;
|
||||
|
||||
if ((cpu == CPU_7400) ||
|
||||
(cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
|
||||
|
||||
tmp |= CPU_MAST_CTL_CLEAN_BLK;
|
||||
tmp |= CPU_MAST_CTL_FLUSH_BLK;
|
||||
|
||||
} else {
|
||||
/* cleanblock must be cleared for CPUs
|
||||
* that do not support this command (603e, 750)
|
||||
* see Res#1 */
|
||||
tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
|
||||
tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
|
||||
}
|
||||
GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
|
||||
}
|
||||
|
||||
/*
|
||||
* board_early_init_f.
|
||||
*
|
||||
* set up gal. device mappings, etc.
|
||||
*/
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
/* set up the GT the way the kernel wants it
|
||||
* the call to move the GT register space will obviously
|
||||
* fail if it has already been done, but we're going to assume
|
||||
* that if it's not at the power-on location, it's where we put
|
||||
* it last time. (huber)
|
||||
*/
|
||||
|
||||
my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
gt_pci_config ();
|
||||
#endif
|
||||
/* mask all external interrupt sources */
|
||||
GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
|
||||
GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
|
||||
/* new in >MV6436x */
|
||||
GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
|
||||
GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
|
||||
/* --------------------- */
|
||||
GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
|
||||
GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
|
||||
GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
|
||||
GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
|
||||
|
||||
/* Device and Boot bus settings
|
||||
*/
|
||||
memoryMapDeviceSpace(DEVICE0, 0, 0);
|
||||
GT_REG_WRITE(DEVICE_BANK0PARAMETERS, 0);
|
||||
memoryMapDeviceSpace(DEVICE1, 0, 0);
|
||||
GT_REG_WRITE(DEVICE_BANK1PARAMETERS, 0);
|
||||
memoryMapDeviceSpace(DEVICE2, 0, 0);
|
||||
GT_REG_WRITE(DEVICE_BANK2PARAMETERS, 0);
|
||||
memoryMapDeviceSpace(DEVICE3, 0, 0);
|
||||
GT_REG_WRITE(DEVICE_BANK3PARAMETERS, 0);
|
||||
|
||||
GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_BOOT_PAR);
|
||||
|
||||
gt_cpu_config();
|
||||
|
||||
/* MPP setup */
|
||||
GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
|
||||
GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
|
||||
GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
|
||||
GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
|
||||
|
||||
GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* various things to do after relocation */
|
||||
|
||||
int misc_init_r ()
|
||||
{
|
||||
u8 val;
|
||||
|
||||
icache_enable ();
|
||||
#ifdef CFG_L2
|
||||
l2cache_enable ();
|
||||
#endif
|
||||
#ifdef CONFIG_MPSC
|
||||
mpsc_sdma_init ();
|
||||
mpsc_init2 ();
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Enable trickle changing in RTC upon powerup
|
||||
* No diode, 250 ohm series resistor
|
||||
*/
|
||||
val = 0xa5;
|
||||
i2c_write(CFG_I2C_RTC_ADDR, 8, 1, &val, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_r(void)
|
||||
{
|
||||
/* now relocate the debug serial driver */
|
||||
mpsc_putchar += gd->reloc_off;
|
||||
mpsc_getchar += gd->reloc_off;
|
||||
mpsc_test_char += gd->reloc_off;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void after_reloc (ulong dest_addr, gd_t * gd)
|
||||
{
|
||||
memoryMapDeviceSpace (BOOT_DEVICE, CFG_BOOT_SPACE, CFG_BOOT_SIZE);
|
||||
|
||||
/* display_mem_map(); */
|
||||
|
||||
/* now, jump to the main U-Boot board init code */
|
||||
board_init_r (gd, dest_addr);
|
||||
/* NOTREACHED */
|
||||
}
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
* right now, assume borad type. (there is just one...after all)
|
||||
*/
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
char *s = getenv("serial#");
|
||||
|
||||
printf("Board: %s", CFG_BOARD_NAME);
|
||||
|
||||
if (s != NULL) {
|
||||
puts(", serial# ");
|
||||
puts(s);
|
||||
}
|
||||
putc('\n');
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* utility functions */
|
||||
void debug_led (int led, int mode)
|
||||
{
|
||||
}
|
||||
|
||||
int display_mem_map (void)
|
||||
{
|
||||
int i, j;
|
||||
unsigned int base, size, width;
|
||||
|
||||
/* SDRAM */
|
||||
printf ("SD (DDR) RAM\n");
|
||||
for (i = 0; i <= BANK3; i++) {
|
||||
base = memoryGetBankBaseAddress (i);
|
||||
size = memoryGetBankSize (i);
|
||||
if (size != 0)
|
||||
printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
|
||||
i, base, size >> 20);
|
||||
}
|
||||
#ifdef CONFIG_PCI
|
||||
/* CPU's PCI windows */
|
||||
for (i = 0; i <= PCI_HOST1; i++) {
|
||||
printf ("\nCPU's PCI %d windows\n", i);
|
||||
base = pciGetSpaceBase (i, PCI_IO);
|
||||
size = pciGetSpaceSize (i, PCI_IO);
|
||||
printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base,
|
||||
size >> 20);
|
||||
/* ronen currently only first PCI MEM is used 3 */
|
||||
for (j = 0; j <= PCI_REGION0; j++) {
|
||||
base = pciGetSpaceBase (i, j);
|
||||
size = pciGetSpaceSize (i, j);
|
||||
printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n",
|
||||
j, base, size >> 20);
|
||||
}
|
||||
}
|
||||
#endif /* of CONFIG_PCI */
|
||||
|
||||
/* Bootrom */
|
||||
base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */
|
||||
size = memoryGetDeviceSize (BOOT_DEVICE);
|
||||
width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
|
||||
printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\t- FLASH\n",
|
||||
base, size >> 20, width);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* DRAM check routines copied from gw8260 */
|
||||
|
||||
#if defined (CFG_DRAM_TEST)
|
||||
|
||||
/*********************************************************************/
|
||||
/* NAME: move64() - moves a double word (64-bit) */
|
||||
/* */
|
||||
/* DESCRIPTION: */
|
||||
/* this function performs a double word move from the data at */
|
||||
/* the source pointer to the location at the destination pointer. */
|
||||
/* */
|
||||
/* INPUTS: */
|
||||
/* unsigned long long *src - pointer to data to move */
|
||||
/* */
|
||||
/* OUTPUTS: */
|
||||
/* unsigned long long *dest - pointer to locate to move data */
|
||||
/* */
|
||||
/* RETURNS: */
|
||||
/* None */
|
||||
/* */
|
||||
/* RESTRICTIONS/LIMITATIONS: */
|
||||
/* May cloober fr0. */
|
||||
/* */
|
||||
/*********************************************************************/
|
||||
static void move64 (unsigned long long *src, unsigned long long *dest)
|
||||
{
|
||||
asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
|
||||
"stfd 0, 0(4)" /* *dest = fpr0 */
|
||||
: : : "fr0"); /* Clobbers fr0 */
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
#if defined (CFG_DRAM_TEST_DATA)
|
||||
|
||||
unsigned long long pattern[] = {
|
||||
0xaaaaaaaaaaaaaaaaULL,
|
||||
0xccccccccccccccccULL,
|
||||
0xf0f0f0f0f0f0f0f0ULL,
|
||||
0xff00ff00ff00ff00ULL,
|
||||
0xffff0000ffff0000ULL,
|
||||
0xffffffff00000000ULL,
|
||||
0x00000000ffffffffULL,
|
||||
0x0000ffff0000ffffULL,
|
||||
0x00ff00ff00ff00ffULL,
|
||||
0x0f0f0f0f0f0f0f0fULL,
|
||||
0x3333333333333333ULL,
|
||||
0x5555555555555555ULL
|
||||
};
|
||||
|
||||
/*********************************************************************/
|
||||
/* NAME: mem_test_data() - test data lines for shorts and opens */
|
||||
/* */
|
||||
/* DESCRIPTION: */
|
||||
/* Tests data lines for shorts and opens by forcing adjacent data */
|
||||
/* to opposite states. Because the data lines could be routed in */
|
||||
/* an arbitrary manner the must ensure test patterns ensure that */
|
||||
/* every case is tested. By using the following series of binary */
|
||||
/* patterns every combination of adjacent bits is test regardless */
|
||||
/* of routing. */
|
||||
/* */
|
||||
/* ...101010101010101010101010 */
|
||||
/* ...110011001100110011001100 */
|
||||
/* ...111100001111000011110000 */
|
||||
/* ...111111110000000011111111 */
|
||||
/* */
|
||||
/* Carrying this out, gives us six hex patterns as follows: */
|
||||
/* */
|
||||
/* 0xaaaaaaaaaaaaaaaa */
|
||||
/* 0xcccccccccccccccc */
|
||||
/* 0xf0f0f0f0f0f0f0f0 */
|
||||
/* 0xff00ff00ff00ff00 */
|
||||
/* 0xffff0000ffff0000 */
|
||||
/* 0xffffffff00000000 */
|
||||
/* */
|
||||
/* The number test patterns will always be given by: */
|
||||
/* */
|
||||
/* log(base 2)(number data bits) = log2 (64) = 6 */
|
||||
/* */
|
||||
/* To test for short and opens to other signals on our boards. we */
|
||||
/* simply */
|
||||
/* test with the 1's complemnt of the paterns as well. */
|
||||
/* */
|
||||
/* OUTPUTS: */
|
||||
/* Displays failing test pattern */
|
||||
/* */
|
||||
/* RETURNS: */
|
||||
/* 0 - Passed test */
|
||||
/* 1 - Failed test */
|
||||
/* */
|
||||
/* RESTRICTIONS/LIMITATIONS: */
|
||||
/* Assumes only one one SDRAM bank */
|
||||
/* */
|
||||
/*********************************************************************/
|
||||
int mem_test_data (void)
|
||||
{
|
||||
unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
|
||||
unsigned long long temp64 = 0;
|
||||
int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
|
||||
int i;
|
||||
unsigned int hi, lo;
|
||||
|
||||
for (i = 0; i < num_patterns; i++) {
|
||||
move64 (&(pattern[i]), pmem);
|
||||
move64 (pmem, &temp64);
|
||||
|
||||
/* hi = (temp64>>32) & 0xffffffff; */
|
||||
/* lo = temp64 & 0xffffffff; */
|
||||
/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
|
||||
|
||||
hi = (pattern[i] >> 32) & 0xffffffff;
|
||||
lo = pattern[i] & 0xffffffff;
|
||||
/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
|
||||
|
||||
if (temp64 != pattern[i]) {
|
||||
printf ("\n Data Test Failed, pattern 0x%08x%08x",
|
||||
hi, lo);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CFG_DRAM_TEST_DATA */
|
||||
|
||||
#if defined (CFG_DRAM_TEST_ADDRESS)
|
||||
/*********************************************************************/
|
||||
/* NAME: mem_test_address() - test address lines */
|
||||
/* */
|
||||
/* DESCRIPTION: */
|
||||
/* This function performs a test to verify that each word im */
|
||||
/* memory is uniquly addressable. The test sequence is as follows: */
|
||||
/* */
|
||||
/* 1) write the address of each word to each word. */
|
||||
/* 2) verify that each location equals its address */
|
||||
/* */
|
||||
/* OUTPUTS: */
|
||||
/* Displays failing test pattern and address */
|
||||
/* */
|
||||
/* RETURNS: */
|
||||
/* 0 - Passed test */
|
||||
/* 1 - Failed test */
|
||||
/* */
|
||||
/* RESTRICTIONS/LIMITATIONS: */
|
||||
/* */
|
||||
/* */
|
||||
/*********************************************************************/
|
||||
int mem_test_address (void)
|
||||
{
|
||||
volatile unsigned int *pmem =
|
||||
(volatile unsigned int *) CFG_MEMTEST_START;
|
||||
const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
|
||||
unsigned int i;
|
||||
|
||||
/* write address to each location */
|
||||
for (i = 0; i < size; i++)
|
||||
pmem[i] = i;
|
||||
|
||||
/* verify each loaction */
|
||||
for (i = 0; i < size; i++) {
|
||||
if (pmem[i] != i) {
|
||||
printf ("\n Address Test Failed at 0x%x", i);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif /* CFG_DRAM_TEST_ADDRESS */
|
||||
|
||||
#if defined (CFG_DRAM_TEST_WALK)
|
||||
/*********************************************************************/
|
||||
/* NAME: mem_march() - memory march */
|
||||
/* */
|
||||
/* DESCRIPTION: */
|
||||
/* Marches up through memory. At each location verifies rmask if */
|
||||
/* read = 1. At each location write wmask if write = 1. Displays */
|
||||
/* failing address and pattern. */
|
||||
/* */
|
||||
/* INPUTS: */
|
||||
/* volatile unsigned long long * base - start address of test */
|
||||
/* unsigned int size - number of dwords(64-bit) to test */
|
||||
/* unsigned long long rmask - read verify mask */
|
||||
/* unsigned long long wmask - wrtie verify mask */
|
||||
/* short read - verifies rmask if read = 1 */
|
||||
/* short write - writes wmask if write = 1 */
|
||||
/* */
|
||||
/* OUTPUTS: */
|
||||
/* Displays failing test pattern and address */
|
||||
/* */
|
||||
/* RETURNS: */
|
||||
/* 0 - Passed test */
|
||||
/* 1 - Failed test */
|
||||
/* */
|
||||
/* RESTRICTIONS/LIMITATIONS: */
|
||||
/* */
|
||||
/* */
|
||||
/*********************************************************************/
|
||||
int mem_march (volatile unsigned long long *base,
|
||||
unsigned int size,
|
||||
unsigned long long rmask,
|
||||
unsigned long long wmask, short read, short write)
|
||||
{
|
||||
unsigned int i;
|
||||
unsigned long long temp = 0;
|
||||
unsigned int hitemp, lotemp, himask, lomask;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
if (read != 0) {
|
||||
/* temp = base[i]; */
|
||||
move64 ((unsigned long long *) &(base[i]), &temp);
|
||||
if (rmask != temp) {
|
||||
hitemp = (temp >> 32) & 0xffffffff;
|
||||
lotemp = temp & 0xffffffff;
|
||||
himask = (rmask >> 32) & 0xffffffff;
|
||||
lomask = rmask & 0xffffffff;
|
||||
|
||||
printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
if (write != 0) {
|
||||
/* base[i] = wmask; */
|
||||
move64 (&wmask, (unsigned long long *) &(base[i]));
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif /* CFG_DRAM_TEST_WALK */
|
||||
|
||||
/*********************************************************************/
|
||||
/* NAME: mem_test_walk() - a simple walking ones test */
|
||||
/* */
|
||||
/* DESCRIPTION: */
|
||||
/* Performs a walking ones through entire physical memory. The */
|
||||
/* test uses as series of memory marches, mem_march(), to verify */
|
||||
/* and write the test patterns to memory. The test sequence is as */
|
||||
/* follows: */
|
||||
/* 1) march writing 0000...0001 */
|
||||
/* 2) march verifying 0000...0001 , writing 0000...0010 */
|
||||
/* 3) repeat step 2 shifting masks left 1 bit each time unitl */
|
||||
/* the write mask equals 1000...0000 */
|
||||
/* 4) march verifying 1000...0000 */
|
||||
/* The test fails if any of the memory marches return a failure. */
|
||||
/* */
|
||||
/* OUTPUTS: */
|
||||
/* Displays which pass on the memory test is executing */
|
||||
/* */
|
||||
/* RETURNS: */
|
||||
/* 0 - Passed test */
|
||||
/* 1 - Failed test */
|
||||
/* */
|
||||
/* RESTRICTIONS/LIMITATIONS: */
|
||||
/* */
|
||||
/* */
|
||||
/*********************************************************************/
|
||||
int mem_test_walk (void)
|
||||
{
|
||||
unsigned long long mask;
|
||||
volatile unsigned long long *pmem =
|
||||
(volatile unsigned long long *) CFG_MEMTEST_START;
|
||||
const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
|
||||
|
||||
unsigned int i;
|
||||
|
||||
mask = 0x01;
|
||||
|
||||
printf ("Initial Pass");
|
||||
mem_march (pmem, size, 0x0, 0x1, 0, 1);
|
||||
|
||||
printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
|
||||
printf (" ");
|
||||
printf (" ");
|
||||
printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
|
||||
|
||||
for (i = 0; i < 63; i++) {
|
||||
printf ("Pass %2d", i + 2);
|
||||
if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
|
||||
/*printf("mask: 0x%x, pass: %d, ", mask, i); */
|
||||
return 1;
|
||||
}
|
||||
mask = mask << 1;
|
||||
printf ("\b\b\b\b\b\b\b");
|
||||
}
|
||||
|
||||
printf ("Last Pass");
|
||||
if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
|
||||
/* printf("mask: 0x%x", mask); */
|
||||
return 1;
|
||||
}
|
||||
printf ("\b\b\b\b\b\b\b\b\b");
|
||||
printf (" ");
|
||||
printf ("\b\b\b\b\b\b\b\b\b");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*********************************************************************/
|
||||
/* NAME: testdram() - calls any enabled memory tests */
|
||||
/* */
|
||||
/* DESCRIPTION: */
|
||||
/* Runs memory tests if the environment test variables are set to */
|
||||
/* 'y'. */
|
||||
/* */
|
||||
/* INPUTS: */
|
||||
/* testdramdata - If set to 'y', data test is run. */
|
||||
/* testdramaddress - If set to 'y', address test is run. */
|
||||
/* testdramwalk - If set to 'y', walking ones test is run */
|
||||
/* */
|
||||
/* OUTPUTS: */
|
||||
/* None */
|
||||
/* */
|
||||
/* RETURNS: */
|
||||
/* 0 - Passed test */
|
||||
/* 1 - Failed test */
|
||||
/* */
|
||||
/* RESTRICTIONS/LIMITATIONS: */
|
||||
/* */
|
||||
/* */
|
||||
/*********************************************************************/
|
||||
int testdram (void)
|
||||
{
|
||||
char *s;
|
||||
int rundata = 0;
|
||||
int runaddress = 0;
|
||||
int runwalk = 0;
|
||||
|
||||
#ifdef CFG_DRAM_TEST_DATA
|
||||
s = getenv ("testdramdata");
|
||||
rundata = (s && (*s == 'y')) ? 1 : 0;
|
||||
#endif
|
||||
#ifdef CFG_DRAM_TEST_ADDRESS
|
||||
s = getenv ("testdramaddress");
|
||||
runaddress = (s && (*s == 'y')) ? 1 : 0;
|
||||
#endif
|
||||
#ifdef CFG_DRAM_TEST_WALK
|
||||
s = getenv ("testdramwalk");
|
||||
runwalk = (s && (*s == 'y')) ? 1 : 0;
|
||||
#endif
|
||||
|
||||
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
|
||||
printf ("Testing RAM from 0x%08x to 0x%08x ... "
|
||||
"(don't panic... that will take a moment !!!!)\n",
|
||||
CFG_MEMTEST_START, CFG_MEMTEST_END);
|
||||
#ifdef CFG_DRAM_TEST_DATA
|
||||
if (rundata == 1) {
|
||||
printf ("Test DATA ... ");
|
||||
if (mem_test_data () == 1) {
|
||||
printf ("failed \n");
|
||||
return 1;
|
||||
} else
|
||||
printf ("ok \n");
|
||||
}
|
||||
#endif
|
||||
#ifdef CFG_DRAM_TEST_ADDRESS
|
||||
if (runaddress == 1) {
|
||||
printf ("Test ADDRESS ... ");
|
||||
if (mem_test_address () == 1) {
|
||||
printf ("failed \n");
|
||||
return 1;
|
||||
} else
|
||||
printf ("ok \n");
|
||||
}
|
||||
#endif
|
||||
#ifdef CFG_DRAM_TEST_WALK
|
||||
if (runwalk == 1) {
|
||||
printf ("Test WALKING ONEs ... ");
|
||||
if (mem_test_walk () == 1) {
|
||||
printf ("failed \n");
|
||||
return 1;
|
||||
} else
|
||||
printf ("ok \n");
|
||||
}
|
||||
#endif
|
||||
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
|
||||
printf ("passed\n");
|
||||
return 0;
|
||||
|
||||
}
|
||||
#endif /* CFG_DRAM_TEST */
|
||||
|
||||
/* ronen - the below functions are used by the bootm function */
|
||||
/* - we map the base register to fbe00000 (same mapping as in the LSP) */
|
||||
/* - we turn off the RX gig dmas - to prevent the dma from overunning */
|
||||
/* the kernel data areas. */
|
||||
/* - we diable and invalidate the icache and dcache. */
|
||||
void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
|
||||
{
|
||||
u32 temp;
|
||||
|
||||
temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
|
||||
if ((temp & 0xffff) == new_loc >> 16)
|
||||
return;
|
||||
|
||||
temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
|
||||
0xffff0000) | (new_loc >> 16);
|
||||
|
||||
out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
|
||||
|
||||
while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
|
||||
new_loc |
|
||||
(INTERNAL_SPACE_DECODE)))))
|
||||
!= temp);
|
||||
|
||||
}
|
1025
board/prodrive/p3mx/pci.c
Normal file
1025
board/prodrive/p3mx/pci.c
Normal file
File diff suppressed because it is too large
Load diff
164
board/prodrive/p3mx/ppc_error_no.h
Normal file
164
board/prodrive/p3mx/ppc_error_no.h
Normal file
|
@ -0,0 +1,164 @@
|
|||
/*
|
||||
* (C) Copyright 2003
|
||||
* Ingo Assmus <ingo.assmus@keymile.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* BK Id: SCCS/s.errno.h 1.9 06/05/01 21:45:21 paulus
|
||||
*/
|
||||
#ifndef _MV_PPC_ERRNO_H
|
||||
#define _MV_PPC_ERRNO_H
|
||||
|
||||
#define EPERM 1 /* Operation not permitted */
|
||||
#define ENOENT 2 /* No such file or directory */
|
||||
#define ESRCH 3 /* No such process */
|
||||
#define EINTR 4 /* Interrupted system call */
|
||||
#define EIO 5 /* I/O error */
|
||||
#define ENXIO 6 /* No such device or address */
|
||||
#define E2BIG 7 /* Arg list too long */
|
||||
#define ENOEXEC 8 /* Exec format error */
|
||||
#define EBADF 9 /* Bad file number */
|
||||
#define ECHILD 10 /* No child processes */
|
||||
#define EAGAIN 11 /* Try again */
|
||||
#define ENOMEM 12 /* Out of memory */
|
||||
#define EACCES 13 /* Permission denied */
|
||||
#define EFAULT 14 /* Bad address */
|
||||
#define ENOTBLK 15 /* Block device required */
|
||||
#define EBUSY 16 /* Device or resource busy */
|
||||
#define EEXIST 17 /* File exists */
|
||||
#define EXDEV 18 /* Cross-device link */
|
||||
#define ENODEV 19 /* No such device */
|
||||
#define ENOTDIR 20 /* Not a directory */
|
||||
#define EISDIR 21 /* Is a directory */
|
||||
#define EINVAL 22 /* Invalid argument */
|
||||
#define ENFILE 23 /* File table overflow */
|
||||
#define EMFILE 24 /* Too many open files */
|
||||
#define ENOTTY 25 /* Not a typewriter */
|
||||
#define ETXTBSY 26 /* Text file busy */
|
||||
#define EFBIG 27 /* File too large */
|
||||
#define ENOSPC 28 /* No space left on device */
|
||||
#define ESPIPE 29 /* Illegal seek */
|
||||
#define EROFS 30 /* Read-only file system */
|
||||
#define EMLINK 31 /* Too many links */
|
||||
#define EPIPE 32 /* Broken pipe */
|
||||
#define EDOM 33 /* Math argument out of domain of func */
|
||||
#define ERANGE 34 /* Math result not representable */
|
||||
#define EDEADLK 35 /* Resource deadlock would occur */
|
||||
#define ENAMETOOLONG 36 /* File name too long */
|
||||
#define ENOLCK 37 /* No record locks available */
|
||||
#define ENOSYS 38 /* Function not implemented */
|
||||
#define ENOTEMPTY 39 /* Directory not empty */
|
||||
#define ELOOP 40 /* Too many symbolic links encountered */
|
||||
#define EWOULDBLOCK EAGAIN /* Operation would block */
|
||||
#define ENOMSG 42 /* No message of desired type */
|
||||
#define EIDRM 43 /* Identifier removed */
|
||||
#define ECHRNG 44 /* Channel number out of range */
|
||||
#define EL2NSYNC 45 /* Level 2 not synchronized */
|
||||
#define EL3HLT 46 /* Level 3 halted */
|
||||
#define EL3RST 47 /* Level 3 reset */
|
||||
#define ELNRNG 48 /* Link number out of range */
|
||||
#define EUNATCH 49 /* Protocol driver not attached */
|
||||
#define ENOCSI 50 /* No CSI structure available */
|
||||
#define EL2HLT 51 /* Level 2 halted */
|
||||
#define EBADE 52 /* Invalid exchange */
|
||||
#define EBADR 53 /* Invalid request descriptor */
|
||||
#define EXFULL 54 /* Exchange full */
|
||||
#define ENOANO 55 /* No anode */
|
||||
#define EBADRQC 56 /* Invalid request code */
|
||||
#define EBADSLT 57 /* Invalid slot */
|
||||
#define EDEADLOCK 58 /* File locking deadlock error */
|
||||
#define EBFONT 59 /* Bad font file format */
|
||||
#define ENOSTR 60 /* Device not a stream */
|
||||
#define ENODATA 61 /* No data available */
|
||||
#define ETIME 62 /* Timer expired */
|
||||
#define ENOSR 63 /* Out of streams resources */
|
||||
#define ENONET 64 /* Machine is not on the network */
|
||||
#define ENOPKG 65 /* Package not installed */
|
||||
#define EREMOTE 66 /* Object is remote */
|
||||
#define ENOLINK 67 /* Link has been severed */
|
||||
#define EADV 68 /* Advertise error */
|
||||
#define ESRMNT 69 /* Srmount error */
|
||||
#define ECOMM 70 /* Communication error on send */
|
||||
#define EPROTO 71 /* Protocol error */
|
||||
#define EMULTIHOP 72 /* Multihop attempted */
|
||||
#define EDOTDOT 73 /* RFS specific error */
|
||||
#define EBADMSG 74 /* Not a data message */
|
||||
#define EOVERFLOW 75 /* Value too large for defined data type */
|
||||
#define ENOTUNIQ 76 /* Name not unique on network */
|
||||
#define EBADFD 77 /* File descriptor in bad state */
|
||||
#define EREMCHG 78 /* Remote address changed */
|
||||
#define ELIBACC 79 /* Can not access a needed shared library */
|
||||
#define ELIBBAD 80 /* Accessing a corrupted shared library */
|
||||
#define ELIBSCN 81 /* .lib section in a.out corrupted */
|
||||
#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
|
||||
#define ELIBEXEC 83 /* Cannot exec a shared library directly */
|
||||
#define EILSEQ 84 /* Illegal byte sequence */
|
||||
#define ERESTART 85 /* Interrupted system call should be restarted */
|
||||
#define ESTRPIPE 86 /* Streams pipe error */
|
||||
#define EUSERS 87 /* Too many users */
|
||||
#define ENOTSOCK 88 /* Socket operation on non-socket */
|
||||
#define EDESTADDRREQ 89 /* Destination address required */
|
||||
#define EMSGSIZE 90 /* Message too long */
|
||||
#define EPROTOTYPE 91 /* Protocol wrong type for socket */
|
||||
#define ENOPROTOOPT 92 /* Protocol not available */
|
||||
#define EPROTONOSUPPORT 93 /* Protocol not supported */
|
||||
#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
|
||||
#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
|
||||
#define EPFNOSUPPORT 96 /* Protocol family not supported */
|
||||
#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
|
||||
#define EADDRINUSE 98 /* Address already in use */
|
||||
#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
|
||||
#define ENETDOWN 100 /* Network is down */
|
||||
#define ENETUNREACH 101 /* Network is unreachable */
|
||||
#define ENETRESET 102 /* Network dropped connection because of reset */
|
||||
#define ECONNABORTED 103 /* Software caused connection abort */
|
||||
#define ECONNRESET 104 /* Connection reset by peer */
|
||||
#define ENOBUFS 105 /* No buffer space available */
|
||||
#define EISCONN 106 /* Transport endpoint is already connected */
|
||||
#define ENOTCONN 107 /* Transport endpoint is not connected */
|
||||
#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
|
||||
#define ETOOMANYREFS 109 /* Too many references: cannot splice */
|
||||
#define ETIMEDOUT 110 /* Connection timed out */
|
||||
#define ECONNREFUSED 111 /* Connection refused */
|
||||
#define EHOSTDOWN 112 /* Host is down */
|
||||
#define EHOSTUNREACH 113 /* No route to host */
|
||||
#define EALREADY 114 /* Operation already in progress */
|
||||
#define EINPROGRESS 115 /* Operation now in progress */
|
||||
#define ESTALE 116 /* Stale NFS file handle */
|
||||
#define EUCLEAN 117 /* Structure needs cleaning */
|
||||
#define ENOTNAM 118 /* Not a XENIX named type file */
|
||||
#define ENAVAIL 119 /* No XENIX semaphores available */
|
||||
#define EISNAM 120 /* Is a named type file */
|
||||
#define EREMOTEIO 121 /* Remote I/O error */
|
||||
#define EDQUOT 122 /* Quota exceeded */
|
||||
|
||||
#define ENOMEDIUM 123 /* No medium found */
|
||||
#define EMEDIUMTYPE 124 /* Wrong medium type */
|
||||
|
||||
/* Should never be seen by user programs */
|
||||
#define ERESTARTSYS 512
|
||||
#define ERESTARTNOINTR 513
|
||||
#define ERESTARTNOHAND 514 /* restart if no handler.. */
|
||||
#define ENOIOCTLCMD 515 /* No ioctl command */
|
||||
|
||||
#define _LAST_ERRNO 515
|
||||
|
||||
#endif
|
434
board/prodrive/p3mx/sdram_init.c
Normal file
434
board/prodrive/p3mx/sdram_init.c
Normal file
|
@ -0,0 +1,434 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*************************************************************************
|
||||
* adaption for the Marvell DB64460 Board
|
||||
* Ingo Assmus (ingo.assmus@keymile.com)
|
||||
*************************************************************************/
|
||||
|
||||
/* sdram_init.c - automatic memory sizing */
|
||||
|
||||
#include <common.h>
|
||||
#include <74xx_7xx.h>
|
||||
#include "../../Marvell/include/memory.h"
|
||||
#include "../../Marvell/include/pci.h"
|
||||
#include "../../Marvell/include/mv_gen_reg.h"
|
||||
#include <net.h>
|
||||
|
||||
#include "eth.h"
|
||||
#include "mpsc.h"
|
||||
#include "../../Marvell/common/i2c.h"
|
||||
#include "64460.h"
|
||||
#include "mv_regs.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#undef DEBUG
|
||||
#define MAP_PCI
|
||||
|
||||
#ifdef DEBUG
|
||||
#define DP(x) x
|
||||
#else
|
||||
#define DP(x)
|
||||
#endif
|
||||
|
||||
int set_dfcdlInit (void); /* setup delay line of Mv64460 */
|
||||
int mvDmaIsChannelActive (int);
|
||||
int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong);
|
||||
int mvDmaTransfer (int, ulong, ulong, ulong, ulong);
|
||||
|
||||
#define D_CACHE_FLUSH_LINE(addr, offset) \
|
||||
{ \
|
||||
__asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
|
||||
}
|
||||
|
||||
int memory_map_bank (unsigned int bankNo,
|
||||
unsigned int bankBase, unsigned int bankLength)
|
||||
{
|
||||
#ifdef MAP_PCI
|
||||
PCI_HOST host;
|
||||
#endif
|
||||
|
||||
#ifdef DEBUG
|
||||
if (bankLength > 0) {
|
||||
printf ("mapping bank %d at %08x - %08x\n",
|
||||
bankNo, bankBase, bankBase + bankLength - 1);
|
||||
} else {
|
||||
printf ("unmapping bank %d\n", bankNo);
|
||||
}
|
||||
#endif
|
||||
|
||||
memoryMapBank (bankNo, bankBase, bankLength);
|
||||
|
||||
#ifdef MAP_PCI
|
||||
for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
|
||||
const int features =
|
||||
PREFETCH_ENABLE |
|
||||
DELAYED_READ_ENABLE |
|
||||
AGGRESSIVE_PREFETCH |
|
||||
READ_LINE_AGGRESSIVE_PREFETCH |
|
||||
READ_MULTI_AGGRESSIVE_PREFETCH |
|
||||
MAX_BURST_4 | PCI_NO_SWAP;
|
||||
|
||||
pciMapMemoryBank (host, bankNo, bankBase, bankLength);
|
||||
|
||||
pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
|
||||
bankLength);
|
||||
|
||||
pciSetRegionFeatures (host, bankNo, features, bankBase,
|
||||
bankLength);
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check memory range for valid RAM. A simple memory test determines
|
||||
* the actually available RAM size between addresses `base' and
|
||||
* `base + maxsize'. Some (not all) hardware errors are detected:
|
||||
* - short between address lines
|
||||
* - short between data lines
|
||||
*/
|
||||
long int dram_size (long int *base, long int maxsize)
|
||||
{
|
||||
volatile long int *addr, *b = base;
|
||||
long int cnt, val, save1, save2;
|
||||
|
||||
#define STARTVAL (1<<20) /* start test at 1M */
|
||||
for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
|
||||
cnt <<= 1) {
|
||||
addr = base + cnt; /* pointer arith! */
|
||||
|
||||
save1 = *addr; /* save contents of addr */
|
||||
save2 = *b; /* save contents of base */
|
||||
|
||||
*addr = cnt; /* write cnt to addr */
|
||||
*b = 0; /* put null at base */
|
||||
|
||||
/* check at base address */
|
||||
if ((*b) != 0) {
|
||||
*addr = save1; /* restore *addr */
|
||||
*b = save2; /* restore *b */
|
||||
return (0);
|
||||
}
|
||||
val = *addr; /* read *addr */
|
||||
val = *addr; /* read *addr */
|
||||
|
||||
*addr = save1;
|
||||
*b = save2;
|
||||
|
||||
if (val != cnt) {
|
||||
DP (printf
|
||||
("Found %08x at Address %08x (failure)\n",
|
||||
(unsigned int) val, (unsigned int) addr));
|
||||
/* fix boundary condition.. STARTVAL means zero */
|
||||
if (cnt == STARTVAL / sizeof (long))
|
||||
cnt = 0;
|
||||
return (cnt * sizeof (long));
|
||||
}
|
||||
}
|
||||
|
||||
return maxsize;
|
||||
}
|
||||
|
||||
#define SDRAM_NORMAL 0x0
|
||||
#define SDRAM_PRECHARGE_ALL 0x1
|
||||
#define SDRAM_REFRESH_ALL 0x2
|
||||
#define SDRAM_MODE_REG_SETUP 0x3
|
||||
#define SDRAM_XTEN_MODE_REG_SETUP 0x4
|
||||
#define SDRAM_NOP 0x5
|
||||
#define SDRAM_SELF_REFRESH 0x7
|
||||
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
int tmp;
|
||||
int start;
|
||||
ulong size;
|
||||
ulong memSpaceAttr;
|
||||
ulong dest;
|
||||
|
||||
/* first disable all banks */
|
||||
memory_map_bank(0, 0, 0);
|
||||
memory_map_bank(1, 0, 0);
|
||||
memory_map_bank(2, 0, 0);
|
||||
memory_map_bank(3, 0, 0);
|
||||
|
||||
/* calibrate delay lines */
|
||||
set_dfcdlInit();
|
||||
|
||||
GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_NOP); /* 0x1418 */
|
||||
do {
|
||||
tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
|
||||
} while(tmp != 0x0);
|
||||
|
||||
/* SDRAM controller configuration */
|
||||
#ifdef CONFIG_MV64460_ECC
|
||||
GT_REG_WRITE(MV64460_SDRAM_CONFIG, 0x58201400); /* 0x1400 */
|
||||
#else
|
||||
GT_REG_WRITE(MV64460_SDRAM_CONFIG, 0x58200400); /* 0x1400 */
|
||||
#endif
|
||||
GT_REG_WRITE(MV64460_D_UNIT_CONTROL_LOW, 0xC3000540); /* 0x1404 */
|
||||
GT_REG_WRITE(MV64460_D_UNIT_CONTROL_HIGH, 0x0300F777); /* 0x1424 */
|
||||
GT_REG_WRITE(MV64460_SDRAM_TIMING_CONTROL_LOW, 0x01712220); /* 0x1408 */
|
||||
GT_REG_WRITE(MV64460_SDRAM_TIMING_CONTROL_HIGH, 0x0000005D); /* 0x140C */
|
||||
GT_REG_WRITE(MV64460_SDRAM_ADDR_CONTROL, 0x00000012); /* 0x1410 */
|
||||
GT_REG_WRITE(MV64460_SDRAM_OPEN_PAGES_CONTROL, 0x00000001); /* 0x1414 */
|
||||
|
||||
/* SDRAM drive strength */
|
||||
GT_REG_WRITE(MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x80000000); /* 0x14C0 */
|
||||
GT_REG_WRITE(MV64460_SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x80000008); /* 0x14C0 */
|
||||
GT_REG_WRITE(MV64460_SDRAM_DATA_PADS_CALIBRATION, 0x80000000); /* 0x14C4 */
|
||||
GT_REG_WRITE(MV64460_SDRAM_DATA_PADS_CALIBRATION, 0x80000008); /* 0x14C4 */
|
||||
|
||||
/* setup SDRAM device registers */
|
||||
|
||||
/* precharge all */
|
||||
GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_PRECHARGE_ALL); /* 0x1418 */
|
||||
do {
|
||||
tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
|
||||
} while(tmp != 0x0);
|
||||
|
||||
/* enable DLL */
|
||||
GT_REG_WRITE(MV64460_EXTENDED_DRAM_MODE, 0x00000000); /* 0x1420 */
|
||||
GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_XTEN_MODE_REG_SETUP); /* 0x1418 */
|
||||
do {
|
||||
tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
|
||||
} while(tmp != 0x0);
|
||||
|
||||
/* reset DLL */
|
||||
GT_REG_WRITE(MV64460_SDRAM_MODE, 0x00000132); /* 0x141C */
|
||||
GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_MODE_REG_SETUP); /* 0x1418 */
|
||||
do {
|
||||
tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
|
||||
} while(tmp != 0x0);
|
||||
|
||||
/* precharge all */
|
||||
GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_PRECHARGE_ALL); /* 0x1418 */
|
||||
do {
|
||||
tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
|
||||
} while(tmp != 0x0);
|
||||
|
||||
/* wait for 2 auto refresh commands */
|
||||
udelay(20);
|
||||
|
||||
/* un-reset DLL */
|
||||
GT_REG_WRITE(MV64460_SDRAM_MODE, 0x00000032); /* 0x141C */
|
||||
GT_REG_WRITE(MV64460_SDRAM_OPERATION, SDRAM_MODE_REG_SETUP); /* 0x1418 */
|
||||
do {
|
||||
tmp = GTREGREAD(MV64460_SDRAM_OPERATION);
|
||||
} while(tmp != 0x0);
|
||||
|
||||
/* wait 200 cycles */
|
||||
udelay(2); /* FIXME make this dynamic for the system clock */
|
||||
|
||||
/* SDRAM init done */
|
||||
memory_map_bank(0, CFG_SDRAM_BASE, (256 << 20));
|
||||
#ifdef CFG_SDRAM1_BASE
|
||||
memory_map_bank(1, CFG_SDRAM1_BASE, (256 << 20));
|
||||
#endif
|
||||
|
||||
/* DUNIT_MMASK: enable SnoopHitEn bit to avoid errata CPU-#4
|
||||
*/
|
||||
tmp = GTREGREAD(MV64460_D_UNIT_MMASK); /* 0x14B0 */
|
||||
GT_REG_WRITE(MV64460_D_UNIT_MMASK, tmp | 0x2);
|
||||
|
||||
start = (0 << 20);
|
||||
#ifdef CONFIG_P3M750
|
||||
size = (512 << 20);
|
||||
#elif defined (CONFIG_P3M7448)
|
||||
size = (128 << 20);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MV64460_ECC
|
||||
memSpaceAttr = ((~(BIT0 << 0)) & 0xf) << 8;
|
||||
mvDmaSetMemorySpace (0, 0, memSpaceAttr, start, size);
|
||||
for (dest = start; dest < start + size; dest += _8M) {
|
||||
mvDmaTransfer (0, start, dest, _8M,
|
||||
BIT8 /*DMA_DTL_128BYTES */ |
|
||||
BIT3 /*DMA_HOLD_SOURCE_ADDR */ |
|
||||
BIT11 /*DMA_BLOCK_TRANSFER_MODE */ );
|
||||
while (mvDmaIsChannelActive (0));
|
||||
}
|
||||
#endif
|
||||
|
||||
return (size);
|
||||
}
|
||||
|
||||
void board_add_ram_info(int use_default)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
puts(" (CL=");
|
||||
switch ((GTREGREAD(MV64460_SDRAM_MODE) >> 4) & 0x7) {
|
||||
case 0x2:
|
||||
puts("2");
|
||||
break;
|
||||
case 0x3:
|
||||
puts("3");
|
||||
break;
|
||||
case 0x5:
|
||||
puts("1.5");
|
||||
break;
|
||||
case 0x6:
|
||||
puts("2.5");
|
||||
break;
|
||||
}
|
||||
|
||||
val = GTREGREAD(MV64460_SDRAM_CONFIG);
|
||||
|
||||
puts(", ECC ");
|
||||
if (val & 0x00001000)
|
||||
puts("enabled)");
|
||||
else
|
||||
puts("not enabled)");
|
||||
}
|
||||
|
||||
/*
|
||||
* mvDmaIsChannelActive - Check if IDMA channel is active
|
||||
*
|
||||
* channel = IDMA channel number from 0 to 7
|
||||
*/
|
||||
int mvDmaIsChannelActive (int channel)
|
||||
{
|
||||
ulong data;
|
||||
|
||||
data = GTREGREAD (MV64460_DMA_CHANNEL0_CONTROL + 4 * channel);
|
||||
if (data & BIT14) /* activity status */
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding
|
||||
* map.
|
||||
*
|
||||
* memSpace = IDMA memory window number from 0 to 7
|
||||
* trg_if = Target interface:
|
||||
* 0x0 DRAM
|
||||
* 0x1 Device Bus
|
||||
* 0x2 Integrated SDRAM (or CPU bus 60x only)
|
||||
* 0x3 PCI0
|
||||
* 0x4 PCI1
|
||||
* attr = IDMA attributes (see MV datasheet)
|
||||
* base_addr = Sets up memory window for transfers
|
||||
*
|
||||
*/
|
||||
int mvDmaSetMemorySpace (ulong memSpace,
|
||||
ulong trg_if,
|
||||
ulong attr, ulong base_addr, ulong size)
|
||||
{
|
||||
ulong temp;
|
||||
|
||||
/* The base address must be aligned to the size. */
|
||||
if (base_addr % size != 0)
|
||||
return 0;
|
||||
|
||||
if (size >= 0x10000) { /* 64K */
|
||||
size &= 0xffff0000;
|
||||
base_addr = (base_addr & 0xffff0000);
|
||||
/* Set the new attributes */
|
||||
GT_REG_WRITE (MV64460_DMA_BASE_ADDR_REG0 + memSpace * 8,
|
||||
(base_addr | trg_if | attr));
|
||||
GT_REG_WRITE ((MV64460_DMA_SIZE_REG0 + memSpace * 8),
|
||||
(size - 1) & 0xffff0000);
|
||||
temp = GTREGREAD (MV64460_DMA_BASE_ADDR_ENABLE_REG);
|
||||
GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG,
|
||||
(temp & ~(BIT0 << memSpace)));
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* mvDmaTransfer - Transfer data from src_addr to dst_addr on one of the 4
|
||||
* DMA channels.
|
||||
*
|
||||
* channel = IDMA channel number from 0 to 3
|
||||
* destAddr = Destination address
|
||||
* sourceAddr = Source address
|
||||
* size = Size in bytes
|
||||
* command = See MV datasheet
|
||||
*
|
||||
*/
|
||||
int mvDmaTransfer (int channel, ulong sourceAddr,
|
||||
ulong destAddr, ulong size, ulong command)
|
||||
{
|
||||
ulong engOffReg = 0; /* Engine Offset Register */
|
||||
|
||||
if (size > 0xffff)
|
||||
command = command | BIT31; /* DMA_16M_DESCRIPTOR_MODE */
|
||||
command = command | ((command >> 6) & 0x7);
|
||||
engOffReg = channel * 4;
|
||||
GT_REG_WRITE (MV64460_DMA_CHANNEL0_BYTE_COUNT + engOffReg, size);
|
||||
GT_REG_WRITE (MV64460_DMA_CHANNEL0_SOURCE_ADDR + engOffReg, sourceAddr);
|
||||
GT_REG_WRITE (MV64460_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg, destAddr);
|
||||
command = command |
|
||||
BIT12 | /* DMA_CHANNEL_ENABLE */
|
||||
BIT9; /* DMA_NON_CHAIN_MODE */
|
||||
/* Activate DMA channel By writting to mvDmaControlRegister */
|
||||
GT_REG_WRITE (MV64460_DMA_CHANNEL0_CONTROL + engOffReg, command);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/****************************************************************************************
|
||||
* SDRAM INIT *
|
||||
* This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb *
|
||||
* This procedure fits only the Atlantis *
|
||||
* *
|
||||
***************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* DFCDL initialize MV643xx Design Considerations *
|
||||
* *
|
||||
***************************************************************************************/
|
||||
int set_dfcdlInit (void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Values from MV64460 User Manual */
|
||||
unsigned int dfcdl_tbl[] = { 0x00000000, 0x00000001, 0x00000042, 0x00000083,
|
||||
0x000000c4, 0x00000105, 0x00000146, 0x00000187,
|
||||
0x000001c8, 0x00000209, 0x0000024a, 0x0000028b,
|
||||
0x000002cc, 0x0000030d, 0x0000034e, 0x0000038f,
|
||||
0x000003d0, 0x00000411, 0x00000452, 0x00000493,
|
||||
0x000004d4, 0x00000515, 0x00000556, 0x00000597,
|
||||
0x000005d8, 0x00000619, 0x0000065a, 0x0000069b,
|
||||
0x000006dc, 0x0000071d, 0x0000075e, 0x0000079f,
|
||||
0x000007e0, 0x00000821, 0x00000862, 0x000008a3,
|
||||
0x000008e4, 0x00000925, 0x00000966, 0x000009a7,
|
||||
0x000009e8, 0x00000a29, 0x00000a6a, 0x00000aab,
|
||||
0x00000aec, 0x00000b2d, 0x00000b6e, 0x00000baf,
|
||||
0x00000bf0, 0x00000c31, 0x00000c72, 0x00000cb3,
|
||||
0x00000cf4, 0x00000d35, 0x00000d76, 0x00000db7,
|
||||
0x00000df8, 0x00000e39, 0x00000e7a, 0x00000ebb,
|
||||
0x00000efc, 0x00000f3d, 0x00000f7e, 0x00000fbf };
|
||||
|
||||
for (i = 0; i < 64; i++)
|
||||
GT_REG_WRITE (SRAM_DATA0, dfcdl_tbl[i]);
|
||||
GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000); /* enable dynamic delay line updating */
|
||||
|
||||
return (0);
|
||||
}
|
107
board/prodrive/p3mx/serial.c
Normal file
107
board/prodrive/p3mx/serial.c
Normal file
|
@ -0,0 +1,107 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
|
||||
*
|
||||
* modified for marvell db64360 eval board by
|
||||
* Ingo Assmus <ingo.assmus@keymile.com>
|
||||
*
|
||||
* modified for cpci750 board by
|
||||
* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* serial.c - serial support for esd cpci750 board
|
||||
*/
|
||||
|
||||
/* supports the MPSC */
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include "../../Marvell/include/memory.h"
|
||||
#include "serial.h"
|
||||
|
||||
#include "mpsc.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int serial_init (void)
|
||||
{
|
||||
mpsc_init (gd->baudrate);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
void serial_putc (const char c)
|
||||
{
|
||||
if (c == '\n')
|
||||
mpsc_putchar ('\r');
|
||||
|
||||
mpsc_putchar (c);
|
||||
}
|
||||
|
||||
int serial_getc (void)
|
||||
{
|
||||
return mpsc_getchar ();
|
||||
}
|
||||
|
||||
int serial_tstc (void)
|
||||
{
|
||||
return mpsc_test_char ();
|
||||
}
|
||||
|
||||
void serial_setbrg (void)
|
||||
{
|
||||
galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
|
||||
}
|
||||
|
||||
|
||||
void serial_puts (const char *s)
|
||||
{
|
||||
while (*s) {
|
||||
serial_putc (*s++);
|
||||
}
|
||||
}
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
void kgdb_serial_init (void)
|
||||
{
|
||||
}
|
||||
|
||||
void putDebugChar (int c)
|
||||
{
|
||||
serial_putc (c);
|
||||
}
|
||||
|
||||
void putDebugStr (const char *str)
|
||||
{
|
||||
serial_puts (str);
|
||||
}
|
||||
|
||||
int getDebugChar (void)
|
||||
{
|
||||
return serial_getc ();
|
||||
}
|
||||
|
||||
void kgdb_interruptible (int yes)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#endif /* CFG_CMD_KGDB */
|
89
board/prodrive/p3mx/serial.h
Normal file
89
board/prodrive/p3mx/serial.h
Normal file
|
@ -0,0 +1,89 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
|
||||
*
|
||||
* modified for marvell db64360 eval board by
|
||||
* Ingo Assmus <ingo.assmus@keymile.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/* serial.h - mostly useful for DUART serial_init in serial.c */
|
||||
|
||||
#ifndef __SERIAL_H__
|
||||
#define __SERIAL_H__
|
||||
|
||||
#if 0
|
||||
|
||||
#define B230400 1
|
||||
#define B115200 2
|
||||
#define B57600 4
|
||||
#define B38400 82
|
||||
#define B19200 163
|
||||
#define B9600 24
|
||||
#define B4800 651
|
||||
#define B2400 1302
|
||||
#define B1200 2604
|
||||
#define B600 5208
|
||||
#define B300 10417
|
||||
#define B150 20833
|
||||
#define B110 28409
|
||||
#define BDEFAULT B115200
|
||||
|
||||
/* this stuff is important to initialize
|
||||
the DUART channels */
|
||||
|
||||
#define Scale 0x01L /* distance between port addresses */
|
||||
#define COM1 0x000003f8 /* Keyboard */
|
||||
#define COM2 0x000002f8 /* Host */
|
||||
|
||||
|
||||
/* Port Definitions relative to base COM port addresses */
|
||||
#define DataIn (0x00*Scale) /* data input port */
|
||||
#define DataOut (0x00*Scale) /* data output port */
|
||||
#define BaudLsb (0x00*Scale) /* baud rate divisor least significant byte */
|
||||
#define BaudMsb (0x01*Scale) /* baud rate divisor most significant byte */
|
||||
#define Ier (0x01*Scale) /* interrupt enable register */
|
||||
#define Iir (0x02*Scale) /* interrupt identification register */
|
||||
#define Lcr (0x03*Scale) /* line control register */
|
||||
#define Mcr (0x04*Scale) /* modem control register */
|
||||
#define Lsr (0x05*Scale) /* line status register */
|
||||
#define Msr (0x06*Scale) /* modem status register */
|
||||
|
||||
/* Bit Definitions for above ports */
|
||||
#define LcrDlab 0x80 /* b7: enable baud rate divisor registers */
|
||||
#define LcrDflt 0x03 /* b6-0: no parity, 1 stop, 8 data */
|
||||
|
||||
#define McrRts 0x02 /* b1: request to send (I am ready to xmit) */
|
||||
#define McrDtr 0x01 /* b0: data terminal ready (I am alive ready to rcv) */
|
||||
#define McrDflt (McrRts|McrDtr)
|
||||
|
||||
#define LsrTxD 0x6000 /* b5: transmit holding register empty (i.e. xmit OK!)*/
|
||||
/* b6: transmitter empty */
|
||||
#define LsrRxD 0x0100 /* b0: received data ready (i.e. got a byte!) */
|
||||
|
||||
#define MsrRi 0x0040 /* b6: ring indicator (other guy is ready to rcv) */
|
||||
#define MsrDsr 0x0020 /* b5: data set ready (other guy is alive ready to rcv */
|
||||
#define MsrCts 0x0010 /* b4: clear to send (other guy is ready to rcv) */
|
||||
|
||||
#define IerRda 0xf /* b0: Enable received data available interrupt */
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __SERIAL_H__ */
|
138
board/prodrive/p3mx/u-boot.lds
Normal file
138
board/prodrive/p3mx/u-boot.lds
Normal file
|
@ -0,0 +1,138 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* u-boot.lds - linker script for U-Boot on the Galileo Eval Board.
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
cpu/74xx_7xx/start.o (.text)
|
||||
|
||||
/* store the environment in a seperate sector in the boot flash */
|
||||
/* . = env_offset; */
|
||||
/* common/environment.o(.text) */
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
*(.eh_frame)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
|
@ -96,12 +96,10 @@ int do_bootvx ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
* If we don't know where the image is then we're done.
|
||||
*/
|
||||
|
||||
if ((tmp = getenv ("loadaddr")) != NULL) {
|
||||
addr = simple_strtoul (tmp, NULL, 16);
|
||||
} else {
|
||||
puts ("No load address provided\n");
|
||||
return 1;
|
||||
}
|
||||
if (argc < 2)
|
||||
addr = load_addr;
|
||||
else
|
||||
addr = simple_strtoul (argv[1], NULL, 16);
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_NET)
|
||||
/* Check to see if we need to tftp the image ourselves before starting */
|
||||
|
|
|
@ -101,6 +101,10 @@ get_cpu_type(void)
|
|||
type = CPU_7457;
|
||||
break;
|
||||
|
||||
case 0x8004:
|
||||
type = CPU_7448;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
@ -152,6 +156,10 @@ int checkcpu (void)
|
|||
str = "MPC7410";
|
||||
break;
|
||||
|
||||
case CPU_7448:
|
||||
str = "MPC7448";
|
||||
break;
|
||||
|
||||
case CPU_7450:
|
||||
str = "MPC7450";
|
||||
break;
|
||||
|
|
|
@ -43,6 +43,7 @@ cpu_init_f (void)
|
|||
case CPU_7450:
|
||||
case CPU_7455:
|
||||
case CPU_7457:
|
||||
case CPU_7448:
|
||||
/* enable the timebase bit in HID0 */
|
||||
set_hid0(get_hid0() | 0x4000000);
|
||||
break;
|
||||
|
|
|
@ -91,6 +91,7 @@ int get_clocks (void)
|
|||
|
||||
/* calculate the clock frequency based upon the CPU type */
|
||||
switch (get_cpu_type()) {
|
||||
case CPU_7448:
|
||||
case CPU_7455:
|
||||
case CPU_7457:
|
||||
/*
|
||||
|
|
|
@ -44,7 +44,8 @@
|
|||
|
||||
#if !defined(CONFIG_DB64360) && \
|
||||
!defined(CONFIG_DB64460) && \
|
||||
!defined(CONFIG_CPCI750)
|
||||
!defined(CONFIG_CPCI750) && \
|
||||
!defined(CONFIG_P3Mx)
|
||||
#include <galileo/gt64260R.h>
|
||||
#endif
|
||||
|
||||
|
@ -270,7 +271,7 @@ in_flash:
|
|||
* gt-regs BAT can be reused after board_init_f calls
|
||||
* board_early_init_f (EVB only).
|
||||
*/
|
||||
#if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC)
|
||||
#if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC) && !defined(CONFIG_P3Mx)
|
||||
/* enable address translation */
|
||||
bl enable_addr_trans
|
||||
sync
|
||||
|
@ -757,7 +758,8 @@ in_ram:
|
|||
defined(CONFIG_DB64360) || \
|
||||
defined(CONFIG_DB64460) || \
|
||||
defined(CONFIG_CPCI750) || \
|
||||
defined(CONFIG_PPMC7XX)
|
||||
defined(CONFIG_PPMC7XX) || \
|
||||
defined(CONFIG_P3Mx)
|
||||
mr r4, r9 /* Use RAM copy of the global data */
|
||||
#endif
|
||||
bl after_reloc
|
||||
|
|
|
@ -112,21 +112,20 @@ void
|
|||
ft_cpu_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
u32 *p;
|
||||
ulong clock;
|
||||
int len;
|
||||
|
||||
clock = bd->bi_busfreq;
|
||||
/* Core XLB bus frequency */
|
||||
p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
|
||||
if (p != NULL)
|
||||
*p = cpu_to_be32(clock);
|
||||
*p = cpu_to_be32(bd->bi_busfreq);
|
||||
|
||||
/* SOC peripherals use the IPB bus frequency */
|
||||
p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
|
||||
if (p != NULL)
|
||||
*p = cpu_to_be32(clock);
|
||||
*p = cpu_to_be32(bd->bi_ipbfreq);
|
||||
|
||||
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@3000/mac-address", &len);
|
||||
if (p != NULL)
|
||||
memcpy(p, bd->bi_enetaddr, 6);
|
||||
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -111,6 +111,7 @@ typedef enum __cpu_t {
|
|||
CPU_750CX, CPU_750FX, CPU_750GX,
|
||||
CPU_7400,
|
||||
CPU_7410,
|
||||
CPU_7448,
|
||||
CPU_7450, CPU_7455, CPU_7457,
|
||||
CPU_UNKNOWN} cpu_t;
|
||||
|
||||
|
|
450
include/configs/p3mx.h
Normal file
450
include/configs/p3mx.h
Normal file
|
@ -0,0 +1,450 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* Based on original work by
|
||||
* Roel Loeffen, (C) Copyright 2006 Prodrive B.V.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/************************************************************************
|
||||
* p3mx.h - configuration for Prodrive P3M750 & P3M7448 boards
|
||||
*
|
||||
* The defines:
|
||||
* CONFIG_P3M750 or
|
||||
* CONFIG_P3M7448
|
||||
* are written into include/config.h by the "make xxx_config" command
|
||||
***********************************************************************/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_P3Mx /* used for both board versions */
|
||||
|
||||
#if defined (CONFIG_P3M750)
|
||||
#define CONFIG_750FX /* 750GL/GX/FX */
|
||||
#define CFG_BOARD_NAME "P3M750"
|
||||
#define CFG_BUS_HZ 100000000
|
||||
#define CFG_BUS_CLK CFG_BUS_HZ
|
||||
#define CFG_TCLK 100000000
|
||||
#elif defined (CONFIG_P3M7448)
|
||||
#define CONFIG_74xx
|
||||
#define CFG_BOARD_NAME "P3M7448"
|
||||
#define CFG_BUS_HZ 133333333
|
||||
#define CFG_BUS_CLK CFG_BUS_HZ
|
||||
#define CFG_TCLK 133333333
|
||||
#endif
|
||||
#define CFG_GT_DUAL_CPU /* also for JTAG even with one cpu */
|
||||
|
||||
/* which initialization functions to call for this board */
|
||||
#define CFG_BOARD_ASM_INIT 1
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
|
||||
#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_f */
|
||||
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */
|
||||
#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#ifdef CONFIG_P3M750
|
||||
#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */
|
||||
#endif
|
||||
|
||||
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#if defined (CONFIG_P3M750)
|
||||
#define CFG_FLASH_BASE 0xff800000 /* start of flash banks */
|
||||
#define CFG_BOOT_SIZE _8M /* boot flash */
|
||||
#elif defined (CONFIG_P3M7448)
|
||||
#define CFG_FLASH_BASE 0xff000000 /* start of flash banks */
|
||||
#define CFG_BOOT_SIZE _16M /* boot flash */
|
||||
#endif
|
||||
#define CFG_BOOT_SPACE CFG_FLASH_BASE /* BOOT_CS0 flash 0 */
|
||||
#define CFG_MONITOR_BASE 0xfff00000
|
||||
#define CFG_RESET_ADDRESS 0xfff00100
|
||||
#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
|
||||
#define CFG_MISC_REGION_BASE 0xf0000000
|
||||
|
||||
#define CFG_DFL_GT_REGS 0xf1000000 /* boot time GT_REGS */
|
||||
#define CFG_GT_REGS 0xf1000000 /* GT Registers are mapped here */
|
||||
#define CFG_INT_SRAM_BASE 0x42000000 /* GT offers 256k internal SRAM */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer (placed in internal SRAM)
|
||||
*----------------------------------------------------------------------*/
|
||||
/*
|
||||
* When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
|
||||
* To an unused memory region. The stack will remain in cache until RAM
|
||||
* is initialized
|
||||
*/
|
||||
#undef CFG_INIT_RAM_LOCK
|
||||
#define CFG_INIT_RAM_ADDR 0x42000000
|
||||
#define CFG_INIT_RAM_END 0x1000
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_MPSC /* MV64460 Serial */
|
||||
#define CONFIG_MPSC_PORT 0
|
||||
#define CONFIG_BAUDRATE 115200 /* console baudrate */
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Ethernet
|
||||
*----------------------------------------------------------------------*/
|
||||
/* Change the default ethernet port, use this define (options: 0, 1, 2) */
|
||||
#define CFG_ETH_PORT ETH_0
|
||||
#define CONFIG_NET_MULTI
|
||||
#define MV_ETH_DEVS 2
|
||||
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
|
||||
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_FLASH_CFI /* The flash is CFI compatible */
|
||||
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
|
||||
#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
|
||||
#if defined (CONFIG_P3M750)
|
||||
#define CFG_ENV_SECT_SIZE 0x20000 /* one sector (1 device)*/
|
||||
#elif defined (CONFIG_P3M7448)
|
||||
#define CFG_ENV_SECT_SIZE 0x40000 /* two sectors (2 devices parallel */
|
||||
#endif
|
||||
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_MV64460_ECC
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_I2C_SPEED 100000 /* I2C speed default */
|
||||
|
||||
/* I2C RTC */
|
||||
#define CONFIG_RTC_M41T11 1
|
||||
#define CFG_I2C_RTC_ADDR 0x68
|
||||
#define CFG_M41T11_BASE_YEAR 1900 /* play along with linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*----------------------------------------------------------------------*/
|
||||
#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
|
||||
#define PCI_HOST_FORCE 1 /* configure as pci host */
|
||||
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
|
||||
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */
|
||||
|
||||
/* PCI MEMORY MAP section */
|
||||
#define CFG_PCI0_MEM_BASE 0x80000000
|
||||
#define CFG_PCI0_MEM_SIZE _128M
|
||||
#define CFG_PCI1_MEM_BASE 0x88000000
|
||||
#define CFG_PCI1_MEM_SIZE _128M
|
||||
|
||||
#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE)
|
||||
#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE)
|
||||
|
||||
/* PCI I/O MAP section */
|
||||
#define CFG_PCI0_IO_BASE 0xfa000000
|
||||
#define CFG_PCI0_IO_SIZE _16M
|
||||
#define CFG_PCI1_IO_BASE 0xfb000000
|
||||
#define CFG_PCI1_IO_SIZE _16M
|
||||
|
||||
#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE)
|
||||
#define CFG_PCI0_IO_SPACE_PCI 0x00000000
|
||||
#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE)
|
||||
#define CFG_PCI1_IO_SPACE_PCI 0x00000000
|
||||
|
||||
#define CFG_ISA_IO_BASE_ADDRESS (CFG_PCI0_IO_BASE)
|
||||
|
||||
#define CFG_PCI_IDSEL 0x30
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \
|
||||
"netdev=eth0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
|
||||
"flash_nfs=run nfsargs addip addtty;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_self=run ramargs addip addtty;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
|
||||
"bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_6xx\0" \
|
||||
"u-boot=p3mx/u-boot/u-boot.bin\0" \
|
||||
"load=tftp 100000 ${u-boot}\0" \
|
||||
"update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \
|
||||
"cp.b 100000 fff00000 40000;" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
"upd=run load;run update\0" \
|
||||
"serverip=11.0.0.152\0"
|
||||
|
||||
#if defined (CONFIG_P3M750)
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_EXTRA_ENV_SETTINGS_COMMON \
|
||||
"hostname=p3m750\0" \
|
||||
"bootfile=/tftpboot/p3mx/vxWorks.st\0" \
|
||||
"kernel_addr=fc000000\0" \
|
||||
"ramdisk_addr=fc180000\0" \
|
||||
"vxfile=p3m750/vxWorks\0" \
|
||||
"vxuser=ddg\0" \
|
||||
"vxpass=ddg\0" \
|
||||
"vxtarget=target\0" \
|
||||
"vxflags=0x8\0" \
|
||||
"vxargs=setenv bootargs mgi(0,0)host:${vxfile} h=${serverip} " \
|
||||
"e=${ipaddr} u=${vxuser} pw=${vxpass} tn=${vxtarget} " \
|
||||
"f=${vxflags}\0"
|
||||
#elif defined (CONFIG_P3M7448)
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_EXTRA_ENV_SETTINGS_COMMON \
|
||||
"hostname=p3m7448\0"
|
||||
#endif
|
||||
|
||||
#if defined (CONFIG_P3M750)
|
||||
#define CONFIG_BOOTCOMMAND "tftp;run vxargs;bootvx"
|
||||
#elif defined (CONFIG_P3M7448)
|
||||
#define CONFIG_BOOTCOMMAND " "
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
|
||||
CONFIG_BOOTP_BOOTFILESIZE)
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_DIAG | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_REGINFO | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_CACHE | \
|
||||
CFG_CMD_SDRAM)
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Miscellaneous configurable options
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_HUSH_PARSER
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x08000000 /* default load address */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
|
||||
#define CONFIG_LOOPW 1 /* enable loopw command */
|
||||
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
|
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Marvell MV64460 config settings
|
||||
*----------------------------------------------------------------------*/
|
||||
/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected device width */
|
||||
#if defined (CONFIG_P3M750)
|
||||
#define CFG_BOOT_PAR 0x8FDFF87F /* 16 bit flash, disable burst*/
|
||||
#elif defined (CONFIG_P3M7448)
|
||||
#define CFG_BOOT_PAR 0x8FEFFFFF /* 32 bit flash, burst enabled */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* MPP[0] Serial Port 0 TxD TxD OUT Connected to P14 (buffered)
|
||||
* MPP[1] Serial Port 0 RxD RxD IN Connected to P14 (buffered)
|
||||
* MPP[2] NC
|
||||
* MPP[3] Serial Port 1 TxD TxD OUT Connected to P14 (buffered)
|
||||
* MPP[4] PCI Monarch# GPIO IN Connected to P12
|
||||
* MPP[5] Serial Port 1 RxD RxD IN Connected to P14 (buffered)
|
||||
* MPP[6] PMC Carrier Interrupt 0 Int IN Connected to P14
|
||||
* MPP[7] PMC Carrier Interrupt 1 Int IN Connected to P14
|
||||
* MPP[8] Reserved Do not use
|
||||
* MPP[9] Reserved Do not use
|
||||
* MPP[10] Reserved Do not use
|
||||
* MPP[11] Reserved Do not use
|
||||
* MPP[12] Phy 0 Interrupt Int IN
|
||||
* MPP[13] Phy 1 Interrupt Int IN
|
||||
* MPP[14] NC
|
||||
* MPP[15] NC
|
||||
* MPP[16] PCI Interrupt C Int IN Connected to P11
|
||||
* MPP[17] PCI Interrupt D Int IN Connected to P11
|
||||
* MPP[18] Watchdog NMI# GPIO IN Connected to MPP[24]
|
||||
* MPP[19] Watchdog Expired# WDE OUT Connected to rst logic
|
||||
* MPP[20] Watchdog Status WD_STS IN Read back of rst by watchdog
|
||||
* MPP[21] NC
|
||||
* MPP[22] GP LED Green GPIO OUT
|
||||
* MPP[23] GP LED Red GPIO OUT
|
||||
* MPP[24] Watchdog NMI# Int OUT
|
||||
* MPP[25] NC
|
||||
* MPP[26] NC
|
||||
* MPP[27] PCI Interrupt A Int IN Connected to P11
|
||||
* MPP[28] NC
|
||||
* MPP[29] PCI Interrupt B Int IN Connected to P11
|
||||
* MPP[30] Module reset GPIO OUT Board reset
|
||||
* MPP[31] PCI EReady GPIO IN Connected to P12
|
||||
*/
|
||||
#define CFG_MPP_CONTROL_0 0x00303022
|
||||
#define CFG_MPP_CONTROL_1 0x00000000
|
||||
#define CFG_MPP_CONTROL_2 0x00004000
|
||||
#define CFG_MPP_CONTROL_3 0x00000004
|
||||
#define CFG_GPP_LEVEL_CONTROL 0x280730D0
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
* Initial BAT mappings
|
||||
*/
|
||||
|
||||
/* NOTES:
|
||||
* 1) GUARDED and WRITE_THRU not allowed in IBATS
|
||||
* 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
|
||||
*/
|
||||
/* SDRAM */
|
||||
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
|
||||
#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
|
||||
#define CFG_DBAT0U CFG_IBAT0U
|
||||
|
||||
/* init ram */
|
||||
#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
|
||||
#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT1L CFG_IBAT1L
|
||||
#define CFG_DBAT1U CFG_IBAT1U
|
||||
|
||||
/* PCI0, PCI1 in one BAT */
|
||||
#define CFG_IBAT2L BATL_NO_ACCESS
|
||||
#define CFG_IBAT2U CFG_DBAT2U
|
||||
#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
|
||||
/* GT regs, bootrom, all the devices, PCI I/O */
|
||||
#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
|
||||
#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
|
||||
#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_DBAT3U CFG_IBAT3U
|
||||
|
||||
#define CFG_IBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
|
||||
#define CFG_IBAT4U (CFG_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_DBAT4U CFG_IBAT4U
|
||||
|
||||
/* set rest out of range for Linux !!!!!!!!!!! */
|
||||
|
||||
/* IBAT5 and DBAT5 */
|
||||
#define CFG_IBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
|
||||
#define CFG_IBAT5U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_DBAT5U CFG_IBAT5U
|
||||
|
||||
/* IBAT6 and DBAT6 */
|
||||
#define CFG_IBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
|
||||
#define CFG_IBAT6U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_DBAT6U CFG_IBAT6U
|
||||
|
||||
/* IBAT7 and DBAT7 */
|
||||
#define CFG_IBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
|
||||
#define CFG_IBAT7U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_DBAT7U CFG_IBAT7U
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
|
||||
#define CFG_VXWORKS_MAC_PTR 0x42010000 /* use some memory in SRAM that's not used!!! */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* L2CR setup -- make sure this is right for your board!
|
||||
* look in include/mpc74xx.h for the defines used here
|
||||
*/
|
||||
#define CFG_L2
|
||||
|
||||
#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
|
||||
#define L2_INIT 0
|
||||
#else
|
||||
#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
|
||||
L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
|
||||
#endif
|
||||
|
||||
#define L2_ENABLE (L2_INIT | L2CR_L2E)
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#endif /* __CONFIG_H */
|
|
@ -1350,26 +1350,26 @@
|
|||
|
||||
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
||||
#define UIC2_DCR_BASE 0xe0
|
||||
#define uic2sr (UIC0_DCR_BASE+0x0) /* UIC2 status-Read Clear */
|
||||
#define uic2srs (UIC0_DCR_BASE+0x1) /* UIC2 status-Read Set */
|
||||
#define uic2er (UIC0_DCR_BASE+0x2) /* UIC2 enable */
|
||||
#define uic2cr (UIC0_DCR_BASE+0x3) /* UIC2 critical */
|
||||
#define uic2pr (UIC0_DCR_BASE+0x4) /* UIC2 polarity */
|
||||
#define uic2tr (UIC0_DCR_BASE+0x5) /* UIC2 triggering */
|
||||
#define uic2msr (UIC0_DCR_BASE+0x6) /* UIC2 masked status */
|
||||
#define uic2vr (UIC0_DCR_BASE+0x7) /* UIC2 vector */
|
||||
#define uic2vcr (UIC0_DCR_BASE+0x8) /* UIC2 vector configuration */
|
||||
#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */
|
||||
#define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */
|
||||
#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
|
||||
#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
|
||||
#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
|
||||
#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
|
||||
#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
|
||||
#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
|
||||
#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
|
||||
|
||||
#define UIC3_DCR_BASE 0xf0
|
||||
#define uic3sr (UIC1_DCR_BASE+0x0) /* UIC3 status-Read Clear */
|
||||
#define uic3srs (UIC0_DCR_BASE+0x1) /* UIC3 status-Read Set */
|
||||
#define uic3er (UIC1_DCR_BASE+0x2) /* UIC3 enable */
|
||||
#define uic3cr (UIC1_DCR_BASE+0x3) /* UIC3 critical */
|
||||
#define uic3pr (UIC1_DCR_BASE+0x4) /* UIC3 polarity */
|
||||
#define uic3tr (UIC1_DCR_BASE+0x5) /* UIC3 triggering */
|
||||
#define uic3msr (UIC1_DCR_BASE+0x6) /* UIC3 masked status */
|
||||
#define uic3vr (UIC1_DCR_BASE+0x7) /* UIC3 vector */
|
||||
#define uic3vcr (UIC1_DCR_BASE+0x8) /* UIC3 vector configuration */
|
||||
#define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */
|
||||
#define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */
|
||||
#define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */
|
||||
#define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */
|
||||
#define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */
|
||||
#define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */
|
||||
#define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */
|
||||
#define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */
|
||||
#define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */
|
||||
#endif /* CONFIG_440SPE */
|
||||
|
||||
#if defined(CONFIG_440GX)
|
||||
|
|
|
@ -142,13 +142,10 @@ int eth_initialize(bd_t *bis)
|
|||
miiphy_init();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DB64360
|
||||
#if defined(CONFIG_DB64360) || defined(CONFIG_CPCI750)
|
||||
mv6436x_eth_initialize(bis);
|
||||
#endif
|
||||
#ifdef CONFIG_CPCI750
|
||||
mv6436x_eth_initialize(bis);
|
||||
#endif
|
||||
#ifdef CONFIG_DB64460
|
||||
#if defined(CONFIG_DB64460) || defined(CONFIG_P3Mx)
|
||||
mv6446x_eth_initialize(bis);
|
||||
#endif
|
||||
#if defined(CONFIG_4xx) && !defined(CONFIG_IOP480) && !defined(CONFIG_AP1000)
|
||||
|
|
Loading…
Reference in a new issue