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imx6: ensure AHB clock is 132MHz in low freq boot mode

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For low freq boot mode(ARM boot up with 396MHz), ROM
will not set AHB clock to 132MHz, and the reset value of
AHB divider is incorrect which will lead to wrong AHB
rate, need to correct it. To enable low freq boot mode,
need to set BOOT_CFG2[2] to high, tested on i.MX6Q/DL
SabreSD board and i.MX6SL EVK board.

Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Anson Huang <b20788@freescale.com>
This commit is contained in:
Anson Huang 2014-01-23 14:00:18 +08:00 committed by Stefano Babic
parent 6fc049bef6
commit 5c92edc21c
1 changed files with 20 additions and 0 deletions
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20
arch/arm/cpu/armv7/mx6/soc.c
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@ -177,10 +177,30 @@ static void imx_set_wdog_powerdown(bool enable)
writew(enable, &wdog2->wmcr); writew(enable, &wdog2->wmcr);
} }
static void set_ahb_rate(u32 val)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
u32 reg, div;
div = get_periph_clk() / val - 1;
reg = readl(&mxc_ccm->cbcdr);
writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
(div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
}
int arch_cpu_init(void) int arch_cpu_init(void)
{ {
init_aips(); init_aips();
/*
* When low freq boot is enabled, ROM will not set AHB
* freq, so we need to ensure AHB freq is 132MHz in such
* scenario.
*/
if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
set_ahb_rate(132000000);
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
#ifdef CONFIG_APBH_DMA #ifdef CONFIG_APBH_DMA