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net: fix cache misaligned issue in Broadcom SF2 driver
Fixed cache misaligned issue in the net driver. The issue shows-up when a call to flush_dcache_range is made with unaligned memory. The memory must be aligned to ARCH_DMA_MINALIGN. Signed-off-by: Suji Velupillai <suji.velupillai@broadcom.com> Tested-by: Suji Velupillai <suji.velupillai@broadcom.com> Reviewed-by: Arun Parameswaran <arun.parameswaran@broadcom.com> Reviewed-by: JD Zheng <jiandong.zheng@broadcom.com> Reviewed-by: Shamez Kurji <shamez.kurji@broadcom.com> Signed-off-by: Steve Rae <steve.rae@raedomain.com> Cover Letter: This series resolves issues specific to the Broadcom SF2 driver: - fix cache misaligned issue - convert to Kconfig END Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Suji Velupillai
Joe Hershberger
parent
ec7aa8fd67
commit
5c624b9e9c
2 changed files with 60 additions and 57 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright 2014 Broadcom Corporation.
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* Copyright 2014-2017 Broadcom.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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@ -28,6 +28,10 @@
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} \
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}
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#define RX_BUF_SIZE_ALIGNED ALIGN(RX_BUF_SIZE, ARCH_DMA_MINALIGN)
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#define TX_BUF_SIZE_ALIGNED ALIGN(TX_BUF_SIZE, ARCH_DMA_MINALIGN)
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#define DESCP_SIZE_ALIGNED ALIGN(sizeof(dma64dd_t), ARCH_DMA_MINALIGN)
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static int gmac_disable_dma(struct eth_dma *dma, int dir);
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static int gmac_enable_dma(struct eth_dma *dma, int dir);
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@ -114,7 +118,7 @@ static void dma_tx_dump(struct eth_dma *dma)
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printf("TX Buffers:\n");
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/* Initialize TX DMA descriptor table */
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for (i = 0; i < TX_BUF_NUM; i++) {
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bufp = (uint8_t *)(dma->tx_buf + i * TX_BUF_SIZE);
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bufp = (uint8_t *)(dma->tx_buf + i * TX_BUF_SIZE_ALIGNED);
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printf("buf%d:0x%x; ", i, (uint32_t)bufp);
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}
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printf("\n");
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@ -145,7 +149,7 @@ static void dma_rx_dump(struct eth_dma *dma)
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printf("RX Buffers:\n");
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for (i = 0; i < RX_BUF_NUM; i++) {
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bufp = dma->rx_buf + i * RX_BUF_SIZE;
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bufp = dma->rx_buf + i * RX_BUF_SIZE_ALIGNED;
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printf("buf%d:0x%x; ", i, (uint32_t)bufp);
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}
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printf("\n");
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@ -163,15 +167,15 @@ static int dma_tx_init(struct eth_dma *dma)
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/* clear descriptor memory */
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memset((void *)(dma->tx_desc_aligned), 0,
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TX_BUF_NUM * sizeof(dma64dd_t));
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memset(dma->tx_buf, 0, TX_BUF_NUM * TX_BUF_SIZE);
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TX_BUF_NUM * DESCP_SIZE_ALIGNED);
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memset(dma->tx_buf, 0, TX_BUF_NUM * TX_BUF_SIZE_ALIGNED);
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/* Initialize TX DMA descriptor table */
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for (i = 0; i < TX_BUF_NUM; i++) {
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descp = (dma64dd_t *)(dma->tx_desc_aligned) + i;
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bufp = dma->tx_buf + i * TX_BUF_SIZE;
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bufp = dma->tx_buf + i * TX_BUF_SIZE_ALIGNED;
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/* clear buffer memory */
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memset((void *)bufp, 0, TX_BUF_SIZE);
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memset((void *)bufp, 0, TX_BUF_SIZE_ALIGNED);
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ctrl = 0;
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/* if last descr set endOfTable */
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@ -187,10 +191,11 @@ static int dma_tx_init(struct eth_dma *dma)
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descp = dma->tx_desc_aligned;
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bufp = dma->tx_buf;
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flush_dcache_range((unsigned long)descp,
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(unsigned long)(descp +
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sizeof(dma64dd_t) * TX_BUF_NUM));
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flush_dcache_range((unsigned long)(bufp),
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(unsigned long)(bufp + TX_BUF_SIZE * TX_BUF_NUM));
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(unsigned long)descp +
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DESCP_SIZE_ALIGNED * TX_BUF_NUM);
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flush_dcache_range((unsigned long)bufp,
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(unsigned long)bufp +
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TX_BUF_SIZE_ALIGNED * TX_BUF_NUM);
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/* initialize the DMA channel */
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writel((uint32_t)(dma->tx_desc_aligned), GMAC0_DMA_TX_ADDR_LOW_ADDR);
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@ -215,20 +220,20 @@ static int dma_rx_init(struct eth_dma *dma)
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/* clear descriptor memory */
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memset((void *)(dma->rx_desc_aligned), 0,
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RX_BUF_NUM * sizeof(dma64dd_t));
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RX_BUF_NUM * DESCP_SIZE_ALIGNED);
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/* clear buffer memory */
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memset(dma->rx_buf, 0, RX_BUF_NUM * RX_BUF_SIZE);
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memset(dma->rx_buf, 0, RX_BUF_NUM * RX_BUF_SIZE_ALIGNED);
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/* Initialize RX DMA descriptor table */
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for (i = 0; i < RX_BUF_NUM; i++) {
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descp = (dma64dd_t *)(dma->rx_desc_aligned) + i;
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bufp = dma->rx_buf + i * RX_BUF_SIZE;
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bufp = dma->rx_buf + i * RX_BUF_SIZE_ALIGNED;
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ctrl = 0;
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/* if last descr set endOfTable */
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if (i == (RX_BUF_NUM - 1))
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ctrl = D64_CTRL1_EOT;
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descp->ctrl1 = ctrl;
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descp->ctrl2 = RX_BUF_SIZE;
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descp->ctrl2 = RX_BUF_SIZE_ALIGNED;
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descp->addrlow = (uint32_t)bufp;
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descp->addrhigh = 0;
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@ -240,10 +245,11 @@ static int dma_rx_init(struct eth_dma *dma)
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bufp = dma->rx_buf;
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/* flush descriptor and buffer */
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flush_dcache_range((unsigned long)descp,
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(unsigned long)(descp +
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sizeof(dma64dd_t) * RX_BUF_NUM));
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(unsigned long)descp +
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DESCP_SIZE_ALIGNED * RX_BUF_NUM);
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flush_dcache_range((unsigned long)(bufp),
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(unsigned long)(bufp + RX_BUF_SIZE * RX_BUF_NUM));
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(unsigned long)bufp +
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RX_BUF_SIZE_ALIGNED * RX_BUF_NUM);
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/* initailize the DMA channel */
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writel((uint32_t)descp, GMAC0_DMA_RX_ADDR_LOW_ADDR);
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@ -292,14 +298,12 @@ static int dma_deinit(struct eth_dma *dma)
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free(dma->tx_buf);
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dma->tx_buf = NULL;
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free(dma->tx_desc);
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dma->tx_desc = NULL;
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free(dma->tx_desc_aligned);
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dma->tx_desc_aligned = NULL;
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free(dma->rx_buf);
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dma->rx_buf = NULL;
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free(dma->rx_desc);
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dma->rx_desc = NULL;
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free(dma->rx_desc_aligned);
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dma->rx_desc_aligned = NULL;
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return 0;
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@ -307,7 +311,7 @@ static int dma_deinit(struct eth_dma *dma)
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int gmac_tx_packet(struct eth_dma *dma, void *packet, int length)
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{
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uint8_t *bufp = dma->tx_buf + dma->cur_tx_index * TX_BUF_SIZE;
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uint8_t *bufp = dma->tx_buf + dma->cur_tx_index * TX_BUF_SIZE_ALIGNED;
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/* kick off the dma */
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size_t len = length;
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@ -348,10 +352,11 @@ int gmac_tx_packet(struct eth_dma *dma, void *packet, int length)
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descp->ctrl2 = ctrl;
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/* flush descriptor and buffer */
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flush_dcache_range((unsigned long)descp,
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(unsigned long)(descp + sizeof(dma64dd_t)));
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flush_dcache_range((unsigned long)dma->tx_desc_aligned,
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(unsigned long)dma->tx_desc_aligned +
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DESCP_SIZE_ALIGNED * TX_BUF_NUM);
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flush_dcache_range((unsigned long)bufp,
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(unsigned long)(bufp + TX_BUF_SIZE));
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(unsigned long)bufp + TX_BUF_SIZE_ALIGNED);
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/* now update the dma last descriptor */
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writel(last_desc, GMAC0_DMA_TX_PTR_ADDR);
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@ -426,14 +431,15 @@ int gmac_check_rx_done(struct eth_dma *dma, uint8_t *buf)
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;
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/* get the packet pointer that corresponds to the rx descriptor */
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bufp = dma->rx_buf + index * RX_BUF_SIZE;
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bufp = dma->rx_buf + index * RX_BUF_SIZE_ALIGNED;
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descp = (dma64dd_t *)(dma->rx_desc_aligned) + index;
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/* flush descriptor and buffer */
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flush_dcache_range((unsigned long)descp,
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(unsigned long)(descp + sizeof(dma64dd_t)));
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flush_dcache_range((unsigned long)dma->rx_desc_aligned,
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(unsigned long)dma->rx_desc_aligned +
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DESCP_SIZE_ALIGNED * RX_BUF_NUM);
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flush_dcache_range((unsigned long)bufp,
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(unsigned long)(bufp + RX_BUF_SIZE));
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(unsigned long)bufp + RX_BUF_SIZE_ALIGNED);
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buflen = (descp->ctrl2 & D64_CTRL2_BC_MASK);
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@ -457,12 +463,13 @@ int gmac_check_rx_done(struct eth_dma *dma, uint8_t *buf)
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memcpy(buf, datap, rcvlen);
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/* update descriptor that is being added back on ring */
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descp->ctrl2 = RX_BUF_SIZE;
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descp->ctrl2 = RX_BUF_SIZE_ALIGNED;
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descp->addrlow = (uint32_t)bufp;
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descp->addrhigh = 0;
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/* flush descriptor */
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flush_dcache_range((unsigned long)descp,
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(unsigned long)(descp + sizeof(dma64dd_t)));
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flush_dcache_range((unsigned long)dma->rx_desc_aligned,
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(unsigned long)dma->rx_desc_aligned +
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DESCP_SIZE_ALIGNED * RX_BUF_NUM);
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/* set the lastdscr for the rx ring */
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writel(((uint32_t)descp) & D64_XP_LD_MASK, GMAC0_DMA_RX_PTR_ADDR);
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@ -573,7 +580,7 @@ static int gmac_enable_dma(struct eth_dma *dma, int dir)
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* set the lastdscr for the rx ring
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*/
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writel(((uint32_t)(dma->rx_desc_aligned) +
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(RX_BUF_NUM - 1) * RX_BUF_SIZE) &
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(RX_BUF_NUM - 1) * RX_BUF_SIZE_ALIGNED) &
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D64_XP_LD_MASK, GMAC0_DMA_RX_PTR_ADDR);
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}
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@ -893,54 +900,52 @@ int gmac_add(struct eth_device *dev)
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void *tmp;
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/*
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* Desc has to be 16-byte aligned ?
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* If it is 8-byte aligned by malloc, fail Tx
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* Desc has to be 16-byte aligned. But for dcache flush it must be
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* aligned to ARCH_DMA_MINALIGN.
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*/
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tmp = malloc(sizeof(dma64dd_t) * TX_BUF_NUM + 8);
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tmp = memalign(ARCH_DMA_MINALIGN, DESCP_SIZE_ALIGNED * TX_BUF_NUM);
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if (tmp == NULL) {
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printf("%s: Failed to allocate TX desc Buffer\n", __func__);
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return -1;
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}
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dma->tx_desc = (void *)tmp;
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dma->tx_desc_aligned = (void *)(((uint32_t)tmp) & (~0xf));
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dma->tx_desc_aligned = (void *)tmp;
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debug("TX Descriptor Buffer: %p; length: 0x%x\n",
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dma->tx_desc_aligned, sizeof(dma64dd_t) * TX_BUF_NUM);
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dma->tx_desc_aligned, DESCP_SIZE_ALIGNED * TX_BUF_NUM);
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tmp = malloc(TX_BUF_SIZE * TX_BUF_NUM);
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tmp = memalign(ARCH_DMA_MINALIGN, TX_BUF_SIZE_ALIGNED * TX_BUF_NUM);
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if (tmp == NULL) {
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printf("%s: Failed to allocate TX Data Buffer\n", __func__);
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free(dma->tx_desc);
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free(dma->tx_desc_aligned);
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return -1;
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}
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dma->tx_buf = (uint8_t *)tmp;
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debug("TX Data Buffer: %p; length: 0x%x\n",
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dma->tx_buf, TX_BUF_SIZE * TX_BUF_NUM);
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dma->tx_buf, TX_BUF_SIZE_ALIGNED * TX_BUF_NUM);
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/* Desc has to be 16-byte aligned ? */
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tmp = malloc(sizeof(dma64dd_t) * RX_BUF_NUM + 8);
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/* Desc has to be 16-byte aligned */
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tmp = memalign(ARCH_DMA_MINALIGN, DESCP_SIZE_ALIGNED * RX_BUF_NUM);
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if (tmp == NULL) {
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printf("%s: Failed to allocate RX Descriptor\n", __func__);
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free(dma->tx_desc);
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free(dma->tx_desc_aligned);
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free(dma->tx_buf);
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return -1;
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}
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dma->rx_desc = tmp;
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dma->rx_desc_aligned = (void *)(((uint32_t)tmp) & (~0xf));
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dma->rx_desc_aligned = (void *)tmp;
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debug("RX Descriptor Buffer: %p, length: 0x%x\n",
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dma->rx_desc_aligned, sizeof(dma64dd_t) * RX_BUF_NUM);
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dma->rx_desc_aligned, DESCP_SIZE_ALIGNED * RX_BUF_NUM);
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tmp = malloc(RX_BUF_SIZE * RX_BUF_NUM);
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tmp = memalign(ARCH_DMA_MINALIGN, RX_BUF_SIZE_ALIGNED * RX_BUF_NUM);
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if (tmp == NULL) {
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printf("%s: Failed to allocate RX Data Buffer\n", __func__);
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free(dma->tx_desc);
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free(dma->tx_desc_aligned);
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free(dma->tx_buf);
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free(dma->rx_desc);
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free(dma->rx_desc_aligned);
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return -1;
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}
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dma->rx_buf = tmp;
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dma->rx_buf = (uint8_t *)tmp;
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debug("RX Data Buffer: %p; length: 0x%x\n",
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dma->rx_buf, RX_BUF_SIZE * RX_BUF_NUM);
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dma->rx_buf, RX_BUF_SIZE_ALIGNED * RX_BUF_NUM);
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g_dmactrlflags = 0;
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@ -1,5 +1,5 @@
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/*
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* Copyright 2014 Broadcom Corporation.
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* Copyright 2014-2017 Broadcom.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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@ -30,8 +30,6 @@ enum {
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struct eth_dma {
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void *tx_desc_aligned;
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void *rx_desc_aligned;
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void *tx_desc;
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void *rx_desc;
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uint8_t *tx_buf;
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uint8_t *rx_buf;
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