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socfpga: arria10: Wait for fifo empty after writing bitstream

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For some reason, on the Mercury+ AA1 module, calling
fpgamgr_wait_early_user_mode immediately after writing the peripheral
bitstream leaves the fpga in a broken state (ddr calibration hangs).
Adding a delay before the first sync word is written seems to fix this.
Inspecting the fpgamgr registers before and after the delay,
imgcfg_FifoEmpty is the only bit that changes. Waiting for this bit
(instead of a hardcoded delay) also fixes the issue.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Paweł Anikiel 2022-06-17 12:47:25 +02:00 committed by Tien Fong Chee
parent 8b1eee3730
commit 5c53d9c0d9
1 changed files with 8 additions and 0 deletions
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8
drivers/fpga/socfpga_arria10.c
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@ -80,6 +80,13 @@ static int wait_for_user_mode(void)
1, FPGA_TIMEOUT_MSEC, false);
}
static int wait_for_fifo_empty(void)
{
return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK,
1, FPGA_TIMEOUT_MSEC, false);
}
int is_fpgamgr_early_user_mode(void)
{
return (readl(&fpga_manager_base->imgcfg_stat) &
@ -874,6 +881,7 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
WATCHDOG_RESET();
}
wait_for_fifo_empty();
if (fpga_loadfs.rbfinfo.section == periph_section) {
if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {