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https://github.com/AsahiLinux/u-boot
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Xilinx changes for v2021.01-rc3
Microblaze: - Enable GC - Get rid of xparameters.h and switch to DT for CFI - Fix config file tpm: - Fix TPM code zynqmp: - Enable TPM by default - Remove unused macros fru: - Several fixes especially use limit for recording -----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCX7eTAAAKCRDKSWXLKUoM IQ/nAJ41sZwLDKsq2r6OhCYEv6Y9za0bUQCfTOhMt4+LPv4h4Og8pAlAg4Pwb7w= =URLE -----END PGP SIGNATURE----- Merge tag 'xilinx-for-v2021.01-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.01-rc3 Microblaze: - Enable GC - Get rid of xparameters.h and switch to DT for CFI - Fix config file tpm: - Fix TPM code zynqmp: - Enable TPM by default - Remove unused macros fru: - Several fixes especially use limit for recording
This commit is contained in:
Tom Rini
commit
5b8991c667
11 changed files with 35 additions and 110 deletions
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@ -134,7 +134,8 @@ struct apu_regs {
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struct csu_regs {
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u32 reserved0[4];
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u32 multi_boot;
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u32 reserved1[12];
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u32 reserved1[11];
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u32 idcode;
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u32 version;
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};
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@ -149,7 +150,4 @@ struct pmu_regs {
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#define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR)
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#define ZYNQMP_CSU_IDCODE_ADDR 0xFFCA0040
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#define ZYNQMP_CSU_VER_ADDR 0xFFCA0044
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#endif /* _ASM_ARCH_HARDWARE_H */
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@ -9,6 +9,9 @@
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CONFIG_STANDALONE_LOAD_ADDR ?= 0x80F00000
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PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__
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PLATFORM_CPPFLAGS += -fdata-sections -ffunction-sections
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LDFLAGS_FINAL += --gc-sections
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ifeq ($(CONFIG_SPL_BUILD),)
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PLATFORM_CPPFLAGS += -fPIC
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@ -14,7 +14,7 @@ SECTIONS
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{
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__text_start = .;
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arch/microblaze/cpu/start.o (.text)
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*(.text)
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*(.text*)
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__text_end = .;
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}
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@ -28,7 +28,7 @@ SECTIONS
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.data ALIGN(0x4):
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{
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__data_start = .;
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*(.data)
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*(.data*)
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__data_end = .;
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}
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@ -51,7 +51,7 @@ SECTIONS
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__bss_start = .;
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*(.sbss)
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*(.scommon)
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*(.bss)
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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__bss_end = .;
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@ -50,12 +50,16 @@ struct fru_board_data {
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/* Xilinx custom fields */
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u8 rev_type_len;
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u8 rev[FRU_BOARD_MAX_LEN];
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u8 pcie_type_len;
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u8 pcie[FRU_BOARD_MAX_LEN];
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u8 uuid_type_len;
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u8 uuid[FRU_BOARD_MAX_LEN];
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};
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struct fru_table {
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bool captured;
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struct fru_common_hdr hdr;
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struct fru_board_data brd;
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bool captured;
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};
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#define FRU_TYPELEN_CODE_MASK 0xC0
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@ -163,12 +163,15 @@ static int fru_parse_board(unsigned long addr)
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{
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u8 i, type;
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int len;
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u8 *data, *term;
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u8 *data, *term, *limit;
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memcpy(&fru_data.brd.ver, (void *)addr, 6);
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addr += 6;
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data = (u8 *)&fru_data.brd.manufacturer_type_len;
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/* Record max structure limit not to write data over allocated space */
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limit = data + sizeof(struct fru_board_data);
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for (i = 0; ; i++, data += FRU_BOARD_MAX_LEN) {
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len = fru_check_type_len(*(u8 *)addr, fru_data.brd.lang_code,
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&type);
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@ -178,6 +181,9 @@ static int fru_parse_board(unsigned long addr)
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if (len == -EINVAL)
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break;
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/* Stop when amount of chars is more then fields to record */
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if (data + len > limit)
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break;
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/* This record type/len field */
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*data++ = *(u8 *)addr;
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@ -217,7 +223,7 @@ int fru_capture(unsigned long addr)
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hdr = (struct fru_common_hdr *)addr;
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memcpy((void *)&fru_data.hdr, (void *)hdr,
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memcpy((void *)&fru_data, (void *)hdr,
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sizeof(struct fru_common_hdr));
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fru_data.captured = true;
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@ -1,18 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2007 Michal Simek
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*
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* Michal SIMEK <monstr@monstr.eu>
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*
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* CAUTION: This file is a faked configuration !!!
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* There is no real target for the microblaze-generic
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* configuration. You have to replace this file with
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* the generated file from your Xilinx design flow.
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*/
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/* Microblaze is microblaze_0 */
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#define XILINX_FSL_NUMBER 3
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/* Flash Memory is FLASH_2Mx32 */
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#define XILINX_FLASH_START 0x2c000000
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#define XILINX_FLASH_SIZE 0x00800000
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@ -48,8 +48,10 @@ CONFIG_DM_I2C=y
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CONFIG_LED=y
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CONFIG_LED_GPIO=y
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CONFIG_MTD=y
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CONFIG_DM_MTD=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_CFI_FLASH=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_FLASH_CFI_MTD=y
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CONFIG_SYS_FLASH_PROTECTION=y
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@ -57,6 +57,7 @@ CONFIG_CMD_TFTPPUT=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_TIME=y
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CONFIG_CMD_TIMER=y
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CONFIG_CMD_TPM=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_MTDPARTS=y
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CONFIG_CMD_MTDPARTS_SPREAD=y
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@ -137,6 +138,7 @@ CONFIG_ZYNQ_SERIAL=y
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CONFIG_SPI=y
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CONFIG_ZYNQ_SPI=y
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CONFIG_ZYNQMP_GQSPI=y
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CONFIG_TPM2_TIS_SPI=y
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CONFIG_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_DWC3=y
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@ -156,5 +158,6 @@ CONFIG_USB_ETHER_ASIX=y
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CONFIG_WDT=y
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CONFIG_WDT_CDNS=y
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CONFIG_PANIC_HANG=y
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CONFIG_TPM=y
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CONFIG_SPL_GZIP=y
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CONFIG_OF_LIBFDT_OVERLAY=y
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@ -30,8 +30,6 @@
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#include "tpm_tis.h"
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#include "tpm_internal.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define TPM_ACCESS(l) (0x0000 | ((l) << 12))
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#define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12))
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#define TPM_STS(l) (0x0018 | ((l) << 12))
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@ -520,7 +518,6 @@ static int tpm_tis_spi_cleanup(struct udevice *dev)
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static int tpm_tis_spi_open(struct udevice *dev)
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{
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struct tpm_chip *chip = dev_get_priv(dev);
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struct tpm_chip_priv *priv = dev_get_uclass_priv(dev);
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if (chip->is_open)
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return -EBUSY;
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@ -8,24 +8,14 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include "../board/xilinx/microblaze-generic/xparameters.h"
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/* Microblaze is microblaze_0 */
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#define XILINX_FSL_NUMBER 3
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/* MicroBlaze CPU */
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#define MICROBLAZE_V5 1
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#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024)
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/* linear and spi flash memory */
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#ifdef XILINX_FLASH_START
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#define FLASH
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#undef SPIFLASH
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#undef RAMENV /* hold environment in flash */
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#else
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#undef FLASH
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#undef SPIFLASH
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#define RAMENV /* hold environment in RAM */
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#endif
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/* uart */
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/* The following table includes the supported baudrates */
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# define CONFIG_SYS_BAUDRATE_TABLE \
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@ -40,67 +30,17 @@
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#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \
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CONFIG_SYS_MALLOC_F_LEN)
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/*
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* CFI flash memory layout - Example
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* CONFIG_SYS_FLASH_BASE = 0x2200_0000;
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* CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB
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*
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* SECT_SIZE = 0x20000; 128kB is one sector
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* CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store
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*
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* 0x2200_0000 CONFIG_SYS_FLASH_BASE
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* FREE 256kB
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* 0x2204_0000 CONFIG_ENV_ADDR
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* ENV_AREA 128kB
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* 0x2206_0000
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* FREE
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* 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
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*
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*/
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#ifdef FLASH
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# define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
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# define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
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#ifdef CONFIG_CFI_FLASH
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/* ?empty sector */
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# define CONFIG_SYS_FLASH_EMPTY_INFO 1
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/* max number of memory banks */
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# define CONFIG_SYS_MAX_FLASH_BANKS 1
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/* max number of sectors on one chip */
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# define CONFIG_SYS_MAX_FLASH_SECT 512
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/* hardware flash protection */
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/* use buffered writes (20x faster) */
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# ifdef RAMENV
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# else /* FLASH && !RAMENV */
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/* 128K(one sector) for env */
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# endif /* FLASH && !RAMBOOT */
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#else /* !FLASH */
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# define CONFIG_SYS_MAX_FLASH_SECT 2048
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#endif
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#ifdef SPIFLASH
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# ifdef RAMENV
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# else /* SPIFLASH && !RAMENV */
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/* 128K(two sectors) for env */
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/* Warning: adjust the offset in respect of other flash content and size */
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# endif /* SPIFLASH && !RAMBOOT */
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#else /* !SPIFLASH */
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/* ENV in RAM */
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#endif /* !SPIFLASH */
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#endif /* !FLASH */
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#define XILINX_USE_ICACHE 1
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#define XILINX_USE_DCACHE 1
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#if defined(XILINX_USE_ICACHE)
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#define CONFIG_ICACHE
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#else
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# undef CONFIG_ICACHE
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#endif
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#if defined(XILINX_USE_DCACHE)
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#define CONFIG_DCACHE
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#else
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# undef CONFIG_DCACHE
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#endif
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#ifndef XILINX_DCACHE_BYTE_SIZE
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#define XILINX_DCACHE_BYTE_SIZE 32768
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@ -111,12 +51,6 @@
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#if defined(CONFIG_MTD_PARTITIONS)
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/* MTD partitions */
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/* default mtd partition table */
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#endif
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/* size of console buffer */
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#define CONFIG_SYS_CBSIZE 512
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/* max number of command args */
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@ -194,15 +128,12 @@
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/* SPL part */
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#ifdef CONFIG_SYS_FLASH_BASE
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# define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
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#endif
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#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
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/* for booting directly linux */
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#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
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#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_TEXT_BASE + \
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0x40000)
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#define CONFIG_SYS_FDT_SIZE (16 << 10)
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#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \
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0x1000000)
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@ -2170,7 +2170,6 @@ CONFIG_SYS_FCC_PSMR
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CONFIG_SYS_FDT_BASE
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CONFIG_SYS_FDT_LOAD_ADDR
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CONFIG_SYS_FDT_PAD
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CONFIG_SYS_FDT_SIZE
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CONFIG_SYS_FEC0_IOBASE
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CONFIG_SYS_FEC1_IOBASE
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CONFIG_SYS_FECI2C
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