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omap4: add omap4460 revision detection
Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
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3 changed files with 5 additions and 0 deletions
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@ -140,6 +140,9 @@ static void init_omap4_revision(void)
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case MIDR_CORTEX_A9_R1P3:
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case MIDR_CORTEX_A9_R1P3:
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*omap4_revision = OMAP4430_ES2_3;
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*omap4_revision = OMAP4430_ES2_3;
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break;
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break;
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case MIDR_CORTEX_A9_R2P10:
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*omap4_revision = OMAP4460_ES1_0;
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break;
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default:
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default:
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*omap4_revision = OMAP4430_SILICON_ID_INVALID;
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*omap4_revision = OMAP4430_SILICON_ID_INVALID;
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break;
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break;
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@ -143,6 +143,7 @@ struct s32ktimer {
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#define OMAP4430_ES2_1 0x44300210
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#define OMAP4430_ES2_1 0x44300210
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#define OMAP4430_ES2_2 0x44300220
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#define OMAP4430_ES2_2 0x44300220
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#define OMAP4430_ES2_3 0x44300230
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#define OMAP4430_ES2_3 0x44300230
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#define OMAP4460_ES1_0 0x44600100
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/* ROM code defines */
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/* ROM code defines */
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/* Boot device */
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/* Boot device */
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@ -29,6 +29,7 @@
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#define MIDR_CORTEX_A9_R0P1 0x410FC091
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#define MIDR_CORTEX_A9_R0P1 0x410FC091
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#define MIDR_CORTEX_A9_R1P2 0x411FC092
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#define MIDR_CORTEX_A9_R1P2 0x411FC092
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#define MIDR_CORTEX_A9_R1P3 0x411FC093
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#define MIDR_CORTEX_A9_R1P3 0x411FC093
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#define MIDR_CORTEX_A9_R2P10 0x412FC09A
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/* CCSIDR */
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/* CCSIDR */
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#define CCSIDR_LINE_SIZE_OFFSET 0
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#define CCSIDR_LINE_SIZE_OFFSET 0
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