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Merge branch 'master' of git://git.denx.de/u-boot-ti

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This commit is contained in:
Tom Rini 2014-10-27 09:05:43 -04:00
commit 5aa7bece10
79 changed files with 3465 additions and 931 deletions
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3
arch/arm/cpu/armv7/keystone/Kconfig
View file

@ -9,6 +9,9 @@ config TARGET_K2HK_EVM
config TARGET_K2E_EVM
bool "TI Keystone 2 Edison EVM"
config TARGET_K2L_EVM
bool "TI Keystone 2 Lamar EVM"
endchoice
config SYS_CPU

5
arch/arm/cpu/armv7/keystone/Makefile
View file

@ -10,10 +10,9 @@ obj-y += psc.o
obj-y += clock.o
obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
obj-$(CONFIG_SOC_K2E) += clock-k2e.o
obj-$(CONFIG_SOC_K2L) += clock-k2l.o
obj-y += cmd_clock.o
obj-y += cmd_mon.o
obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o
obj-y += msmc.o
obj-$(CONFIG_SPL_BUILD) += spl.o
obj-y += ddr3.o
obj-y += ddr3.o cmd_ddr3.o
obj-y += keystone.o

138
arch/arm/cpu/armv7/keystone/clock-k2l.c Normal file
View file

@ -0,0 +1,138 @@
/*
* Keystone2: get clk rate for K2L
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/clock_defs.h>
const struct keystone_pll_regs keystone_pll_regs[] = {
[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
[TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
[DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
};
int dev_speeds[] = {
SPD800,
SPD1000,
SPD1200,
SPD800,
SPD800,
SPD800,
SPD800,
SPD800,
SPD1200,
SPD1000,
SPD800,
SPD800,
SPD800,
};
int arm_speeds[] = {
SPD800,
SPD1000,
SPD1200,
SPD1350,
SPD1400,
SPD800,
SPD1400,
SPD1350,
SPD1200,
SPD1000,
SPD800,
SPD800,
SPD800,
};
/**
* pll_freq_get - get pll frequency
* Fout = Fref * NF(mult) / NR(prediv) / OD
* @pll: pll identifier
*/
static unsigned long pll_freq_get(int pll)
{
unsigned long mult = 1, prediv = 1, output_div = 2;
unsigned long ret;
u32 tmp, reg;
if (pll == CORE_PLL) {
ret = external_clk[sys_clk];
if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) {
/* PLL mode */
tmp = __raw_readl(KS2_MAINPLLCTL0);
prediv = (tmp & PLL_DIV_MASK) + 1;
mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) |
(pllctl_reg_read(pll, mult) &
PLLM_MULT_LO_MASK)) + 1;
output_div = ((pllctl_reg_read(pll, secctl) >>
PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1;
ret = ret / prediv / output_div * mult;
}
} else {
switch (pll) {
case PASS_PLL:
ret = external_clk[pa_clk];
reg = KS2_PASSPLLCTL0;
break;
case TETRIS_PLL:
ret = external_clk[tetris_clk];
reg = KS2_ARMPLLCTL0;
break;
case DDR3_PLL:
ret = external_clk[ddr3_clk];
reg = KS2_DDR3APLLCTL0;
break;
default:
return 0;
}
tmp = __raw_readl(reg);
if (!(tmp & PLLCTL_BYPASS)) {
/* Bypass disabled */
prediv = (tmp & PLL_DIV_MASK) + 1;
mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1;
output_div = ((tmp >> PLL_CLKOD_SHIFT) &
PLL_CLKOD_MASK) + 1;
ret = ((ret / prediv) * mult) / output_div;
}
}
return ret;
}
unsigned long clk_get_rate(unsigned int clk)
{
switch (clk) {
case core_pll_clk: return pll_freq_get(CORE_PLL);
case pass_pll_clk: return pll_freq_get(PASS_PLL);
case tetris_pll_clk: return pll_freq_get(TETRIS_PLL);
case ddr3_pll_clk: return pll_freq_get(DDR3_PLL);
case sys_clk0_1_clk:
case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
default:
break;
}
return 0;
}

17
arch/arm/cpu/armv7/keystone/clock.c
View file

@ -185,10 +185,6 @@ void init_pll(const struct pll_init_data *data)
tmp &= ~(PLL_BWADJ_HI_MASK);
tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK);
/* set PLL Select (bit 13) for PASS PLL */
if (data->pll == PASS_PLL)
tmp |= PLLCTL_PAPLL;
__raw_writel(tmp, keystone_pll_regs[data->pll].reg1);
/* Reset bit: bit 14 for both DDR3 & PASS PLL */
@ -261,3 +257,16 @@ inline int get_max_arm_speed(void)
return get_max_speed((read_efuse_bootrom() >> 16) & 0xffff, arm_speeds);
}
#endif
void pass_pll_pa_clk_enable(void)
{
u32 reg;
reg = readl(keystone_pll_regs[PASS_PLL].reg1);
reg |= PLLCTL_PAPLL;
writel(reg, keystone_pll_regs[PASS_PLL].reg1);
/* wait till clock is enabled */
sdelay(15000);
}

24
arch/arm/cpu/armv7/keystone/cmd_clock.c
View file

@ -58,20 +58,11 @@ pll_cmd_usage:
return cmd_usage(cmdtp);
}
#ifdef CONFIG_SOC_K2HK
U_BOOT_CMD(
pllset, 5, 0, do_pll_cmd,
"set pll multiplier and pre divider",
"<pa|arm|ddr3a|ddr3b> <mult> <div> <OD>\n"
PLLSET_CMD_LIST " <mult> <div> <OD>\n"
);
#endif
#ifdef CONFIG_SOC_K2E
U_BOOT_CMD(
pllset, 5, 0, do_pll_cmd,
"set pll multiplier and pre divider",
"<pa|ddr3> <mult> <div> <OD>\n"
);
#endif
int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
@ -95,12 +86,8 @@ U_BOOT_CMD(
getclk, 2, 0, do_getclk_cmd,
"get clock rate",
"<clk index>\n"
#ifdef CONFIG_SOC_K2HK
"See the 'enum clk_e' in the clock-k2hk.h for clk indexes\n"
#endif
#ifdef CONFIG_SOC_K2E
"See the 'enum clk_e' in the clock-k2e.h for clk indexes\n"
#endif
"The indexes for clocks:\n"
CLOCK_INDEXES_LIST
);
int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@ -141,5 +128,8 @@ U_BOOT_CMD(
psc, 3, 0, do_psc_cmd,
"<enable/disable psc module os disable domain>",
"<mod/domain index> <en|di|domain>\n"
"See the hardware.h for Power and Sleep Controller (PSC) Domains\n"
"Intended to control Power and Sleep Controller (PSC) domains and\n"
"modules. The module or domain index exectly corresponds to ones\n"
"listed in official TRM. For instance, to enable MSMC RAM clock\n"
"domain use command: psc 14 en.\n"
);

248
arch/arm/cpu/armv7/keystone/cmd_ddr3.c Normal file
View file

@ -0,0 +1,248 @@
/*
* Keystone2: DDR3 test commands
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/hardware.h>
#include <asm/arch/ddr3.h>
#include <common.h>
#include <command.h>
DECLARE_GLOBAL_DATA_PTR;
#define DDR_MIN_ADDR CONFIG_SYS_SDRAM_BASE
#define DDR_REMAP_ADDR 0x80000000
#define ECC_START_ADDR1 ((DDR_MIN_ADDR - DDR_REMAP_ADDR) >> 17)
#define ECC_END_ADDR1 (((gd->start_addr_sp - DDR_REMAP_ADDR - \
CONFIG_STACKSIZE) >> 17) - 2)
#define DDR_TEST_BURST_SIZE 1024
static int ddr_memory_test(u32 start_address, u32 end_address, int quick)
{
u32 index_start, value, index;
index_start = start_address;
while (1) {
/* Write a pattern */
for (index = index_start;
index < index_start + DDR_TEST_BURST_SIZE;
index += 4)
__raw_writel(index, index);
/* Read and check the pattern */
for (index = index_start;
index < index_start + DDR_TEST_BURST_SIZE;
index += 4) {
value = __raw_readl(index);
if (value != index) {
printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
index, value, __raw_readl(index));
return -1;
}
}
index_start += DDR_TEST_BURST_SIZE;
if (index_start >= end_address)
break;
if (quick)
continue;
/* Write a pattern for complementary values */
for (index = index_start;
index < index_start + DDR_TEST_BURST_SIZE;
index += 4)
__raw_writel((u32)~index, index);
/* Read and check the pattern */
for (index = index_start;
index < index_start + DDR_TEST_BURST_SIZE;
index += 4) {
value = __raw_readl(index);
if (value != ~index) {
printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
index, value, __raw_readl(index));
return -1;
}
}
index_start += DDR_TEST_BURST_SIZE;
if (index_start >= end_address)
break;
/* Write a pattern */
for (index = index_start;
index < index_start + DDR_TEST_BURST_SIZE;
index += 2)
__raw_writew((u16)index, index);
/* Read and check the pattern */
for (index = index_start;
index < index_start + DDR_TEST_BURST_SIZE;
index += 2) {
value = __raw_readw(index);
if (value != (u16)index) {
printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
index, value, __raw_readw(index));
return -1;
}
}
index_start += DDR_TEST_BURST_SIZE;
if (index_start >= end_address)
break;
/* Write a pattern */
for (index = index_start;
index < index_start + DDR_TEST_BURST_SIZE;
index += 1)
__raw_writeb((u8)index, index);
/* Read and check the pattern */
for (index = index_start;
index < index_start + DDR_TEST_BURST_SIZE;
index += 1) {
value = __raw_readb(index);
if (value != (u8)index) {
printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n",
index, value, __raw_readb(index));
return -1;
}
}
index_start += DDR_TEST_BURST_SIZE;
if (index_start >= end_address)
break;
}
puts("ddr memory test PASSED!\n");
return 0;
}
static int ddr_memory_compare(u32 address1, u32 address2, u32 size)
{
u32 index, value, index2, value2;
for (index = address1, index2 = address2;
index < address1 + size;
index += 4, index2 += 4) {
value = __raw_readl(index);
value2 = __raw_readl(index2);
if (value != value2) {
printf("ddr_memory_test: Compare failed at address = 0x%x value = 0x%x, address2 = 0x%x value2 = 0x%x\n",
index, value, index2, value2);
return -1;
}
}
puts("ddr memory compare PASSED!\n");
return 0;
}
static int ddr_memory_ecc_err(u32 base, u32 address, u32 ecc_err)
{
u32 value1, value2, value3;
puts("Disabling DDR ECC ...\n");
ddr3_disable_ecc(base);
value1 = __raw_readl(address);
value2 = value1 ^ ecc_err;
__raw_writel(value2, address);
value3 = __raw_readl(address);
printf("ECC err test, addr 0x%x, read data 0x%x, wrote data 0x%x, err pattern: 0x%x, read after write data 0x%x\n",
address, value1, value2, ecc_err, value3);
__raw_writel(ECC_START_ADDR1 | (ECC_END_ADDR1 << 16),
base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
puts("Enabling DDR ECC ...\n");
ddr3_enable_ecc(base, 1);
value1 = __raw_readl(address);
printf("ECC err test, addr 0x%x, read data 0x%x\n", address, value1);
ddr3_check_ecc_int(base);
return 0;
}
static int do_ddr_test(cmd_tbl_t *cmdtp,
int flag, int argc, char * const argv[])
{
u32 start_addr, end_addr, size, ecc_err;
if ((argc == 4) && (strncmp(argv[1], "ecc_err", 8) == 0)) {
if (!ddr3_ecc_support_rmw(KS2_DDR3A_EMIF_CTRL_BASE)) {
puts("ECC RMW isn't supported for this SOC\n");
return 1;
}
start_addr = simple_strtoul(argv[2], NULL, 16);
ecc_err = simple_strtoul(argv[3], NULL, 16);
if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
(start_addr > (CONFIG_SYS_SDRAM_BASE +
CONFIG_MAX_RAM_BANK_SIZE - 1))) {
puts("Invalid address!\n");
return cmd_usage(cmdtp);
}
ddr_memory_ecc_err(KS2_DDR3A_EMIF_CTRL_BASE,
start_addr, ecc_err);
return 0;
}
if (!(((argc == 4) && (strncmp(argv[1], "test", 5) == 0)) ||
((argc == 5) && (strncmp(argv[1], "compare", 8) == 0))))
return cmd_usage(cmdtp);
start_addr = simple_strtoul(argv[2], NULL, 16);
end_addr = simple_strtoul(argv[3], NULL, 16);
if ((start_addr < CONFIG_SYS_SDRAM_BASE) ||
(start_addr > (CONFIG_SYS_SDRAM_BASE +
CONFIG_MAX_RAM_BANK_SIZE - 1)) ||
(end_addr < CONFIG_SYS_SDRAM_BASE) ||
(end_addr > (CONFIG_SYS_SDRAM_BASE +
CONFIG_MAX_RAM_BANK_SIZE - 1)) || (start_addr >= end_addr)) {
puts("Invalid start or end address!\n");
return cmd_usage(cmdtp);
}
puts("Please wait ...\n");
if (argc == 5) {
size = simple_strtoul(argv[4], NULL, 16);
ddr_memory_compare(start_addr, end_addr, size);
} else {
ddr_memory_test(start_addr, end_addr, 0);
}
return 0;
}
U_BOOT_CMD(ddr, 5, 1, do_ddr_test,
"DDR3 test",
"test <start_addr in hex> <end_addr in hex> - test DDR from start\n"
" address to end address\n"
"ddr compare <start_addr in hex> <end_addr in hex> <size in hex> -\n"
" compare DDR data of (size) bytes from start address to end\n"
" address\n"
"ddr ecc_err <addr in hex> <bit_err in hex> - generate bit errors\n"
" in DDR data at <addr>, the command will read a 32-bit data\n"
" from <addr>, and write (data ^ bit_err) back to <addr>\n"
);

244
arch/arm/cpu/armv7/keystone/ddr3.c
View file

@ -9,9 +9,19 @@
#include <asm/io.h>
#include <common.h>
#include <asm/arch/msmc.h>
#include <asm/arch/ddr3.h>
#include <asm/arch/psc_defs.h>
#include <asm/ti-common/ti-edma3.h>
#define DDR3_EDMA_BLK_SIZE_SHIFT 10
#define DDR3_EDMA_BLK_SIZE (1 << DDR3_EDMA_BLK_SIZE_SHIFT)
#define DDR3_EDMA_BCNT 0x8000
#define DDR3_EDMA_CCNT 1
#define DDR3_EDMA_XF_SIZE (DDR3_EDMA_BLK_SIZE * DDR3_EDMA_BCNT)
#define DDR3_EDMA_SLOT_NUM 1
void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
{
unsigned int tmp;
@ -70,6 +80,240 @@ void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg)
__raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET);
}
int ddr3_ecc_support_rmw(u32 base)
{
u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET);
/* Check the DDR3 controller ID reg if the controllers
supports ECC RMW or not */
if (value == 0x40461C02)
return 1;
return 0;
}
static void ddr3_ecc_config(u32 base, u32 value)
{
u32 data;
__raw_writel(value, base + KS2_DDR3_ECC_CTRL_OFFSET);
udelay(100000); /* delay required to synchronize across clock domains */
if (value & KS2_DDR3_ECC_EN) {
/* Clear the 1-bit error count */
data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
__raw_writel(data, base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
/* enable the ECC interrupt */
__raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
KS2_DDR3_WR_ECC_ERR_SYS,
base + KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET);
/* Clear the ECC error interrupt status */
__raw_writel(KS2_DDR3_1B_ECC_ERR_SYS | KS2_DDR3_2B_ECC_ERR_SYS |
KS2_DDR3_WR_ECC_ERR_SYS,
base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
}
}
static void ddr3_reset_data(u32 base, u32 ddr3_size)
{
u32 mpax[2];
u32 seg_num;
u32 seg, blks, dst, edma_blks;
struct edma3_slot_config slot;
struct edma3_channel_config edma_channel;
u32 edma_src[DDR3_EDMA_BLK_SIZE/4] __aligned(16) = {0, };
/* Setup an edma to copy the 1k block to the entire DDR */
puts("\nClear entire DDR3 memory to enable ECC\n");
/* save the SES MPAX regs */
msmc_get_ses_mpax(8, 0, mpax);
/* setup edma slot 1 configuration */
slot.opt = EDMA3_SLOPT_TRANS_COMP_INT_ENB |
EDMA3_SLOPT_COMP_CODE(0) |
EDMA3_SLOPT_STATIC | EDMA3_SLOPT_AB_SYNC;
slot.bcnt = DDR3_EDMA_BCNT;
slot.acnt = DDR3_EDMA_BLK_SIZE;
slot.ccnt = DDR3_EDMA_CCNT;
slot.src_bidx = 0;
slot.dst_bidx = DDR3_EDMA_BLK_SIZE;
slot.src_cidx = 0;
slot.dst_cidx = 0;
slot.link = EDMA3_PARSET_NULL_LINK;
slot.bcntrld = 0;
edma3_slot_configure(KS2_EDMA0_BASE, DDR3_EDMA_SLOT_NUM, &slot);
/* configure quik edma channel */
edma_channel.slot = DDR3_EDMA_SLOT_NUM;
edma_channel.chnum = 0;
edma_channel.complete_code = 0;
/* event trigger after dst update */
edma_channel.trigger_slot_word = EDMA3_TWORD(dst);
qedma3_start(KS2_EDMA0_BASE, &edma_channel);
/* DDR3 size in segments (4KB seg size) */
seg_num = ddr3_size << (30 - KS2_MSMC_SEG_SIZE_SHIFT);
for (seg = 0; seg < seg_num; seg += KS2_MSMC_MAP_SEG_NUM) {
/* map 2GB 36-bit DDR address to 32-bit DDR address in EMIF
access slave interface so that edma driver can access */
msmc_map_ses_segment(8, 0, base >> KS2_MSMC_SEG_SIZE_SHIFT,
KS2_MSMC_DST_SEG_BASE + seg, MPAX_SEG_2G);
if ((seg_num - seg) > KS2_MSMC_MAP_SEG_NUM)
edma_blks = KS2_MSMC_MAP_SEG_NUM <<
(KS2_MSMC_SEG_SIZE_SHIFT
- DDR3_EDMA_BLK_SIZE_SHIFT);
else
edma_blks = (seg_num - seg) << (KS2_MSMC_SEG_SIZE_SHIFT
- DDR3_EDMA_BLK_SIZE_SHIFT);
/* Use edma driver to scrub 2GB DDR memory */
for (dst = base, blks = 0; blks < edma_blks;
blks += DDR3_EDMA_BCNT, dst += DDR3_EDMA_XF_SIZE) {
edma3_set_src_addr(KS2_EDMA0_BASE,
edma_channel.slot, (u32)edma_src);
edma3_set_dest_addr(KS2_EDMA0_BASE,
edma_channel.slot, (u32)dst);
while (edma3_check_for_transfer(KS2_EDMA0_BASE,
&edma_channel))
udelay(10);
}
}
qedma3_stop(KS2_EDMA0_BASE, &edma_channel);
/* restore the SES MPAX regs */
msmc_set_ses_mpax(8, 0, mpax);
}
static void ddr3_ecc_init_range(u32 base)
{
u32 ecc_val = KS2_DDR3_ECC_EN;
u32 rmw = ddr3_ecc_support_rmw(base);
if (rmw)
ecc_val |= KS2_DDR3_ECC_RMW_EN;
__raw_writel(0, base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET);
ddr3_ecc_config(base, ecc_val);
}
void ddr3_enable_ecc(u32 base, int test)
{
u32 ecc_val = KS2_DDR3_ECC_ENABLE;
u32 rmw = ddr3_ecc_support_rmw(base);
if (test)
ecc_val |= KS2_DDR3_ECC_ADDR_RNG_1_EN;
if (!rmw) {
if (!test)
/* by default, disable ecc when rmw = 0 and no
ecc test */
ecc_val = 0;
} else {
ecc_val |= KS2_DDR3_ECC_RMW_EN;
}
ddr3_ecc_config(base, ecc_val);
}
void ddr3_disable_ecc(u32 base)
{
ddr3_ecc_config(base, 0);
}
#if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
static void cic_init(u32 base)
{
/* Disable CIC global interrupts */
__raw_writel(0, base + KS2_CIC_GLOBAL_ENABLE);
/* Set to normal mode, no nesting, no priority hold */
__raw_writel(0, base + KS2_CIC_CTRL);
__raw_writel(0, base + KS2_CIC_HOST_CTRL);
/* Enable CIC global interrupts */
__raw_writel(1, base + KS2_CIC_GLOBAL_ENABLE);
}
static void cic_map_cic_to_gic(u32 base, u32 chan_num, u32 irq_num)
{
/* Map the system interrupt to a CIC channel */
__raw_writeb(chan_num, base + KS2_CIC_CHAN_MAP(0) + irq_num);
/* Enable CIC system interrupt */
__raw_writel(irq_num, base + KS2_CIC_SYS_ENABLE_IDX_SET);
/* Enable CIC Host interrupt */
__raw_writel(chan_num, base + KS2_CIC_HOST_ENABLE_IDX_SET);
}
static void ddr3_map_ecc_cic2_irq(u32 base)
{
cic_init(base);
cic_map_cic_to_gic(base, KS2_CIC2_DDR3_ECC_CHAN_NUM,
KS2_CIC2_DDR3_ECC_IRQ_NUM);
}
#endif
void ddr3_init_ecc(u32 base)
{
u32 ddr3_size;
if (!ddr3_ecc_support_rmw(base)) {
ddr3_disable_ecc(base);
return;
}
ddr3_ecc_init_range(base);
ddr3_size = ddr3_get_size();
ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size);
/* mapping DDR3 ECC system interrupt from CIC2 to GIC */
#if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L)
ddr3_map_ecc_cic2_irq(KS2_CIC2_BASE);
#endif
ddr3_enable_ecc(base, 0);
}
void ddr3_check_ecc_int(u32 base)
{
char *env;
int ecc_test = 0;
u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET);
env = getenv("ecc_test");
if (env)
ecc_test = simple_strtol(env, NULL, 0);
if (value & KS2_DDR3_WR_ECC_ERR_SYS)
puts("DDR3 ECC write error interrupted\n");
if (value & KS2_DDR3_2B_ECC_ERR_SYS) {
puts("DDR3 ECC 2-bit error interrupted\n");
if (!ecc_test) {
puts("Reseting the device ...\n");
reset_cpu(0);
}
}
value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET);
if (value) {
printf("1-bit ECC err count: 0x%x\n", value);
value = __raw_readl(base +
KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET);
printf("1-bit ECC err address log: 0x%x\n", value);
}
}
void ddr3_reset_ddrphy(void)
{
u32 tmp;

63
arch/arm/cpu/armv7/keystone/init.c
View file

@ -13,6 +13,7 @@
#include <asm/arch/msmc.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
#include <asm/arch/psc_defs.h>
void chip_configuration_unlock(void)
{
@ -20,17 +21,67 @@ void chip_configuration_unlock(void)
__raw_writel(KS2_KICK1_MAGIC, KS2_KICK1);
}
#ifdef CONFIG_SOC_K2L
void osr_init(void)
{
u32 i;
u32 j;
u32 val;
u32 base = KS2_OSR_CFG_BASE;
u32 ecc_ctrl[KS2_OSR_NUM_RAM_BANKS];
/* Enable the OSR clock domain */
psc_enable_module(KS2_LPSC_OSR);
/* Disable OSR ECC check for all the ram banks */
for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++) {
val = i | KS2_OSR_ECC_VEC_TRIG_RD |
(KS2_OSR_ECC_CTRL << KS2_OSR_ECC_VEC_RD_ADDR_SH);
writel(val , base + KS2_OSR_ECC_VEC);
/**
* wait till read is done.
* Print should be added after earlyprintk support is added.
*/
for (j = 0; j < 10000; j++) {
val = readl(base + KS2_OSR_ECC_VEC);
if (val & KS2_OSR_ECC_VEC_RD_DONE)
break;
}
ecc_ctrl[i] = readl(base + KS2_OSR_ECC_CTRL) ^
KS2_OSR_ECC_CTRL_CHK;
writel(ecc_ctrl[i], KS2_MSMC_DATA_BASE + i * 4);
writel(ecc_ctrl[i], base + KS2_OSR_ECC_CTRL);
}
/* Reset OSR memory to all zeros */
for (i = 0; i < KS2_OSR_SIZE; i += 4)
writel(0, KS2_OSR_DATA_BASE + i);
/* Enable OSR ECC check for all the ram banks */
for (i = 0; i < KS2_OSR_NUM_RAM_BANKS; i++)
writel(ecc_ctrl[i] |
KS2_OSR_ECC_CTRL_CHK, base + KS2_OSR_ECC_CTRL);
}
#endif
int arch_cpu_init(void)
{
chip_configuration_unlock();
icache_enable();
msmc_share_all_segments(8); /* TETRIS */
msmc_share_all_segments(9); /* NETCP */
msmc_share_all_segments(10); /* QM PDSP */
msmc_share_all_segments(11); /* PCIE 0 */
#ifdef CONFIG_SOC_K2E
msmc_share_all_segments(13); /* PCIE 1 */
msmc_share_all_segments(KS2_MSMC_SEGMENT_TETRIS);
msmc_share_all_segments(KS2_MSMC_SEGMENT_NETCP);
msmc_share_all_segments(KS2_MSMC_SEGMENT_QM_PDSP);
msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE0);
#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
msmc_share_all_segments(KS2_MSMC_SEGMENT_PCIE1);
#endif
#ifdef CONFIG_SOC_K2L
osr_init();
#endif
/*

26
arch/arm/cpu/armv7/keystone/msmc.c
View file

@ -66,3 +66,29 @@ void msmc_share_all_segments(int priv_id)
msmc->ses[priv_id][j].mpaxh &= 0xffffff7ful;
}
}
void msmc_map_ses_segment(int priv_id, int ses_pair,
u32 src_pfn, u32 dst_pfn, enum mpax_seg_size size)
{
struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
msmc->ses[priv_id][ses_pair].mpaxh = src_pfn << 12 |
(size & 0x1f) | 0x80;
msmc->ses[priv_id][ses_pair].mpaxl = dst_pfn << 8 | 0x3f;
}
void msmc_get_ses_mpax(int priv_id, int ses_pair, u32 *mpax)
{
struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
*mpax++ = msmc->ses[priv_id][ses_pair].mpaxl;
*mpax = msmc->ses[priv_id][ses_pair].mpaxh;
}
void msmc_set_ses_mpax(int priv_id, int ses_pair, u32 *mpax)
{
struct msms_regs *msmc = (struct msms_regs *)KS2_MSMC_CTRL_BASE;
msmc->ses[priv_id][ses_pair].mpaxl = *mpax++;
msmc->ses[priv_id][ses_pair].mpaxh = *mpax;
}

53
arch/arm/cpu/armv7/keystone/spl.c
View file

@ -1,53 +0,0 @@
/*
* common spl init code
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <config.h>
#include <ns16550.h>
#include <malloc.h>
#include <spl.h>
#include <spi_flash.h>
#include <asm/u-boot.h>
#include <asm/utils.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_K2HK_EVM
static struct pll_init_data spl_pll_config[] = {
CORE_PLL_799,
TETRIS_PLL_500,
};
#endif
#ifdef CONFIG_K2E_EVM
static struct pll_init_data spl_pll_config[] = {
CORE_PLL_800,
};
#endif
void spl_init_keystone_plls(void)
{
init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
}
void spl_board_init(void)
{
spl_init_keystone_plls();
preloader_console_init();
}
u32 spl_boot_device(void)
{
#if defined(CONFIG_SPL_SPI_LOAD)
return BOOT_DEVICE_SPI;
#else
puts("Unknown boot device\n");
hang();
#endif
}

2
arch/arm/cpu/armv7/omap3/Kconfig
View file

@ -16,7 +16,7 @@ config TARGET_OMAP3_BEAGLE
bool "TI OMAP3 BeagleBoard"
config TARGET_CM_T35
bool "CompuLab CM-T35"
bool "CompuLab CM-T3530 and CM-T3730 boards"
config TARGET_DEVKIT8000
bool "TimLL OMAP3 Devkit8000"

43
arch/arm/include/asm/arch-keystone/clock-k2e.h
View file

@ -25,27 +25,28 @@ enum ext_clk_e {
extern unsigned int external_clk[ext_clk_count];
enum clk_e {
core_pll_clk,
pass_pll_clk,
ddr3_pll_clk,
sys_clk0_clk,
sys_clk0_1_clk,
sys_clk0_2_clk,
sys_clk0_3_clk,
sys_clk0_4_clk,
sys_clk0_6_clk,
sys_clk0_8_clk,
sys_clk0_12_clk,
sys_clk0_24_clk,
sys_clk1_clk,
sys_clk1_3_clk,
sys_clk1_4_clk,
sys_clk1_6_clk,
sys_clk1_12_clk,
sys_clk2_clk,
sys_clk3_clk
};
#define CLK_LIST(CLK)\
CLK(0, core_pll_clk)\
CLK(1, pass_pll_clk)\
CLK(2, ddr3_pll_clk)\
CLK(3, sys_clk0_clk)\
CLK(4, sys_clk0_1_clk)\
CLK(5, sys_clk0_2_clk)\
CLK(6, sys_clk0_3_clk)\
CLK(7, sys_clk0_4_clk)\
CLK(8, sys_clk0_6_clk)\
CLK(9, sys_clk0_8_clk)\
CLK(10, sys_clk0_12_clk)\
CLK(11, sys_clk0_24_clk)\
CLK(12, sys_clk1_clk)\
CLK(13, sys_clk1_3_clk)\
CLK(14, sys_clk1_4_clk)\
CLK(15, sys_clk1_6_clk)\
CLK(16, sys_clk1_12_clk)\
CLK(17, sys_clk2_clk)\
CLK(18, sys_clk3_clk)
#define PLLSET_CMD_LIST "<pa|ddr3>"
#define KS2_CLK1_6 sys_clk0_6_clk

47
arch/arm/include/asm/arch-keystone/clock-k2hk.h
View file

@ -28,29 +28,30 @@ enum ext_clk_e {
extern unsigned int external_clk[ext_clk_count];
enum clk_e {
core_pll_clk,
pass_pll_clk,
tetris_pll_clk,
ddr3a_pll_clk,
ddr3b_pll_clk,
sys_clk0_clk,
sys_clk0_1_clk,
sys_clk0_2_clk,
sys_clk0_3_clk,
sys_clk0_4_clk,
sys_clk0_6_clk,
sys_clk0_8_clk,
sys_clk0_12_clk,
sys_clk0_24_clk,
sys_clk1_clk,
sys_clk1_3_clk,
sys_clk1_4_clk,
sys_clk1_6_clk,
sys_clk1_12_clk,
sys_clk2_clk,
sys_clk3_clk
};
#define CLK_LIST(CLK)\
CLK(0, core_pll_clk)\
CLK(1, pass_pll_clk)\
CLK(2, tetris_pll_clk)\
CLK(3, ddr3a_pll_clk)\
CLK(4, ddr3b_pll_clk)\
CLK(5, sys_clk0_clk)\
CLK(6, sys_clk0_1_clk)\
CLK(7, sys_clk0_2_clk)\
CLK(8, sys_clk0_3_clk)\
CLK(9, sys_clk0_4_clk)\
CLK(10, sys_clk0_6_clk)\
CLK(11, sys_clk0_8_clk)\
CLK(12, sys_clk0_12_clk)\
CLK(13, sys_clk0_24_clk)\
CLK(14, sys_clk1_clk)\
CLK(15, sys_clk1_3_clk)\
CLK(16, sys_clk1_4_clk)\
CLK(17, sys_clk1_6_clk)\
CLK(18, sys_clk1_12_clk)\
CLK(19, sys_clk2_clk)\
CLK(20, sys_clk3_clk)
#define PLLSET_CMD_LIST "<pa|arm|ddr3a|ddr3b>"
#define KS2_CLK1_6 sys_clk0_6_clk

95
arch/arm/include/asm/arch-keystone/clock-k2l.h Normal file
View file

@ -0,0 +1,95 @@
/*
* K2L: Clock management APIs
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_CLOCK_K2L_H
#define __ASM_ARCH_CLOCK_K2L_H
enum ext_clk_e {
sys_clk,
alt_core_clk,
pa_clk,
tetris_clk,
ddr3_clk,
pcie_clk,
sgmii_clk,
usb_clk,
rp1_clk,
ext_clk_count /* number of external clocks */
};
extern unsigned int external_clk[ext_clk_count];
#define CLK_LIST(CLK)\
CLK(0, core_pll_clk)\
CLK(1, pass_pll_clk)\
CLK(2, tetris_pll_clk)\
CLK(3, ddr3_pll_clk)\
CLK(4, sys_clk0_clk)\
CLK(5, sys_clk0_1_clk)\
CLK(6, sys_clk0_2_clk)\
CLK(7, sys_clk0_3_clk)\
CLK(8, sys_clk0_4_clk)\
CLK(9, sys_clk0_6_clk)\
CLK(10, sys_clk0_8_clk)\
CLK(11, sys_clk0_12_clk)\
CLK(12, sys_clk0_24_clk)\
CLK(13, sys_clk1_clk)\
CLK(14, sys_clk1_3_clk)\
CLK(15, sys_clk1_4_clk)\
CLK(16, sys_clk1_6_clk)\
CLK(17, sys_clk1_12_clk)\
CLK(18, sys_clk2_clk)\
CLK(19, sys_clk3_clk)\
#define PLLSET_CMD_LIST "<pa|arm|ddr3>"
#define KS2_CLK1_6 sys_clk0_6_clk
/* PLL identifiers */
enum pll_type_e {
CORE_PLL,
PASS_PLL,
TETRIS_PLL,
DDR3_PLL,
};
enum {
SPD800,
SPD1000,
SPD1200,
SPD1350,
SPD1400,
SPD_RSV
};
#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
#define CORE_PLL_1000 {CORE_PLL, 114, 7, 2}
#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2}
#define CORE_PLL_1198 {CORE_PLL, 39, 2, 2}
#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2}
#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2}
#define PASS_PLL_983 {PASS_PLL, 16, 1, 2}
#define PASS_PLL_1050 {PASS_PLL, 205, 12, 2}
#define TETRIS_PLL_491 {TETRIS_PLL, 8, 1, 2}
#define TETRIS_PLL_737 {TETRIS_PLL, 12, 1, 2}
#define TETRIS_PLL_799 {TETRIS_PLL, 13, 1, 2}
#define TETRIS_PLL_983 {TETRIS_PLL, 16, 1, 2}
#define TETRIS_PLL_1000 {TETRIS_PLL, 114, 7, 2}
#define TETRIS_PLL_1167 {TETRIS_PLL, 19, 1, 2}
#define TETRIS_PLL_1198 {TETRIS_PLL, 39, 2, 2}
#define TETRIS_PLL_1228 {TETRIS_PLL, 20, 1, 2}
#define TETRIS_PLL_1352 {TETRIS_PLL, 22, 1, 2}
#define TETRIS_PLL_1401 {TETRIS_PLL, 114, 5, 2}
#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2}
#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4}
#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6}
#endif

13
arch/arm/include/asm/arch-keystone/clock.h
View file

@ -20,10 +20,22 @@
#include <asm/arch/clock-k2e.h>
#endif
#ifdef CONFIG_SOC_K2L
#include <asm/arch/clock-k2l.h>
#endif
#define MAIN_PLL CORE_PLL
#include <asm/types.h>
#define GENERATE_ENUM(NUM, ENUM) ENUM = NUM,
#define GENERATE_INDX_STR(NUM, STRING) #NUM"\t- "#STRING"\n"
#define CLOCK_INDEXES_LIST CLK_LIST(GENERATE_INDX_STR)
enum clk_e {
CLK_LIST(GENERATE_ENUM)
};
struct keystone_pll_regs {
u32 reg0;
u32 reg1;
@ -46,6 +58,7 @@ void init_pll(const struct pll_init_data *data);
unsigned long clk_get_rate(unsigned int clk);
unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
int clk_set_rate(unsigned int clk, unsigned long hz);
void pass_pll_pa_clk_enable(void);
int get_max_dev_speed(void);
int get_max_arm_speed(void);

6
arch/arm/include/asm/arch-keystone/ddr3.h
View file

@ -49,8 +49,14 @@ struct ddr3_emif_config {
};
void ddr3_init(void);
int ddr3_get_size(void);
void ddr3_reset_ddrphy(void);
void ddr3_init_ecc(u32 base);
void ddr3_disable_ecc(u32 base);
void ddr3_check_ecc_int(u32 base);
int ddr3_ecc_support_rmw(u32 base);
void ddr3_err_reset_workaround(void);
void ddr3_enable_ecc(u32 base, int test);
void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);

237
arch/arm/include/asm/arch-keystone/emac_defs.h
View file

@ -1,237 +0,0 @@
/*
* emac definitions for keystone2 devices
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _EMAC_DEFS_H_
#define _EMAC_DEFS_H_
#include <asm/arch/hardware.h>
#include <asm/io.h>
#define EMAC_EMACSL_BASE_ADDR (KS2_PASS_BASE + 0x00090900)
#define EMAC_MDIO_BASE_ADDR (KS2_PASS_BASE + 0x00090300)
#define EMAC_SGMII_BASE_ADDR (KS2_PASS_BASE + 0x00090100)
#define KEYSTONE2_EMAC_GIG_ENABLE
#define MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
#ifdef CONFIG_SOC_K2HK
/* MDIO module input frequency */
#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk))
/* MDIO clock output frequency */
#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 1.0 MHz */
#endif
/* MII Status Register */
#define MII_STATUS_REG 1
#define MII_STATUS_LINK_MASK (0x4)
/* Marvell 88E1111 PHY ID */
#define PHY_MARVELL_88E1111 (0x01410cc0)
#define MDIO_CONTROL_IDLE (0x80000000)
#define MDIO_CONTROL_ENABLE (0x40000000)
#define MDIO_CONTROL_FAULT_ENABLE (0x40000)
#define MDIO_CONTROL_FAULT (0x80000)
#define MDIO_USERACCESS0_GO (0x80000000)
#define MDIO_USERACCESS0_WRITE_READ (0x0)
#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
#define MDIO_USERACCESS0_ACK (0x20000000)
#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7)
#define EMAC_MACCONTROL_GIGFORCE (1 << 17)
#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15)
#define EMAC_MIN_ETHERNET_PKT_SIZE 60
struct mac_sl_cfg {
u_int32_t max_rx_len; /* Maximum receive packet length. */
u_int32_t ctl; /* Control bitfield */
};
/*
* Definition: Control bitfields used in the ctl field of hwGmacSlCfg_t
*/
#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES (1 << 24)
#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES (1 << 23)
#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES (1 << 22)
#define GMACSL_RX_ENABLE_EXT_CTL (1 << 18)
#define GMACSL_RX_ENABLE_GIG_FORCE (1 << 17)
#define GMACSL_RX_ENABLE_IFCTL_B (1 << 16)
#define GMACSL_RX_ENABLE_IFCTL_A (1 << 15)
#define GMACSL_RX_ENABLE_CMD_IDLE (1 << 11)
#define GMACSL_TX_ENABLE_SHORT_GAP (1 << 10)
#define GMACSL_ENABLE_GIG_MODE (1 << 7)
#define GMACSL_TX_ENABLE_PACE (1 << 6)
#define GMACSL_ENABLE (1 << 5)
#define GMACSL_TX_ENABLE_FLOW_CTL (1 << 4)
#define GMACSL_RX_ENABLE_FLOW_CTL (1 << 3)
#define GMACSL_ENABLE_LOOPBACK (1 << 1)
#define GMACSL_ENABLE_FULL_DUPLEX (1 << 0)
/*
* DEFINTITION: function return values
*/
#define GMACSL_RET_OK 0
#define GMACSL_RET_INVALID_PORT -1
#define GMACSL_RET_WARN_RESET_INCOMPLETE -2
#define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3
#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4
/* Register offsets */
#define CPGMACSL_REG_ID 0x00
#define CPGMACSL_REG_CTL 0x04
#define CPGMACSL_REG_STATUS 0x08
#define CPGMACSL_REG_RESET 0x0c
#define CPGMACSL_REG_MAXLEN 0x10
#define CPGMACSL_REG_BOFF 0x14
#define CPGMACSL_REG_RX_PAUSE 0x18
#define CPGMACSL_REG_TX_PAURSE 0x1c
#define CPGMACSL_REG_EM_CTL 0x20
#define CPGMACSL_REG_PRI 0x24
/* Soft reset register values */
#define CPGMAC_REG_RESET_VAL_RESET_MASK (1 << 0)
#define CPGMAC_REG_RESET_VAL_RESET (1 << 0)
/* Maxlen register values */
#define CPGMAC_REG_MAXLEN_LEN 0x3fff
/* Control bitfields */
#define CPSW_CTL_P2_PASS_PRI_TAGGED (1 << 5)
#define CPSW_CTL_P1_PASS_PRI_TAGGED (1 << 4)
#define CPSW_CTL_P0_PASS_PRI_TAGGED (1 << 3)
#define CPSW_CTL_P0_ENABLE (1 << 2)
#define CPSW_CTL_VLAN_AWARE (1 << 1)
#define CPSW_CTL_FIFO_LOOPBACK (1 << 0)
#define DEVICE_CPSW_NUM_PORTS 5 /* 5 switch ports */
#define DEVICE_CPSW_BASE (0x02090800)
#define target_get_switch_ctl() CPSW_CTL_P0_ENABLE /* Enable port 0 */
#define SWITCH_MAX_PKT_SIZE 9000
/* Register offsets */
#define CPSW_REG_CTL 0x004
#define CPSW_REG_STAT_PORT_EN 0x00c
#define CPSW_REG_MAXLEN 0x040
#define CPSW_REG_ALE_CONTROL 0x608
#define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x)*4)
/* Register values */
#define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf
#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000)
#define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010)
#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3
#define SGMII_REG_STATUS_LOCK BIT(4)
#define SGMII_REG_STATUS_LINK BIT(0)
#define SGMII_REG_STATUS_AUTONEG BIT(2)
#define SGMII_REG_CONTROL_AUTONEG BIT(0)
#define SGMII_REG_CONTROL_MASTER BIT(5)
#define SGMII_REG_MR_ADV_ENABLE BIT(0)
#define SGMII_REG_MR_ADV_LINK BIT(15)
#define SGMII_REG_MR_ADV_FULL_DUPLEX BIT(12)
#define SGMII_REG_MR_ADV_GIG_MODE BIT(11)
#define SGMII_LINK_MAC_MAC_AUTONEG 0
#define SGMII_LINK_MAC_PHY 1
#define SGMII_LINK_MAC_MAC_FORCED 2
#define SGMII_LINK_MAC_FIBER 3
#define SGMII_LINK_MAC_PHY_FORCED 4
#define TARGET_SGMII_BASE KS2_PASS_BASE + 0x00090100
#define TARGET_SGMII_BASE_ADDRESSES {KS2_PASS_BASE + 0x00090100, \
KS2_PASS_BASE + 0x00090200, \
KS2_PASS_BASE + 0x00090400, \
KS2_PASS_BASE + 0x00090500}
#define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
/*
* SGMII registers
*/
#define SGMII_IDVER_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x000)
#define SGMII_SRESET_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x004)
#define SGMII_CTL_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x010)
#define SGMII_STATUS_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x014)
#define SGMII_MRADV_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x018)
#define SGMII_LPADV_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x020)
#define SGMII_TXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x030)
#define SGMII_RXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x034)
#define SGMII_AUXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x038)
#define DEVICE_EMACSL_BASE(x) (KS2_PASS_BASE + 0x00090900 + (x) * 0x040)
#define DEVICE_N_GMACSL_PORTS 4
#define DEVICE_EMACSL_RESET_POLL_COUNT 100
#define DEVICE_PSTREAM_CFG_REG_ADDR (KS2_PASS_BASE + 0x604)
#ifdef CONFIG_SOC_K2HK
#define DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI 0x06060606
#endif
#define hw_config_streaming_switch() \
writel(DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI,\
DEVICE_PSTREAM_CFG_REG_ADDR);
/* EMAC MDIO Registers Structure */
struct mdio_regs {
dv_reg version;
dv_reg control;
dv_reg alive;
dv_reg link;
dv_reg linkintraw;
dv_reg linkintmasked;
u_int8_t rsvd0[8];
dv_reg userintraw;
dv_reg userintmasked;
dv_reg userintmaskset;
dv_reg userintmaskclear;
u_int8_t rsvd1[80];
dv_reg useraccess0;
dv_reg userphysel0;
dv_reg useraccess1;
dv_reg userphysel1;
};
/* Ethernet MAC Registers Structure */
struct emac_regs {
dv_reg idver;
dv_reg maccontrol;
dv_reg macstatus;
dv_reg soft_reset;
dv_reg rx_maxlen;
u32 rsvd0;
dv_reg rx_pause;
dv_reg tx_pause;
dv_reg emcontrol;
dv_reg pri_map;
u32 rsvd1[6];
};
#define SGMII_ACCESS(port, reg) \
*((volatile unsigned int *)(sgmiis[port] + reg))
struct eth_priv_t {
char int_name[32];
int rx_flow;
int phy_addr;
int slave_port;
int sgmii_link_type;
};
extern struct eth_priv_t eth_priv_cfg[];
int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
void sgmii_serdes_setup_156p25mhz(void);
void sgmii_serdes_shutdown(void);
#endif /* _EMAC_DEFS_H_ */

23
arch/arm/include/asm/arch-keystone/hardware-k2e.h
View file

@ -34,11 +34,34 @@
#define KS2_LPSC_PCIE_1 27
#define KS2_LPSC_XGE 50
/* MSMC */
#define KS2_MSMC_SEGMENT_PCIE1 13
/* Chip Interrupt Controller */
#define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */
#define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */
/* SGMII SerDes */
#define KS2_SGMII_SERDES2_BASE 0x02324000
#define KS2_LANES_PER_SGMII_SERDES 4
/* Number of DSP cores */
#define KS2_NUM_DSPS 1
/* NETCP pktdma */
#define KS2_NETCP_PDMA_CTRL_BASE 0x24186000
#define KS2_NETCP_PDMA_TX_BASE 0x24187000
#define KS2_NETCP_PDMA_TX_CH_NUM 21
#define KS2_NETCP_PDMA_RX_BASE 0x24188000
#define KS2_NETCP_PDMA_RX_CH_NUM 91
#define KS2_NETCP_PDMA_SCHED_BASE 0x24186100
#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x24189000
#define KS2_NETCP_PDMA_RX_FLOW_NUM 96
#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001
#define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002
#define KS2_NETCP_PDMA_TX_SND_QUEUE 896
/* NETCP */
#define KS2_NETCP_BASE 0x24000000
#endif

25
arch/arm/include/asm/arch-keystone/hardware-k2hk.h
View file

@ -10,8 +10,6 @@
#ifndef __ASM_ARCH_HARDWARE_K2HK_H
#define __ASM_ARCH_HARDWARE_K2HK_H
#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
#define KS2_ARM_PLL_EN BIT(13)
/* PA SS Registers */
@ -81,7 +79,30 @@
#define KS2_DDR3B_EMIF_DATA_BASE 0x60000000
#define KS2_DDR3B_DDRPHYC 0x02328000
#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3 /* DDR3 ECC system irq number */
#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D /* DDR3 ECC int mapped to CIC2
channel 29 */
/* SGMII SerDes */
#define KS2_LANES_PER_SGMII_SERDES 4
/* Number of DSP cores */
#define KS2_NUM_DSPS 8
/* NETCP pktdma */
#define KS2_NETCP_PDMA_CTRL_BASE 0x02004000
#define KS2_NETCP_PDMA_TX_BASE 0x02004400
#define KS2_NETCP_PDMA_TX_CH_NUM 9
#define KS2_NETCP_PDMA_RX_BASE 0x02004800
#define KS2_NETCP_PDMA_RX_CH_NUM 26
#define KS2_NETCP_PDMA_SCHED_BASE 0x02004c00
#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x02005000
#define KS2_NETCP_PDMA_RX_FLOW_NUM 32
#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001
#define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002
#define KS2_NETCP_PDMA_TX_SND_QUEUE 648
/* NETCP */
#define KS2_NETCP_BASE 0x02000000
#endif /* __ASM_ARCH_HARDWARE_H */

101
arch/arm/include/asm/arch-keystone/hardware-k2l.h Normal file
View file

@ -0,0 +1,101 @@
/*
* K2L: SoC definitions
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ASM_ARCH_HARDWARE_K2L_H
#define __ASM_ARCH_HARDWARE_K2L_H
#define KS2_ARM_PLL_EN BIT(13)
/* PA SS Registers */
#define KS2_PASS_BASE 0x26000000
/* Power and Sleep Controller (PSC) Domains */
#define KS2_LPSC_MOD 0
#define KS2_LPSC_DFE_IQN_SYS 1
#define KS2_LPSC_USB 2
#define KS2_LPSC_EMIF25_SPI 3
#define KS2_LPSC_TSIP 4
#define KS2_LPSC_DEBUGSS_TRC 5
#define KS2_LPSC_TETB_TRC 6
#define KS2_LPSC_PKTPROC 7
#define KS2_LPSC_PA KS2_LPSC_PKTPROC
#define KS2_LPSC_SGMII 8
#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII
#define KS2_LPSC_CRYPTO 9
#define KS2_LPSC_PCIE0 10
#define KS2_LPSC_PCIE1 11
#define KS2_LPSC_JESD_MISC 12
#define KS2_LPSC_CHIP_SRSS 13
#define KS2_LPSC_MSMC 14
#define KS2_LPSC_GEM_1 16
#define KS2_LPSC_GEM_2 17
#define KS2_LPSC_GEM_3 18
#define KS2_LPSC_EMIF4F_DDR3 23
#define KS2_LPSC_TAC 25
#define KS2_LPSC_RAC 26
#define KS2_LPSC_DDUC4X_CFR2X_BB 27
#define KS2_LPSC_FFTC_A 28
#define KS2_LPSC_OSR 34
#define KS2_LPSC_TCP3D_0 35
#define KS2_LPSC_TCP3D_1 37
#define KS2_LPSC_VCP2X4_A 39
#define KS2_LPSC_VCP2X4_B 40
#define KS2_LPSC_VCP2X4_C 41
#define KS2_LPSC_VCP2X4_D 42
#define KS2_LPSC_BCP 47
#define KS2_LPSC_DPD4X 48
#define KS2_LPSC_FFTC_B 49
#define KS2_LPSC_IQN_AIL 50
/* MSMC */
#define KS2_MSMC_SEGMENT_PCIE1 14
/* Chip Interrupt Controller */
#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3
#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D
/* OSR */
#define KS2_OSR_DATA_BASE 0x70000000 /* OSR data base */
#define KS2_OSR_CFG_BASE 0x02348c00 /* OSR config base */
#define KS2_OSR_ECC_VEC 0x08 /* ECC Vector reg */
#define KS2_OSR_ECC_CTRL 0x14 /* ECC control reg */
/* OSR ECC Vector register */
#define KS2_OSR_ECC_VEC_TRIG_RD BIT(15) /* trigger a read op */
#define KS2_OSR_ECC_VEC_RD_DONE BIT(24) /* read complete */
#define KS2_OSR_ECC_VEC_RAM_ID_SH 0 /* RAM ID shift */
#define KS2_OSR_ECC_VEC_RD_ADDR_SH 16 /* read address shift */
/* OSR ECC control register */
#define KS2_OSR_ECC_CTRL_EN BIT(0) /* ECC enable bit */
#define KS2_OSR_ECC_CTRL_CHK BIT(1) /* ECC check bit */
#define KS2_OSR_ECC_CTRL_RMW BIT(2) /* ECC check bit */
/* Number of OSR RAM banks */
#define KS2_OSR_NUM_RAM_BANKS 4
/* OSR memory size */
#define KS2_OSR_SIZE 0x100000
/* Number of DSP cores */
#define KS2_NUM_DSPS 4
/* NETCP pktdma */
#define KS2_NETCP_PDMA_CTRL_BASE 0x26186000
#define KS2_NETCP_PDMA_TX_BASE 0x26187000
#define KS2_NETCP_PDMA_TX_CH_NUM 21
#define KS2_NETCP_PDMA_RX_BASE 0x26188000
#define KS2_NETCP_PDMA_RX_CH_NUM 91
#define KS2_NETCP_PDMA_SCHED_BASE 0x26186100
#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x26189000
#define KS2_NETCP_PDMA_RX_FLOW_NUM 96
#define KS2_NETCP_PDMA_TX_SND_QUEUE 896
#endif /* __ASM_ARCH_HARDWARE_K2L_H */

98
arch/arm/include/asm/arch-keystone/hardware.h
View file

@ -87,6 +87,52 @@ typedef volatile unsigned int *dv_reg_p;
#define KS2_DDR3_PLLCTRL_PHY_RESET 0x80000000
/* DDR3 ECC */
#define KS2_DDR3_ECC_INT_STATUS_OFFSET 0x0AC
#define KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET 0x0B4
#define KS2_DDR3_ECC_CTRL_OFFSET 0x110
#define KS2_DDR3_ECC_ADDR_RANGE1_OFFSET 0x114
#define KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET 0x130
#define KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET 0x13C
/* DDR3 ECC Interrupt Status register */
#define KS2_DDR3_1B_ECC_ERR_SYS BIT(5)
#define KS2_DDR3_2B_ECC_ERR_SYS BIT(4)
#define KS2_DDR3_WR_ECC_ERR_SYS BIT(3)
/* DDR3 ECC Control register */
#define KS2_DDR3_ECC_EN BIT(31)
#define KS2_DDR3_ECC_ADDR_RNG_PROT BIT(30)
#define KS2_DDR3_ECC_VERIFY_EN BIT(29)
#define KS2_DDR3_ECC_RMW_EN BIT(28)
#define KS2_DDR3_ECC_ADDR_RNG_1_EN BIT(0)
#define KS2_DDR3_ECC_ENABLE (KS2_DDR3_ECC_EN | \
KS2_DDR3_ECC_ADDR_RNG_PROT | \
KS2_DDR3_ECC_VERIFY_EN)
/* EDMA */
#define KS2_EDMA0_BASE 0x02700000
/* EDMA3 register offsets */
#define KS2_EDMA_QCHMAP0 0x0200
#define KS2_EDMA_IPR 0x1068
#define KS2_EDMA_ICR 0x1070
#define KS2_EDMA_QEECR 0x1088
#define KS2_EDMA_QEESR 0x108c
#define KS2_EDMA_PARAM_1(x) (0x4020 + (4 * x))
/* Chip Interrupt Controller */
#define KS2_CIC2_BASE 0x02608000
/* Chip Interrupt Controller register offsets */
#define KS2_CIC_CTRL 0x04
#define KS2_CIC_HOST_CTRL 0x0C
#define KS2_CIC_GLOBAL_ENABLE 0x10
#define KS2_CIC_SYS_ENABLE_IDX_SET 0x28
#define KS2_CIC_HOST_ENABLE_IDX_SET 0x34
#define KS2_CIC_CHAN_MAP(n) (0x0400 + (n << 2))
#define KS2_UART0_BASE 0x02530c00
#define KS2_UART1_BASE 0x02531000
@ -140,19 +186,51 @@ typedef volatile unsigned int *dv_reg_p;
/* Flag from ks2_debug options to check if DSPs need to stay ON */
#define DBG_LEAVE_DSPS_ON 0x1
/* MSMC control */
#define KS2_MSMC_CTRL_BASE 0x0bc00000
#define KS2_MSMC_DATA_BASE 0x0c000000
#define KS2_MSMC_SEGMENT_TETRIS 8
#define KS2_MSMC_SEGMENT_NETCP 9
#define KS2_MSMC_SEGMENT_QM_PDSP 10
#define KS2_MSMC_SEGMENT_PCIE0 11
/* MSMC segment size shift bits */
#define KS2_MSMC_SEG_SIZE_SHIFT 12
#define KS2_MSMC_MAP_SEG_NUM (2 << (30 - KS2_MSMC_SEG_SIZE_SHIFT))
#define KS2_MSMC_DST_SEG_BASE (CONFIG_SYS_LPAE_SDRAM_BASE >> \
KS2_MSMC_SEG_SIZE_SHIFT)
/* Device speed */
#define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
#define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
/* Queue manager */
#define KS2_QM_MANAGER_BASE 0x02a02000
#define KS2_QM_BASE_ADDRESS 0x23a80000
#define KS2_QM_CONF_BASE 0x02a02000
#define KS2_QM_DESC_SETUP_BASE 0x02a03000
#define KS2_QM_MANAGER_QUEUES_BASEi 0x02a80000
#define KS2_QM_STATUS_RAM_BASE 0x02a06000
#define KS2_QM_INTD_CONF_BASE 0x02a0c000
#define KS2_QM_PDSP1_CMD_BASE 0x02a20000
#define KS2_QM_PDSP1_CTRL_BASE 0x02a0f000
#define KS2_QM_PDSP1_IRAM_BASE 0x02a10000
#define KS2_QM_MANAGER_QUEUES_BASE 0x02a80000
#define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
#define KS2_QM_QUEUE_STATUS_BASE 0x02a40000
#define KS2_QM_LINK_RAM_BASE 0x00100000
#define KS2_QM_REGION_NUM 64
#define KS2_QM_QPOOL_NUM 4000
/* MSMC control */
#define KS2_MSMC_CTRL_BASE 0x0bc00000
/* USB */
#define KS2_USB_SS_BASE 0x02680000
#define KS2_USB_HOST_XHCI_BASE (KS2_USB_SS_BASE + 0x10000)
#define KS2_DEV_USB_PHY_BASE 0x02620738
#define KS2_USB_PHY_CFG_BASE 0x02630000
#define KS2_MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
/* SGMII SerDes */
#define KS2_SGMII_SERDES_BASE 0x0232a000
#ifdef CONFIG_SOC_K2HK
#include <asm/arch/hardware-k2hk.h>
@ -162,6 +240,10 @@ typedef volatile unsigned int *dv_reg_p;
#include <asm/arch/hardware-k2e.h>
#endif
#ifdef CONFIG_SOC_K2L
#include <asm/arch/hardware-k2l.h>
#endif
#ifndef __ASSEMBLY__
static inline int cpu_is_k2hk(void)
{
@ -179,6 +261,14 @@ static inline int cpu_is_k2e(void)
return (part_no == 0xb9a6) ? 1 : 0;
}
static inline int cpu_is_k2l(void)
{
unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
unsigned int part_no = (jtag_id >> 12) & 0xffff;
return (part_no == 0xb9a7) ? 1 : 0;
}
static inline int cpu_revision(void)
{
unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);

28
arch/arm/include/asm/arch-keystone/msmc.h
View file

@ -12,6 +12,34 @@
#include <asm/arch/hardware.h>
enum mpax_seg_size {
MPAX_SEG_4K = 0x0b,
MPAX_SEG_8K,
MPAX_SEG_16K,
MPAX_SEG_32K,
MPAX_SEG_64K,
MPAX_SEG_128K,
MPAX_SEG_256K,
MPAX_SEG_512K,
MPAX_SEG_1M,
MPAX_SEG_2M,
MPAX_SEG_4M,
MPAX_SEG_8M,
MPAX_SEG_16M,
MPAX_SEG_32M,
MPAX_SEG_64M,
MPAX_SEG_128M,
MPAX_SEG_256M,
MPAX_SEG_512M,
MPAX_SEG_1G,
MPAX_SEG_2G,
MPAX_SEG_4G
};
void msmc_share_all_segments(int priv_id);
void msmc_get_ses_mpax(int priv_id, int ses_pair, u32 *mpax);
void msmc_set_ses_mpax(int priv_id, int ses_pair, u32 *mpax);
void msmc_map_ses_segment(int priv_id, int ses_pair,
u32 src_pfn, u32 dst_pfn, enum mpax_seg_size size);
#endif

12
arch/arm/include/asm/arch-keystone/spl.h
View file

@ -1,12 +0,0 @@
/*
* (C) Copyright 2012-2014
* Texas Instruments, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_SPL_H_
#define _ASM_ARCH_SPL_H_
#define BOOT_DEVICE_SPI 2
#endif

21
arch/arm/include/asm/arch-keystone/xhci-keystone.h Normal file
View file

@ -0,0 +1,21 @@
/*
* USB 3.0 DRD Controller
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define USB3_PHY_REF_SSP_EN BIT(29)
#define USB3_PHY_OTG_VBUSVLDECTSEL BIT(16)
/* KEYSTONE2 XHCI PHY register structure */
struct keystone_xhci_phy {
unsigned int phy_utmi; /* ctl0 */
unsigned int phy_pipe; /* ctl1 */
unsigned int phy_param_ctrl_1; /* ctl2 */
unsigned int phy_param_ctrl_2; /* ctl3 */
unsigned int phy_clock; /* ctl4 */
unsigned int phy_pll; /* ctl5 */
};

2
arch/arm/include/asm/arch-omap3/mux.h
View file

@ -281,7 +281,7 @@
#define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18
#define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A
#define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2
#define CONTROL_PADCONF_JTAG_nTRST 0x0A1C
#define CONTROL_PADCONF_JTAG_NTRST 0x0A1C
#define CONTROL_PADCONF_JTAG_TCK 0x0A1E
#define CONTROL_PADCONF_JTAG_TMS 0x0A20
#define CONTROL_PADCONF_JTAG_TDI 0x0A22

16
arch/arm/include/asm/arch-keystone/keystone_nav.h → arch/arm/include/asm/ti-common/keystone_nav.h
View file

@ -13,10 +13,6 @@
#include <asm/arch/hardware.h>
#include <asm/io.h>
enum soc_type_t {
k2hk
};
#define QM_OK 0
#define QM_ERR -1
#define QM_DESC_TYPE_HOST 0
@ -173,6 +169,8 @@ struct pktdma_cfg {
u32 rx_flow; /* flow that is used for RX */
};
extern struct pktdma_cfg netcp_pktdma;
/*
* packet dma user allocates memory for rx buffers
* and describe it in the following structure
@ -184,10 +182,10 @@ struct rx_buff_desc {
u32 rx_flow;
};
int netcp_close(void);
int netcp_init(struct rx_buff_desc *rx_buffers);
int netcp_send(u32 *pkt, int num_bytes, u32 swinfo2);
void *netcp_recv(u32 **pkt, int *num_bytes);
void netcp_release_rxhd(void *hd);
int ksnav_close(struct pktdma_cfg *pktdma);
int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc *rx_buffers);
int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes, u32 swinfo2);
void *ksnav_recv(struct pktdma_cfg *pktdma, u32 **pkt, int *num_bytes);
void ksnav_release_rxhd(struct pktdma_cfg *pktdma, void *hd);
#endif /* _KEYSTONE_NAV_H_ */

249
arch/arm/include/asm/ti-common/keystone_net.h Normal file
View file

@ -0,0 +1,249 @@
/*
* emac definitions for keystone2 devices
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _KEYSTONE_NET_H_
#define _KEYSTONE_NET_H_
#include <asm/io.h>
/* EMAC */
#ifdef CONFIG_KSNET_NETCP_V1_0
#define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00090000)
#define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x900)
#define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x300)
#define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x100)
#define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x040)
/* Register offsets */
#define CPGMACSL_REG_CTL 0x04
#define CPGMACSL_REG_STATUS 0x08
#define CPGMACSL_REG_RESET 0x0c
#define CPGMACSL_REG_MAXLEN 0x10
#elif defined CONFIG_KSNET_NETCP_V1_5
#define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00200000)
#define CPGMACSL_REG_RX_PRI_MAP 0x020
#define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x22000)
#define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x00f00)
#define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x00100)
#define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x1000)
/* Register offsets */
#define CPGMACSL_REG_CTL 0x330
#define CPGMACSL_REG_STATUS 0x334
#define CPGMACSL_REG_RESET 0x338
#define CPGMACSL_REG_MAXLEN 0x024
#endif
#define KEYSTONE2_EMAC_GIG_ENABLE
#define MAC_ID_BASE_ADDR CONFIG_KSNET_MAC_ID_BASE
/* MDIO module input frequency */
#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk))
/* MDIO clock output frequency */
#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */
/* MII Status Register */
#define MII_STATUS_REG 1
#define MII_STATUS_LINK_MASK 0x4
#define MDIO_CONTROL_IDLE 0x80000000
#define MDIO_CONTROL_ENABLE 0x40000000
#define MDIO_CONTROL_FAULT_ENABLE 0x40000
#define MDIO_CONTROL_FAULT 0x80000
#define MDIO_USERACCESS0_GO 0x80000000
#define MDIO_USERACCESS0_WRITE_READ 0x0
#define MDIO_USERACCESS0_WRITE_WRITE 0x40000000
#define MDIO_USERACCESS0_ACK 0x20000000
#define EMAC_MACCONTROL_MIIEN_ENABLE 0x20
#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE 0x1
#define EMAC_MACCONTROL_GIGABIT_ENABLE BIT(7)
#define EMAC_MACCONTROL_GIGFORCE BIT(17)
#define EMAC_MACCONTROL_RMIISPEED_100 BIT(15)
#define EMAC_MIN_ETHERNET_PKT_SIZE 60
struct mac_sl_cfg {
u_int32_t max_rx_len; /* Maximum receive packet length. */
u_int32_t ctl; /* Control bitfield */
};
/**
* Definition: Control bitfields used in the ctl field of mac_sl_cfg
*/
#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES BIT(24)
#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES BIT(23)
#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES BIT(22)
#define GMACSL_RX_ENABLE_EXT_CTL BIT(18)
#define GMACSL_RX_ENABLE_GIG_FORCE BIT(17)
#define GMACSL_RX_ENABLE_IFCTL_B BIT(16)
#define GMACSL_RX_ENABLE_IFCTL_A BIT(15)
#define GMACSL_RX_ENABLE_CMD_IDLE BIT(11)
#define GMACSL_TX_ENABLE_SHORT_GAP BIT(10)
#define GMACSL_ENABLE_GIG_MODE BIT(7)
#define GMACSL_TX_ENABLE_PACE BIT(6)
#define GMACSL_ENABLE BIT(5)
#define GMACSL_TX_ENABLE_FLOW_CTL BIT(4)
#define GMACSL_RX_ENABLE_FLOW_CTL BIT(3)
#define GMACSL_ENABLE_LOOPBACK BIT(1)
#define GMACSL_ENABLE_FULL_DUPLEX BIT(0)
/* EMAC SL function return values */
#define GMACSL_RET_OK 0
#define GMACSL_RET_INVALID_PORT -1
#define GMACSL_RET_WARN_RESET_INCOMPLETE -2
#define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3
#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4
/* EMAC SL register definitions */
#define DEVICE_EMACSL_RESET_POLL_COUNT 100
/* Soft reset register values */
#define CPGMAC_REG_RESET_VAL_RESET_MASK BIT(0)
#define CPGMAC_REG_RESET_VAL_RESET BIT(0)
#define CPGMAC_REG_MAXLEN_LEN 0x3fff
/* CPSW */
/* Control bitfields */
#define CPSW_CTL_P2_PASS_PRI_TAGGED BIT(5)
#define CPSW_CTL_P1_PASS_PRI_TAGGED BIT(4)
#define CPSW_CTL_P0_PASS_PRI_TAGGED BIT(3)
#define CPSW_CTL_P0_ENABLE BIT(2)
#define CPSW_CTL_VLAN_AWARE BIT(1)
#define CPSW_CTL_FIFO_LOOPBACK BIT(0)
#define DEVICE_CPSW_NUM_PORTS CONFIG_KSNET_CPSW_NUM_PORTS
#define DEVICE_N_GMACSL_PORTS (DEVICE_CPSW_NUM_PORTS - 1)
#ifdef CONFIG_KSNET_NETCP_V1_0
#define DEVICE_CPSW_BASE (GBETH_BASE + 0x800)
#define CPSW_REG_CTL 0x004
#define CPSW_REG_STAT_PORT_EN 0x00c
#define CPSW_REG_MAXLEN 0x040
#define CPSW_REG_ALE_CONTROL 0x608
#define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x) * 4)
#define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf
#elif defined CONFIG_KSNET_NETCP_V1_5
#define DEVICE_CPSW_BASE (GBETH_BASE + 0x20000)
#define CPSW_REG_CTL 0x00004
#define CPSW_REG_STAT_PORT_EN 0x00014
#define CPSW_REG_MAXLEN 0x01024
#define CPSW_REG_ALE_CONTROL 0x1e008
#define CPSW_REG_ALE_PORTCTL(x) (0x1e040 + (x) * 4)
#define CPSW_REG_VAL_STAT_ENABLE_ALL 0x1ff
#endif
#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000)
#define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010)
#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3
#define target_get_switch_ctl() CPSW_CTL_P0_ENABLE
#define SWITCH_MAX_PKT_SIZE 9000
/* SGMII */
#define SGMII_REG_STATUS_LOCK BIT(4)
#define SGMII_REG_STATUS_LINK BIT(0)
#define SGMII_REG_STATUS_AUTONEG BIT(2)
#define SGMII_REG_CONTROL_AUTONEG BIT(0)
#define SGMII_REG_CONTROL_MASTER BIT(5)
#define SGMII_REG_MR_ADV_ENABLE BIT(0)
#define SGMII_REG_MR_ADV_LINK BIT(15)
#define SGMII_REG_MR_ADV_FULL_DUPLEX BIT(12)
#define SGMII_REG_MR_ADV_GIG_MODE BIT(11)
#define SGMII_LINK_MAC_MAC_AUTONEG 0
#define SGMII_LINK_MAC_PHY 1
#define SGMII_LINK_MAC_MAC_FORCED 2
#define SGMII_LINK_MAC_FIBER 3
#define SGMII_LINK_MAC_PHY_FORCED 4
#ifdef CONFIG_KSNET_NETCP_V1_0
#define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
#elif defined CONFIG_KSNET_NETCP_V1_5
#define SGMII_OFFSET(x) ((x) * 0x100)
#endif
#define SGMII_IDVER_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x000)
#define SGMII_SRESET_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x004)
#define SGMII_CTL_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x010)
#define SGMII_STATUS_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x014)
#define SGMII_MRADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x018)
#define SGMII_LPADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x020)
#define SGMII_TXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x030)
#define SGMII_RXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034)
#define SGMII_AUXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038)
/* PSS */
#ifdef CONFIG_KSNET_NETCP_V1_0
#define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x604)
#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x06060606
#define hw_config_streaming_switch()\
writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR);
#elif defined CONFIG_KSNET_NETCP_V1_5
#define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x500)
#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x0
#define hw_config_streaming_switch()\
writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
DEVICE_PSTREAM_CFG_REG_ADDR);\
writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
DEVICE_PSTREAM_CFG_REG_ADDR+4);\
writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
DEVICE_PSTREAM_CFG_REG_ADDR+8);\
writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\
DEVICE_PSTREAM_CFG_REG_ADDR+12);
#endif
/* EMAC MDIO Registers Structure */
struct mdio_regs {
u32 version;
u32 control;
u32 alive;
u32 link;
u32 linkintraw;
u32 linkintmasked;
u32 rsvd0[2];
u32 userintraw;
u32 userintmasked;
u32 userintmaskset;
u32 userintmaskclear;
u32 rsvd1[20];
u32 useraccess0;
u32 userphysel0;
u32 useraccess1;
u32 userphysel1;
};
struct eth_priv_t {
char int_name[32];
int rx_flow;
int phy_addr;
int slave_port;
int sgmii_link_type;
struct phy_device *phy_dev;
};
int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
void sgmii_serdes_setup_156p25mhz(void);
void sgmii_serdes_shutdown(void);
#endif /* _KEYSTONE_NET_H_ */

55
arch/arm/include/asm/ti-common/keystone_serdes.h Normal file
View file

@ -0,0 +1,55 @@
/*
* Texas Instruments Keystone SerDes driver
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __TI_KEYSTONE_SERDES_H__
#define __TI_KEYSTONE_SERDES_H__
/* SERDES Reference clock */
enum ks2_serdes_clock {
SERDES_CLOCK_100M, /* 100 MHz */
SERDES_CLOCK_122P88M, /* 122.88 MHz */
SERDES_CLOCK_125M, /* 125 MHz */
SERDES_CLOCK_156P25M, /* 156.25 MHz */
SERDES_CLOCK_312P5M, /* 312.5 MHz */
};
/* SERDES Lane Baud Rate */
enum ks2_serdes_rate {
SERDES_RATE_4P9152G, /* 4.9152 GBaud */
SERDES_RATE_5G, /* 5 GBaud */
SERDES_RATE_6P144G, /* 6.144 GBaud */
SERDES_RATE_6P25G, /* 6.25 GBaud */
SERDES_RATE_10p3125g, /* 10.3215 GBaud */
SERDES_RATE_12p5g, /* 12.5 GBaud */
};
/* SERDES Lane Rate Mode */
enum ks2_serdes_rate_mode {
SERDES_FULL_RATE,
SERDES_HALF_RATE,
SERDES_QUARTER_RATE,
};
/* SERDES PHY TYPE */
enum ks2_serdes_interface {
SERDES_PHY_SGMII,
SERDES_PHY_PCSR, /* XGE SERDES */
};
struct ks2_serdes {
enum ks2_serdes_clock clk;
enum ks2_serdes_rate rate;
enum ks2_serdes_rate_mode rate_mode;
enum ks2_serdes_interface intf;
u32 loopback;
};
int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes);
#endif /* __TI_KEYSTONE_SERDES_H__ */

121
arch/arm/include/asm/ti-common/ti-edma3.h Normal file
View file

@ -0,0 +1,121 @@
/*
* Enhanced Direct Memory Access (EDMA3) Controller
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _EDMA3_H_
#define _EDMA3_H_
#include <linux/stddef.h>
#define EDMA3_PARSET_NULL_LINK 0xffff
/*
* All parameter RAM set options
* opt field in edma3_param_set_config structure
*/
#define EDMA3_SLOPT_PRIV_LEVEL BIT(31)
#define EDMA3_SLOPT_PRIV_ID(id) ((0xf & (id)) << 24)
#define EDMA3_SLOPT_INTERM_COMP_CHAIN_ENB BIT(23)
#define EDMA3_SLOPT_TRANS_COMP_CHAIN_ENB BIT(22)
#define EDMA3_SLOPT_INTERM_COMP_INT_ENB BIT(21)
#define EDMA3_SLOPT_TRANS_COMP_INT_ENB BIT(20)
#define EDMA3_SLOPT_COMP_CODE(code) ((0x3f & (code)) << 12)
#define EDMA3_SLOPT_FIFO_WIDTH_8 0
#define EDMA3_SLOPT_FIFO_WIDTH_16 (1 << 8)
#define EDMA3_SLOPT_FIFO_WIDTH_32 (2 << 8)
#define EDMA3_SLOPT_FIFO_WIDTH_64 (3 << 8)
#define EDMA3_SLOPT_FIFO_WIDTH_128 (4 << 8)
#define EDMA3_SLOPT_FIFO_WIDTH_256 (5 << 8)
#define EDMA3_SLOPT_FIFO_WIDTH_SET(w) ((w & 0x7) << 8)
#define EDMA3_SLOPT_STATIC BIT(3)
#define EDMA3_SLOPT_AB_SYNC BIT(2)
#define EDMA3_SLOPT_DST_ADDR_CONST_MODE BIT(1)
#define EDMA3_SLOPT_SRC_ADDR_CONST_MODE BIT(0)
enum edma3_address_mode {
INCR = 0,
FIFO = 1
};
enum edma3_fifo_width {
W8BIT = 0,
W16BIT = 1,
W32BIT = 2,
W64BIT = 3,
W128BIT = 4,
W256BIT = 5
};
enum edma3_sync_dimension {
ASYNC = 0,
ABSYNC = 1
};
/* PaRAM slots are laid out like this */
struct edma3_slot_layout {
u32 opt;
u32 src;
u32 a_b_cnt;
u32 dst;
u32 src_dst_bidx;
u32 link_bcntrld;
u32 src_dst_cidx;
u32 ccnt;
} __packed;
/*
* Use this to assign trigger word number of edma3_slot_layout struct.
* trigger_word_name - is the exact name from edma3_slot_layout.
*/
#define EDMA3_TWORD(trigger_word_name)\
(offsetof(struct edma3_slot_layout, trigger_word_name) / 4)
struct edma3_slot_config {
u32 opt;
u32 src;
u32 dst;
int bcnt;
int acnt;
int ccnt;
int src_bidx;
int dst_bidx;
int src_cidx;
int dst_cidx;
int bcntrld;
int link;
};
struct edma3_channel_config {
int slot;
int chnum;
int complete_code; /* indicate pending complete interrupt */
int trigger_slot_word; /* only used for qedma */
};
void qedma3_start(u32 base, struct edma3_channel_config *cfg);
void qedma3_stop(u32 base, struct edma3_channel_config *cfg);
void edma3_slot_configure(u32 base, int slot, struct edma3_slot_config *cfg);
int edma3_check_for_transfer(u32 base, struct edma3_channel_config *cfg);
void edma3_write_slot(u32 base, int slot, struct edma3_slot_layout *param);
void edma3_read_slot(u32 base, int slot, struct edma3_slot_layout *param);
void edma3_set_dest(u32 base, int slot, u32 dst, enum edma3_address_mode mode,
enum edma3_fifo_width width);
void edma3_set_dest_index(u32 base, unsigned slot, int bidx, int cidx);
void edma3_set_dest_addr(u32 base, int slot, u32 dst);
void edma3_set_src(u32 base, int slot, u32 src, enum edma3_address_mode mode,
enum edma3_fifo_width width);
void edma3_set_src_index(u32 base, unsigned slot, int bidx, int cidx);
void edma3_set_src_addr(u32 base, int slot, u32 src);
void edma3_set_transfer_params(u32 base, int slot, int acnt,
int bcnt, int ccnt, u16 bcnt_rld,
enum edma3_sync_dimension sync_mode);
#endif

2
board/8dtech/eco5pk/eco5pk.h
View file

@ -332,7 +332,7 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
/* JTAG */\
MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \

19
board/compulab/cm_t35/cm_t35.c
View file

@ -53,16 +53,6 @@ static u32 gpmc_net_config[GPMC_MAX_REG] = {
0
};
static u32 gpmc_nand_config[GPMC_MAX_REG] = {
M_NAND_GPMC_CONFIG1,
M_NAND_GPMC_CONFIG2,
M_NAND_GPMC_CONFIG3,
M_NAND_GPMC_CONFIG4,
M_NAND_GPMC_CONFIG5,
M_NAND_GPMC_CONFIG6,
0,
};
#ifdef CONFIG_LCD
#ifdef CONFIG_CMD_NAND
static int splash_load_from_nand(u32 bmp_load_addr)
@ -148,9 +138,6 @@ int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[0],
CONFIG_SYS_NAND_BASE, GPMC_SIZE_16M);
/* board id for Linux */
if (get_cpu_family() == CPU_OMAP34XX)
gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
@ -381,7 +368,7 @@ static void cm_t3x_set_common_muxconf(void)
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/
MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/
MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)); /*JTAG_nTRST*/
MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)); /*JTAG_NTRST*/
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/
@ -457,6 +444,8 @@ void set_muxconf_regs(void)
}
#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
#define SB_T35_WP_GPIO 59
int board_mmc_getcd(struct mmc *mmc)
{
u8 val;
@ -469,7 +458,7 @@ int board_mmc_getcd(struct mmc *mmc)
int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0, 0, 0, -1, 59);
return omap_mmc_init(0, 0, 0, -1, SB_T35_WP_GPIO);
}
#endif

2
board/htkw/mcx/mcx.h
View file

@ -339,7 +339,7 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))\
MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4))\
/* JTAG */\
MUX_VAL(CP(JTAG_nTRST), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(JTAG_NTRST), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(JTAG_TCK), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M4)) \

2
board/logicpd/am3517evm/am3517evm.h
View file

@ -333,7 +333,7 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
/* JTAG */\
MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \

2
board/logicpd/omap3som/omap3logic.c
View file

@ -230,6 +230,6 @@ void set_muxconf_regs(void)
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0));
MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0));
MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0));
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
}

135
board/overo/overo.c
View file

@ -27,12 +27,19 @@
#include <asm/mach-types.h>
#include "overo.h"
#ifdef CONFIG_USB_EHCI
#include <usb.h>
#include <asm/ehci-omap.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
#define TWL4030_I2C_BUS 0
#define EXPANSION_EEPROM_I2C_BUS 2
#define EXPANSION_EEPROM_I2C_ADDRESS 0x51
#define GUMSTIX_EMPTY_EEPROM 0x0
#define GUMSTIX_SUMMIT 0x01000200
#define GUMSTIX_TOBI 0x02000200
#define GUMSTIX_TOBI_DUO 0x03000200
@ -58,22 +65,7 @@ static struct {
char fab_revision[8];
char env_var[16];
char env_setting[64];
} expansion_config;
#if defined(CONFIG_CMD_NET)
static void setup_net_chip(void);
#endif
/* GPMC definitions for LAN9221 chips on Tobi expansion boards */
static const u32 gpmc_lan_config[] = {
NET_LAN9221_GPMC_CONFIG1,
NET_LAN9221_GPMC_CONFIG2,
NET_LAN9221_GPMC_CONFIG3,
NET_LAN9221_GPMC_CONFIG4,
NET_LAN9221_GPMC_CONFIG5,
NET_LAN9221_GPMC_CONFIG6,
/*CONFIG7- computed as params */
};
} expansion_config = {0x0};
static const struct ns16550_platdata overo_serial = {
OMAP34XX_UART3,
@ -226,6 +218,9 @@ int get_sdio2_config(void)
*/
unsigned int get_expansion_id(void)
{
if (expansion_config.device_vendor != 0x0)
return expansion_config.device_vendor;
i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS);
/* return GUMSTIX_NO_EEPROM if eeprom doesn't respond */
@ -254,10 +249,6 @@ int misc_init_r(void)
twl4030_power_init();
twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
#if defined(CONFIG_CMD_NET)
setup_net_chip();
#endif
printf("Board revision: %d\n", get_board_revision());
switch (get_sdio2_config()) {
@ -279,6 +270,7 @@ int misc_init_r(void)
printf("Recognized Summit expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
setenv("defaultdisplay", "dvi");
setenv("expansionname", "summit");
break;
@ -286,6 +278,7 @@ int misc_init_r(void)
printf("Recognized Tobi expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
setenv("defaultdisplay", "dvi");
setenv("expansionname", "tobi");
break;
@ -293,20 +286,20 @@ int misc_init_r(void)
printf("Recognized Tobi Duo expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
/* second lan chip */
enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4],
0x2B000000, GPMC_SIZE_16M);
MUX_GUMSTIX();
break;
case GUMSTIX_PALO35:
printf("Recognized Palo35 expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
setenv("defaultdisplay", "lcd35");
break;
case GUMSTIX_PALO43:
printf("Recognized Palo43 expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
setenv("defaultdisplay", "lcd43");
setenv("expansionname", "palo43");
break;
@ -314,6 +307,7 @@ int misc_init_r(void)
printf("Recognized Chestnut43 expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
setenv("defaultdisplay", "lcd43");
setenv("expansionname", "chestnut43");
break;
@ -321,11 +315,13 @@ int misc_init_r(void)
printf("Recognized Pinto expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
break;
case GUMSTIX_GALLOP43:
printf("Recognized Gallop43 expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
setenv("defaultdisplay", "lcd43");
setenv("expansionname", "gallop43");
break;
@ -333,6 +329,7 @@ int misc_init_r(void)
printf("Recognized Alto35 expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
MUX_ALTO35();
setenv("defaultdisplay", "lcd35");
setenv("expansionname", "alto35");
@ -341,21 +338,25 @@ int misc_init_r(void)
printf("Recognized Stagecoach expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
break;
case GUMSTIX_THUMBO:
printf("Recognized Thumbo expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
break;
case GUMSTIX_TURTLECORE:
printf("Recognized Turtlecore expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
break;
case GUMSTIX_ARBOR43C:
printf("Recognized Arbor43C expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
MUX_ARBOR43C();
setenv("defaultdisplay", "lcd43");
break;
@ -363,16 +364,17 @@ int misc_init_r(void)
printf("Recognized Ettus Research USRP-E (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
MUX_USRP_E();
setenv("defaultdisplay", "dvi");
break;
case GUMSTIX_NO_EEPROM:
puts("No EEPROM on expansion board\n");
case GUMSTIX_EMPTY_EEPROM:
puts("No or empty EEPROM on expansion board\n");
MUX_GUMSTIX();
setenv("expansionname", "tobi");
break;
default:
if (expansion_id == 0x0)
setenv("expansionname", "tobi");
printf("Unrecognized expansion board 0x%08x\n", expansion_id);
break;
}
@ -401,7 +403,18 @@ void set_muxconf_regs(void)
MUX_OVERO();
}
#if defined(CONFIG_CMD_NET)
#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SPL_BUILD)
/* GPMC definitions for LAN9221 chips on Tobi expansion boards */
static const u32 gpmc_lan_config[] = {
NET_LAN9221_GPMC_CONFIG1,
NET_LAN9221_GPMC_CONFIG2,
NET_LAN9221_GPMC_CONFIG3,
NET_LAN9221_GPMC_CONFIG4,
NET_LAN9221_GPMC_CONFIG5,
NET_LAN9221_GPMC_CONFIG6,
/*CONFIG7- computed as params */
};
/*
* Routine: setup_net_chip
* Description: Setting up the configuration GPMC registers specific to the
@ -411,10 +424,6 @@ static void setup_net_chip(void)
{
struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
/* first lan chip */
enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
GPMC_SIZE_16M);
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
@ -422,7 +431,14 @@ static void setup_net_chip(void)
/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
&ctrl_base->gpmc_nadv_ale);
}
/*
* Routine: reset_net_chip
* Description: Reset the Ethernet hardware.
*/
static void reset_net_chip(void)
{
/* Make GPIO 64 as output pin and send a magic pulse through it */
if (!gpio_request(64, "")) {
gpio_direction_output(64, 0);
@ -433,16 +449,42 @@ static void setup_net_chip(void)
gpio_set_value(64, 1);
}
}
#endif
int board_eth_init(bd_t *bis)
{
unsigned int expansion_id;
int rc = 0;
#ifdef CONFIG_SMC911X
expansion_id = get_expansion_id();
switch (expansion_id) {
case GUMSTIX_TOBI_DUO:
/* second lan chip */
enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4],
0x2B000000, GPMC_SIZE_16M);
/* no break */
case GUMSTIX_TOBI:
case GUMSTIX_CHESTNUT43:
case GUMSTIX_STAGECOACH:
case GUMSTIX_NO_EEPROM:
case GUMSTIX_EMPTY_EEPROM:
/* first lan chip */
enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
0x2C000000, GPMC_SIZE_16M);
setup_net_chip();
reset_net_chip();
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
break;
default:
break;
}
#endif
return rc;
}
#endif
#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
@ -450,3 +492,32 @@ int board_mmc_init(bd_t *bis)
return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD)
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
};
#define GUMSTIX_GPIO_USBH_CPEN 168
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
/* Enable USB power */
if (!gpio_request(GUMSTIX_GPIO_USBH_CPEN, "usbh_cpen"))
gpio_direction_output(GUMSTIX_GPIO_USBH_CPEN, 1);
return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
}
int ehci_hcd_stop(void)
{
/* Disable USB power */
gpio_set_value(GUMSTIX_GPIO_USBH_CPEN, 0);
gpio_free(GUMSTIX_GPIO_USBH_CPEN);
return omap_ehci_hcd_stop();
}
#endif /* CONFIG_USB_EHCI */

150
board/overo/overo.h
View file

@ -101,13 +101,9 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO_54*/\
/* - MMC1_WP*/\
MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/\
MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nCS3*/\
MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M0)) /*GPMC_CLK*/\
@ -117,45 +113,11 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
/* - SMSC911X_NRES*/\
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | DIS | M4)) /*GPIO_65*/\
/*DSS*/\
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
/*CAMERA*/\
MUX_VAL(CP(CAM_HS), (IEN | PTU | DIS | M0)) /*CAM_HS */\
MUX_VAL(CP(CAM_VS), (IEN | PTU | DIS | M0)) /*CAM_VS */\
MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
MUX_VAL(CP(CAM_PCLK), (IEN | PTU | DIS | M0)) /*CAM_PCLK*/\
MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*CAM_FLD*/\
MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
@ -168,13 +130,8 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M0)) /*CAM_WEN*/\
MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) /*GPIO_112*/\
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) /*GPIO_113*/\
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\
/* - PEN_DOWN*/\
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) /*GPIO_115*/\
/*Audio Interface */\
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
@ -208,14 +165,7 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144 - LCD_EN*/\
MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\
MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
MUX_VAL(CP(UART1_RTS), (IEN | PTU | DIS | M4)) /*GPIO_149*/ \
MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M0)) /*McBSP4_CLKX*/\
MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M0)) /*McBSP4_DR*/\
MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M0)) /*McBSP4_DX*/\
@ -228,7 +178,6 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) /*McBSP1_FSX*/\
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) /*McBSP1_CLKX*/\
/*Serial Interface*/\
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
MUX_VAL(CP(UART3_RTS_SD), (IEN | PTU | EN | M4)) /*GPIO_164 W2W_*/\
/* BT_NRESET*/\
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTU | EN | M0)) /*UART3_RX_IRRX*/\
@ -255,14 +204,6 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*HDQ_SIO*/\
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176 */\
/* - LAN_INTR */\
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA2*/\
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA7*/\
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA4*/\
@ -281,21 +222,9 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10*/\
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M2)) /*MMC3_CLK*/\
MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M4)) /*GPIO_14*/\
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M4)) /*GPIO_15 - X_GATE*/\
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M4)) /*GPIO_16*/\
/* - W2W_NRESET*/\
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M4)) /*GPIO_21*/\
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M4)) /*GPIO_22*/\
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | EN | M4)) /*GPIO_23*/\
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DIR*/\
@ -369,6 +298,85 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
#define MUX_GUMSTIX() \
/*GPMC*/\
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) /*GPIO_63*/\
/* - CAM_IRQ*/\
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
/* - SMSC911X_NRES*/\
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | DIS | M4)) /*GPIO_65*/\
/*DSS*/\
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
/*CAMERA*/\
MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*CAM_FLD*/\
MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M0)) /*CAM_WEN*/\
MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\
/* - PEN_DOWN*/\
/*Bluetooth*/\
MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144 - LCD_EN*/\
MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\
MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
/*Serial Interface*/\
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*HDQ_SIO*/\
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176 */\
/* - LAN_INTR */\
/*Control and debug */\
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10*/\
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M2)) /*MMC3_CLK*/\
MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M4)) /*GPIO_14*/\
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M4)) /*GPIO_21*/\
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M4)) /*GPIO_22*/\
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | EN | M4)) /*GPIO_23*/\
#define MUX_OVERO_SDIO2_DIRECT() \
MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\

2
board/pandora/pandora.h
View file

@ -310,7 +310,7 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8*/\
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
/*JTAG*/\
MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /*JTAG_NTRST*/\
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\

2
board/technexion/tao3530/tao3530.h
View file

@ -275,7 +275,7 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \

2
board/technexion/twister/twister.h
View file

@ -337,7 +337,7 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
/* JTAG */\
MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \

2
board/teejet/mt_ventoux/mt_ventoux.h
View file

@ -339,7 +339,7 @@ const omap3_sysinfo sysinfo = {
/* gpio_10 */\
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) \
/* JTAG */\
MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) \

4
board/ti/am335x/mux.c
View file

@ -359,9 +359,9 @@ void enable_board_pin_mux(struct am335x_baseboard_id *header)
configure_module_pin_mux(i2c1_pin_mux);
configure_module_pin_mux(mii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
#if defined(CONFIG_NAND)
#if defined(CONFIG_NAND) && defined(CONFIG_EMMC_BOOT)
configure_module_pin_mux(nand_pin_mux);
#elif defined(CONFIG_NOR)
#elif defined(CONFIG_NOR) && defined(CONFIG_EMMC_BOOT)
configure_module_pin_mux(bone_norcape_pin_mux);
#else
configure_module_pin_mux(mmc1_pin_mux);

2
board/ti/am3517crane/am3517crane.h
View file

@ -284,7 +284,7 @@ const omap3_sysinfo sysinfo = {
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))/*GPIO_10 TP*/\
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0))\
/*JTAG*/\
MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\

2
board/ti/evm/evm.h
View file

@ -300,7 +300,7 @@ static void reset_net_chip(void);
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M0)) /*SYS_CLKOUT2*/\
MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)) /*JTAG_NTRST*/\
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\

16
board/ti/ks2_evm/Kconfig
View file

@ -23,3 +23,19 @@ config SYS_CONFIG_NAME
default "k2hk_evm"
endif
if TARGET_K2L_EVM
config SYS_BOARD
string
default "ks2_evm"
config SYS_VENDOR
string
default "ti"
config SYS_CONFIG_NAME
string
default "k2l_evm"
endif

2
board/ti/ks2_evm/MAINTAINERS
View file

@ -6,3 +6,5 @@ F: include/configs/k2hk_evm.h
F: configs/k2hk_evm_defconfig
F: include/configs/k2e_evm.h
F: configs/k2e_evm_defconfig
F: include/configs/k2l_evm.h
F: configs/k2l_evm_defconfig

2
board/ti/ks2_evm/Makefile
View file

@ -11,3 +11,5 @@ obj-$(CONFIG_K2HK_EVM) += board_k2hk.o
obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o
obj-$(CONFIG_K2E_EVM) += board_k2e.o
obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o
obj-$(CONFIG_K2L_EVM) += board_k2l.o
obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o

34
board/ti/ks2_evm/board.c
View file

@ -9,11 +9,13 @@
#include "board.h"
#include <common.h>
#include <spl.h>
#include <exports.h>
#include <fdt_support.h>
#include <asm/arch/ddr3.h>
#include <asm/arch/emac_defs.h>
#include <asm/arch/psc_defs.h>
#include <asm/ti-common/ti-aemif.h>
#include <asm/ti-common/keystone_net.h>
DECLARE_GLOBAL_DATA_PTR;
@ -38,6 +40,7 @@ int dram_init(void)
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE);
return 0;
}
@ -68,6 +71,15 @@ int board_eth_init(bd_t *bis)
int port_num;
char link_type_name[32];
/* By default, select PA PLL clock as PA clock source */
if (psc_enable_module(KS2_LPSC_PA))
return -1;
if (psc_enable_module(KS2_LPSC_CPGMAC))
return -1;
if (psc_enable_module(KS2_LPSC_CRYPTO))
return -1;
pass_pll_pa_clk_enable();
port_num = get_num_eth_ports();
for (j = 0; j < port_num; j++) {
@ -83,6 +95,24 @@ int board_eth_init(bd_t *bis)
}
#endif
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
spl_init_keystone_plls();
preloader_console_init();
}
u32 spl_boot_device(void)
{
#if defined(CONFIG_SPL_SPI_LOAD)
return BOOT_DEVICE_SPI;
#else
puts("Unknown boot device\n");
hang();
#endif
}
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
@ -225,5 +255,7 @@ void ft_board_setup_ex(void *blob, bd_t *bd)
reserve_start += 2;
}
}
ddr3_check_ecc_int(KS2_DDR3A_EMIF_CTRL_BASE);
}
#endif

3
board/ti/ks2_evm/board.h
View file

@ -10,10 +10,11 @@
#ifndef _KS2_BOARD
#define _KS2_BOARD
#include <asm/arch/emac_defs.h>
#include <asm/ti-common/keystone_net.h>
extern struct eth_priv_t eth_priv_cfg[];
int get_num_eth_ports(void);
void spl_init_keystone_plls(void);
#endif

79
board/ti/ks2_evm/board_k2e.c
View file

@ -10,6 +10,7 @@
#include <common.h>
#include <asm/arch/ddr3.h>
#include <asm/arch/hardware.h>
#include <asm/ti-common/keystone_net.h>
DECLARE_GLOBAL_DATA_PTR;
@ -35,10 +36,75 @@ static struct pll_init_data core_pll_config[] = {
CORE_PLL_1500,
};
static struct pll_init_data pa_pll_config =
PASS_PLL_1000;
#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
struct eth_priv_t eth_priv_cfg[] = {
{
.int_name = "K2E_EMAC0",
.rx_flow = 0,
.phy_addr = 0,
.slave_port = 1,
.sgmii_link_type = SGMII_LINK_MAC_PHY,
},
{
.int_name = "K2E_EMAC1",
.rx_flow = 8,
.phy_addr = 1,
.slave_port = 2,
.sgmii_link_type = SGMII_LINK_MAC_PHY,
},
{
.int_name = "K2E_EMAC2",
.rx_flow = 16,
.phy_addr = 2,
.slave_port = 3,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
},
{
.int_name = "K2E_EMAC3",
.rx_flow = 24,
.phy_addr = 3,
.slave_port = 4,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
},
{
.int_name = "K2E_EMAC4",
.rx_flow = 32,
.phy_addr = 4,
.slave_port = 5,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
},
{
.int_name = "K2E_EMAC5",
.rx_flow = 40,
.phy_addr = 5,
.slave_port = 6,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
},
{
.int_name = "K2E_EMAC6",
.rx_flow = 48,
.phy_addr = 6,
.slave_port = 7,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
},
{
.int_name = "K2E_EMAC7",
.rx_flow = 56,
.phy_addr = 7,
.slave_port = 8,
.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
},
};
int get_num_eth_ports(void)
{
return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
}
#endif
#if defined(CONFIG_BOARD_EARLY_INIT_F)
int board_early_init_f(void)
{
@ -52,3 +118,14 @@ int board_early_init_f(void)
return 0;
}
#endif
#ifdef CONFIG_SPL_BUILD
static struct pll_init_data spl_pll_config[] = {
CORE_PLL_800,
};
void spl_init_keystone_plls(void)
{
init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
}
#endif

14
board/ti/ks2_evm/board_k2hk.c
View file

@ -10,7 +10,7 @@
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
#include <asm/arch/emac_defs.h>
#include <asm/ti-common/keystone_net.h>
DECLARE_GLOBAL_DATA_PTR;
@ -100,3 +100,15 @@ int board_early_init_f(void)
return 0;
}
#endif
#ifdef CONFIG_SPL_BUILD
static struct pll_init_data spl_pll_config[] = {
CORE_PLL_799,
TETRIS_PLL_500,
};
void spl_init_keystone_plls(void)
{
init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
}
#endif

72
board/ti/ks2_evm/board_k2l.c Normal file
View file

@ -0,0 +1,72 @@
/*
* K2L EVM : Board initialization
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/ddr3.h>
#include <asm/arch/hardware.h>
#include <asm/ti-common/ti-aemif.h>
DECLARE_GLOBAL_DATA_PTR;
unsigned int external_clk[ext_clk_count] = {
[sys_clk] = 122880000,
[alt_core_clk] = 100000000,
[pa_clk] = 122880000,
[tetris_clk] = 122880000,
[ddr3_clk] = 100000000,
[pcie_clk] = 100000000,
[sgmii_clk] = 156250000,
[usb_clk] = 100000000,
};
static struct pll_init_data core_pll_config[] = {
CORE_PLL_799,
CORE_PLL_1000,
CORE_PLL_1198,
};
static struct pll_init_data tetris_pll_config[] = {
TETRIS_PLL_799,
TETRIS_PLL_1000,
TETRIS_PLL_1198,
TETRIS_PLL_1352,
TETRIS_PLL_1401,
};
static struct pll_init_data pa_pll_config =
PASS_PLL_983;
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
int speed;
speed = get_max_dev_speed();
init_pll(&core_pll_config[speed]);
init_pll(&pa_pll_config);
speed = get_max_arm_speed();
init_pll(&tetris_pll_config[speed]);
return 0;
}
#endif
#ifdef CONFIG_SPL_BUILD
static struct pll_init_data spl_pll_config[] = {
CORE_PLL_799,
TETRIS_PLL_491,
};
void spl_init_keystone_plls(void)
{
init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
}
#endif

36
board/ti/ks2_evm/ddr3_cfg.c
View file

@ -133,6 +133,42 @@ struct ddr3_emif_config ddr3_1600_4g = {
};
#endif
struct ddr3_phy_config ddr3phy_1600_2g = {
.pllcr = 0x0001C000ul,
.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
.ptr0 = 0x42C21590ul,
.ptr1 = 0xD05612C0ul,
.ptr2 = 0, /* not set in gel */
.ptr3 = 0x0D861A80ul,
.ptr4 = 0x0C827100ul,
.dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
.dcr_val = ((1 << 10)),
.dtpr0 = 0x9D5CBB66ul,
.dtpr1 = 0x12868300ul,
.dtpr2 = 0x5002D200ul,
.mr0 = 0x00001C70ul,
.mr1 = 0x00000006ul,
.mr2 = 0x00000018ul,
.dtcr = 0x710035C7ul,
.pgcr2 = 0x00F07A12ul,
.zq0cr1 = 0x0001005Dul,
.zq1cr1 = 0x0001005Bul,
.zq2cr1 = 0x0001005Bul,
.pir_v1 = 0x00000033ul,
.pir_v2 = 0x0000FF81ul,
};
struct ddr3_emif_config ddr3_1600_2g = {
.sdcfg = 0x6200CE62ul,
.sdtim1 = 0x166C9855ul,
.sdtim2 = 0x00001D4Aul,
.sdtim3 = 0x435DFF53ul,
.sdtim4 = 0x543F0CFFul,
.zqcfg = 0x70073200ul,
.sdrfc = 0x00001869ul,
};
int ddr3_get_dimm_params(char *dimm_name)
{
int ret;

3
board/ti/ks2_evm/ddr3_cfg.h
View file

@ -19,6 +19,9 @@ extern struct ddr3_emif_config ddr3_1333_2g;
extern struct ddr3_phy_config ddr3phy_1600_4g;
extern struct ddr3_emif_config ddr3_1600_4g;
extern struct ddr3_phy_config ddr3phy_1600_2g;
extern struct ddr3_emif_config ddr3_1600_2g;
int ddr3_get_dimm_params(char *dimm_name);
#endif /* __DDR3_CFG_H */

16
board/ti/ks2_evm/ddr3_k2hk.c
View file

@ -12,6 +12,8 @@
#include <asm/arch/ddr3.h>
#include <asm/arch/hardware.h>
static int ddr3_size;
struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
@ -44,12 +46,14 @@ void ddr3_init(void)
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
&ddr3_1600_8g);
printf("DRAM: Capacity 8 GiB (includes reported below)\n");
ddr3_size = 8;
} else {
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
ddr3_1600_8g.sdcfg |= 0x1000;
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
&ddr3_1600_8g);
printf("DRAM: Capacity 4 GiB (includes reported below)\n");
ddr3_size = 4;
}
} else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
init_pll(&ddr3a_333);
@ -70,11 +74,15 @@ void ddr3_init(void)
}
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
&ddr3_1333_2g);
ddr3_size = 2;
printf("DRAM: 2 GiB");
} else {
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g);
ddr3_1333_2g.sdcfg |= 0x1000;
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
&ddr3_1333_2g);
ddr3_size = 1;
printf("DRAM: 1 GiB");
}
} else {
printf("Unknown SO-DIMM. Cannot configure DDR3\n");
@ -86,3 +94,11 @@ void ddr3_init(void)
if (cpu_revision() <= 1)
ddr3_err_reset_workaround();
}
/**
* ddr3_get_size - return ddr3 size in GiB
*/
int ddr3_get_size(void)
{
return ddr3_size;
}

38
board/ti/ks2_evm/ddr3_k2l.c Normal file
View file

@ -0,0 +1,38 @@
/*
* Keystone2: DDR3 initialization
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include "ddr3_cfg.h"
#include <asm/arch/ddr3.h>
static int ddr3_size;
static struct pll_init_data ddr3_400 = DDR3_PLL_400;
void ddr3_init(void)
{
init_pll(&ddr3_400);
/* No SO-DIMM, 2GB discreet DDR */
printf("DRAM: 2 GiB\n");
ddr3_size = 2;
/* Reset DDR3 PHY after PLL enabled */
ddr3_reset_ddrphy();
ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g);
ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_2g);
}
/**
* ddr3_get_size - return ddr3 size in GiB
*/
int ddr3_get_size(void)
{
return ddr3_size;
}

2
board/ti/sdp3430/sdp.h
View file

@ -265,7 +265,7 @@
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(SYS_CLKOUT2), (OFF_IN_PD | IEN | PTU | EN | M4))/*GPIO_186*/\
MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\

1
common/Makefile
View file

@ -233,6 +233,7 @@ obj-$(CONFIG_SPL_ENV_SUPPORT) += env_flags.o
obj-$(CONFIG_SPL_ENV_SUPPORT) += env_callback.o
obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
obj-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o
obj-$(CONFIG_ENV_IS_IN_FAT) += env_fat.o
obj-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
obj-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
obj-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o

4
configs/k2l_evm_defconfig Normal file
View file

@ -0,0 +1,4 @@
CONFIG_SPL=y
+S:CONFIG_ARM=y
+S:CONFIG_ARCH_KEYSTONE=y
+S:CONFIG_TARGET_K2L_EVM=y

2
drivers/Makefile
View file

@ -19,3 +19,5 @@ obj-$(CONFIG_QE) += qe/
obj-y += memory/
obj-y += pwm/
obj-y += input/
# SOC specific infrastructure drivers.
obj-y += soc/

2
drivers/dma/Makefile
View file

@ -8,3 +8,5 @@
obj-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
obj-$(CONFIG_APBH_DMA) += apbh_dma.o
obj-$(CONFIG_FSL_DMA) += fsl_dma.o
obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o
obj-$(CONFIG_TI_EDMA3) += ti-edma3.o

192
arch/arm/cpu/armv7/keystone/keystone_nav.c → drivers/dma/keystone_nav.c
View file

@ -8,28 +8,23 @@
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/keystone_nav.h>
#include <asm/ti-common/keystone_nav.h>
static int soc_type =
#ifdef CONFIG_SOC_K2HK
k2hk;
#endif
struct qm_config k2hk_qm_memmap = {
.stat_cfg = 0x02a40000,
.queue = (struct qm_reg_queue *)0x02a80000,
.mngr_vbusm = 0x23a80000,
.i_lram = 0x00100000,
.proxy = (struct qm_reg_queue *)0x02ac0000,
.status_ram = 0x02a06000,
.mngr_cfg = (struct qm_cfg_reg *)0x02a02000,
.intd_cfg = 0x02a0c000,
.desc_mem = (struct descr_mem_setup_reg *)0x02a03000,
.region_num = 64,
.pdsp_cmd = 0x02a20000,
.pdsp_ctl = 0x02a0f000,
.pdsp_iram = 0x02a10000,
.qpool_num = 4000,
struct qm_config qm_memmap = {
.stat_cfg = CONFIG_KSNAV_QM_QUEUE_STATUS_BASE,
.queue = (void *)CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE,
.mngr_vbusm = CONFIG_KSNAV_QM_BASE_ADDRESS,
.i_lram = CONFIG_KSNAV_QM_LINK_RAM_BASE,
.proxy = (void *)CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE,
.status_ram = CONFIG_KSNAV_QM_STATUS_RAM_BASE,
.mngr_cfg = (void *)CONFIG_KSNAV_QM_CONF_BASE,
.intd_cfg = CONFIG_KSNAV_QM_INTD_CONF_BASE,
.desc_mem = (void *)CONFIG_KSNAV_QM_DESC_SETUP_BASE,
.region_num = CONFIG_KSNAV_QM_REGION_NUM,
.pdsp_cmd = CONFIG_KSNAV_QM_PDSP1_CMD_BASE,
.pdsp_ctl = CONFIG_KSNAV_QM_PDSP1_CTRL_BASE,
.pdsp_iram = CONFIG_KSNAV_QM_PDSP1_IRAM_BASE,
.qpool_num = CONFIG_KSNAV_QM_QPOOL_NUM,
};
/*
@ -52,13 +47,10 @@ inline int num_of_desc_to_reg(int num_descr)
return 15;
}
static int _qm_init(struct qm_config *cfg)
int _qm_init(struct qm_config *cfg)
{
u32 j;
if (cfg == NULL)
return QM_ERR;
qm_cfg = cfg;
qm_cfg->mngr_cfg->link_ram_base0 = qm_cfg->i_lram;
@ -82,12 +74,7 @@ static int _qm_init(struct qm_config *cfg)
int qm_init(void)
{
switch (soc_type) {
case k2hk:
return _qm_init(&k2hk_qm_memmap);
}
return QM_ERR;
return _qm_init(&qm_memmap);
}
void qm_close(void)
@ -166,39 +153,23 @@ void queue_close(u32 qnum)
;
}
/*
/**
* DMA API
*/
struct pktdma_cfg k2hk_netcp_pktdma = {
.global = (struct global_ctl_regs *)0x02004000,
.tx_ch = (struct tx_chan_regs *)0x02004400,
.tx_ch_num = 9,
.rx_ch = (struct rx_chan_regs *)0x02004800,
.rx_ch_num = 26,
.tx_sched = (u32 *)0x02004c00,
.rx_flows = (struct rx_flow_regs *)0x02005000,
.rx_flow_num = 32,
.rx_free_q = 4001,
.rx_rcv_q = 4002,
.tx_snd_q = 648,
};
struct pktdma_cfg *netcp;
static int netcp_rx_disable(void)
static int ksnav_rx_disable(struct pktdma_cfg *pktdma)
{
u32 j, v, k;
for (j = 0; j < netcp->rx_ch_num; j++) {
v = readl(&netcp->rx_ch[j].cfg_a);
for (j = 0; j < pktdma->rx_ch_num; j++) {
v = readl(&pktdma->rx_ch[j].cfg_a);
if (!(v & CPDMA_CHAN_A_ENABLE))
continue;
writel(v | CPDMA_CHAN_A_TDOWN, &netcp->rx_ch[j].cfg_a);
writel(v | CPDMA_CHAN_A_TDOWN, &pktdma->rx_ch[j].cfg_a);
for (k = 0; k < TDOWN_TIMEOUT_COUNT; k++) {
udelay(100);
v = readl(&netcp->rx_ch[j].cfg_a);
v = readl(&pktdma->rx_ch[j].cfg_a);
if (!(v & CPDMA_CHAN_A_ENABLE))
continue;
}
@ -206,33 +177,33 @@ static int netcp_rx_disable(void)
}
/* Clear all of the flow registers */
for (j = 0; j < netcp->rx_flow_num; j++) {
writel(0, &netcp->rx_flows[j].control);
writel(0, &netcp->rx_flows[j].tags);
writel(0, &netcp->rx_flows[j].tag_sel);
writel(0, &netcp->rx_flows[j].fdq_sel[0]);
writel(0, &netcp->rx_flows[j].fdq_sel[1]);
writel(0, &netcp->rx_flows[j].thresh[0]);
writel(0, &netcp->rx_flows[j].thresh[1]);
writel(0, &netcp->rx_flows[j].thresh[2]);
for (j = 0; j < pktdma->rx_flow_num; j++) {
writel(0, &pktdma->rx_flows[j].control);
writel(0, &pktdma->rx_flows[j].tags);
writel(0, &pktdma->rx_flows[j].tag_sel);
writel(0, &pktdma->rx_flows[j].fdq_sel[0]);
writel(0, &pktdma->rx_flows[j].fdq_sel[1]);
writel(0, &pktdma->rx_flows[j].thresh[0]);
writel(0, &pktdma->rx_flows[j].thresh[1]);
writel(0, &pktdma->rx_flows[j].thresh[2]);
}
return QM_OK;
}
static int netcp_tx_disable(void)
static int ksnav_tx_disable(struct pktdma_cfg *pktdma)
{
u32 j, v, k;
for (j = 0; j < netcp->tx_ch_num; j++) {
v = readl(&netcp->tx_ch[j].cfg_a);
for (j = 0; j < pktdma->tx_ch_num; j++) {
v = readl(&pktdma->tx_ch[j].cfg_a);
if (!(v & CPDMA_CHAN_A_ENABLE))
continue;
writel(v | CPDMA_CHAN_A_TDOWN, &netcp->tx_ch[j].cfg_a);
writel(v | CPDMA_CHAN_A_TDOWN, &pktdma->tx_ch[j].cfg_a);
for (k = 0; k < TDOWN_TIMEOUT_COUNT; k++) {
udelay(100);
v = readl(&netcp->tx_ch[j].cfg_a);
v = readl(&pktdma->tx_ch[j].cfg_a);
if (!(v & CPDMA_CHAN_A_ENABLE))
continue;
}
@ -242,19 +213,17 @@ static int netcp_tx_disable(void)
return QM_OK;
}
static int _netcp_init(struct pktdma_cfg *netcp_cfg,
struct rx_buff_desc *rx_buffers)
int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc *rx_buffers)
{
u32 j, v;
struct qm_host_desc *hd;
u8 *rx_ptr;
if (netcp_cfg == NULL || rx_buffers == NULL ||
if (pktdma == NULL || rx_buffers == NULL ||
rx_buffers->buff_ptr == NULL || qm_cfg == NULL)
return QM_ERR;
netcp = netcp_cfg;
netcp->rx_flow = rx_buffers->rx_flow;
pktdma->rx_flow = rx_buffers->rx_flow;
/* init rx queue */
rx_ptr = rx_buffers->buff_ptr;
@ -264,77 +233,64 @@ static int _netcp_init(struct pktdma_cfg *netcp_cfg,
if (hd == NULL)
return QM_ERR;
qm_buff_push(hd, netcp->rx_free_q,
qm_buff_push(hd, pktdma->rx_free_q,
rx_ptr, rx_buffers->buff_len);
rx_ptr += rx_buffers->buff_len;
}
netcp_rx_disable();
ksnav_rx_disable(pktdma);
/* configure rx channels */
v = CPDMA_REG_VAL_MAKE_RX_FLOW_A(1, 1, 0, 0, 0, 0, 0, netcp->rx_rcv_q);
writel(v, &netcp->rx_flows[netcp->rx_flow].control);
writel(0, &netcp->rx_flows[netcp->rx_flow].tags);
writel(0, &netcp->rx_flows[netcp->rx_flow].tag_sel);
v = CPDMA_REG_VAL_MAKE_RX_FLOW_A(1, 1, 0, 0, 0, 0, 0, pktdma->rx_rcv_q);
writel(v, &pktdma->rx_flows[pktdma->rx_flow].control);
writel(0, &pktdma->rx_flows[pktdma->rx_flow].tags);
writel(0, &pktdma->rx_flows[pktdma->rx_flow].tag_sel);
v = CPDMA_REG_VAL_MAKE_RX_FLOW_D(0, netcp->rx_free_q, 0,
netcp->rx_free_q);
v = CPDMA_REG_VAL_MAKE_RX_FLOW_D(0, pktdma->rx_free_q, 0,
pktdma->rx_free_q);
writel(v, &netcp->rx_flows[netcp->rx_flow].fdq_sel[0]);
writel(v, &netcp->rx_flows[netcp->rx_flow].fdq_sel[1]);
writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[0]);
writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[1]);
writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[2]);
writel(v, &pktdma->rx_flows[pktdma->rx_flow].fdq_sel[0]);
writel(v, &pktdma->rx_flows[pktdma->rx_flow].fdq_sel[1]);
writel(0, &pktdma->rx_flows[pktdma->rx_flow].thresh[0]);
writel(0, &pktdma->rx_flows[pktdma->rx_flow].thresh[1]);
writel(0, &pktdma->rx_flows[pktdma->rx_flow].thresh[2]);
for (j = 0; j < netcp->rx_ch_num; j++)
writel(CPDMA_CHAN_A_ENABLE, &netcp->rx_ch[j].cfg_a);
for (j = 0; j < pktdma->rx_ch_num; j++)
writel(CPDMA_CHAN_A_ENABLE, &pktdma->rx_ch[j].cfg_a);
/* configure tx channels */
/* Disable loopback in the tx direction */
writel(0, &netcp->global->emulation_control);
writel(0, &pktdma->global->emulation_control);
/* TODO: make it dependend on a soc type variable */
#ifdef CONFIG_SOC_K2HK
/* Set QM base address, only for K2x devices */
writel(0x23a80000, &netcp->global->qm_base_addr[0]);
#endif
writel(CONFIG_KSNAV_QM_BASE_ADDRESS, &pktdma->global->qm_base_addr[0]);
/* Enable all channels. The current state isn't important */
for (j = 0; j < netcp->tx_ch_num; j++) {
writel(0, &netcp->tx_ch[j].cfg_b);
writel(CPDMA_CHAN_A_ENABLE, &netcp->tx_ch[j].cfg_a);
for (j = 0; j < pktdma->tx_ch_num; j++) {
writel(0, &pktdma->tx_ch[j].cfg_b);
writel(CPDMA_CHAN_A_ENABLE, &pktdma->tx_ch[j].cfg_a);
}
return QM_OK;
}
int netcp_init(struct rx_buff_desc *rx_buffers)
int ksnav_close(struct pktdma_cfg *pktdma)
{
switch (soc_type) {
case k2hk:
_netcp_init(&k2hk_netcp_pktdma, rx_buffers);
return QM_OK;
}
return QM_ERR;
}
int netcp_close(void)
{
if (!netcp)
if (!pktdma)
return QM_ERR;
netcp_tx_disable();
netcp_rx_disable();
ksnav_tx_disable(pktdma);
ksnav_rx_disable(pktdma);
queue_close(netcp->rx_free_q);
queue_close(netcp->rx_rcv_q);
queue_close(netcp->tx_snd_q);
queue_close(pktdma->rx_free_q);
queue_close(pktdma->rx_rcv_q);
queue_close(pktdma->tx_snd_q);
return QM_OK;
}
int netcp_send(u32 *pkt, int num_bytes, u32 swinfo2)
int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes, u32 swinfo2)
{
struct qm_host_desc *hd;
@ -346,16 +302,16 @@ int netcp_send(u32 *pkt, int num_bytes, u32 swinfo2)
hd->swinfo[2] = swinfo2;
hd->packet_info = qm_cfg->qpool_num;
qm_buff_push(hd, netcp->tx_snd_q, pkt, num_bytes);
qm_buff_push(hd, pktdma->tx_snd_q, pkt, num_bytes);
return QM_OK;
}
void *netcp_recv(u32 **pkt, int *num_bytes)
void *ksnav_recv(struct pktdma_cfg *pktdma, u32 **pkt, int *num_bytes)
{
struct qm_host_desc *hd;
hd = qm_pop(netcp->rx_rcv_q);
hd = qm_pop(pktdma->rx_rcv_q);
if (!hd)
return NULL;
@ -365,12 +321,12 @@ void *netcp_recv(u32 **pkt, int *num_bytes)
return hd;
}
void netcp_release_rxhd(void *hd)
void ksnav_release_rxhd(struct pktdma_cfg *pktdma, void *hd)
{
struct qm_host_desc *_hd = (struct qm_host_desc *)hd;
_hd->buff_len = _hd->orig_buff_len;
_hd->buff_ptr = _hd->orig_buff_ptr;
qm_push(_hd, netcp->rx_free_q);
qm_push(_hd, pktdma->rx_free_q);
}

27
drivers/dma/keystone_nav_cfg.c Normal file
View file

@ -0,0 +1,27 @@
/*
* Multicore Navigator driver for TI Keystone 2 devices.
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/ti-common/keystone_nav.h>
#ifdef CONFIG_KSNAV_PKTDMA_NETCP
/* NETCP Pktdma */
struct pktdma_cfg netcp_pktdma = {
.global = (void *)CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE,
.tx_ch = (void *)CONFIG_KSNAV_NETCP_PDMA_TX_BASE,
.tx_ch_num = CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM,
.rx_ch = (void *)CONFIG_KSNAV_NETCP_PDMA_RX_BASE,
.rx_ch_num = CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM,
.tx_sched = (u32 *)CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE,
.rx_flows = (void *)CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE,
.rx_flow_num = CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM,
.rx_free_q = CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE,
.rx_rcv_q = CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE,
.tx_snd_q = CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE,
};
#endif

384
drivers/dma/ti-edma3.c Normal file
View file

@ -0,0 +1,384 @@
/*
* Enhanced Direct Memory Access (EDMA3) Controller
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* Author: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/io.h>
#include <common.h>
#include <asm/ti-common/ti-edma3.h>
#define EDMA3_SL_BASE(slot) (0x4000 + ((slot) << 5))
#define EDMA3_SL_MAX_NUM 512
#define EDMA3_SLOPT_FIFO_WIDTH_MASK (0x7 << 8)
#define EDMA3_QCHMAP(ch) 0x0200 + ((ch) << 2)
#define EDMA3_CHMAP_PARSET_MASK 0x1ff
#define EDMA3_CHMAP_PARSET_SHIFT 0x5
#define EDMA3_CHMAP_TRIGWORD_SHIFT 0x2
#define EDMA3_QEMCR 0x314
#define EDMA3_IPR 0x1068
#define EDMA3_IPRH 0x106c
#define EDMA3_ICR 0x1070
#define EDMA3_ICRH 0x1074
#define EDMA3_QEECR 0x1088
#define EDMA3_QEESR 0x108c
#define EDMA3_QSECR 0x1094
/**
* qedma3_start - start qdma on a channel
* @base: base address of edma
* @cfg: pinter to struct edma3_channel_config where you can set
* the slot number to associate with, the chnum, which corresponds
* your quick channel number 0-7, complete code - transfer complete code
* and trigger slot word - which has to correspond to the word number in
* edma3_slot_layout struct for generating event.
*
*/
void qedma3_start(u32 base, struct edma3_channel_config *cfg)
{
u32 qchmap;
/* Clear the pending int bit */
if (cfg->complete_code < 32)
__raw_writel(1 << cfg->complete_code, base + EDMA3_ICR);
else
__raw_writel(1 << cfg->complete_code, base + EDMA3_ICRH);
/* Map parameter set and trigger word 7 to quick channel */
qchmap = ((EDMA3_CHMAP_PARSET_MASK & cfg->slot)
<< EDMA3_CHMAP_PARSET_SHIFT) |
(cfg->trigger_slot_word << EDMA3_CHMAP_TRIGWORD_SHIFT);
__raw_writel(qchmap, base + EDMA3_QCHMAP(cfg->chnum));
/* Clear missed event if set*/
__raw_writel(1 << cfg->chnum, base + EDMA3_QSECR);
__raw_writel(1 << cfg->chnum, base + EDMA3_QEMCR);
/* Enable qdma channel event */
__raw_writel(1 << cfg->chnum, base + EDMA3_QEESR);
}
/**
* edma3_set_dest - set initial DMA destination address in parameter RAM slot
* @base: base address of edma
* @slot: parameter RAM slot being configured
* @dst: physical address of destination (memory, controller FIFO, etc)
* @addressMode: INCR, except in very rare cases
* @width: ignored unless @addressMode is FIFO, else specifies the
* width to use when addressing the fifo (e.g. W8BIT, W32BIT)
*
* Note that the destination address is modified during the DMA transfer
* according to edma3_set_dest_index().
*/
void edma3_set_dest(u32 base, int slot, u32 dst, enum edma3_address_mode mode,
enum edma3_fifo_width width)
{
u32 opt;
struct edma3_slot_layout *rg;
rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
opt = __raw_readl(&rg->opt);
if (mode == FIFO)
opt = (opt & EDMA3_SLOPT_FIFO_WIDTH_MASK) |
(EDMA3_SLOPT_DST_ADDR_CONST_MODE |
EDMA3_SLOPT_FIFO_WIDTH_SET(width));
else
opt &= ~EDMA3_SLOPT_DST_ADDR_CONST_MODE;
__raw_writel(opt, &rg->opt);
__raw_writel(dst, &rg->dst);
}
/**
* edma3_set_dest_index - configure DMA destination address indexing
* @base: base address of edma
* @slot: parameter RAM slot being configured
* @bidx: byte offset between destination arrays in a frame
* @cidx: byte offset between destination frames in a block
*
* Offsets are specified to support either contiguous or discontiguous
* memory transfers, or repeated access to a hardware register, as needed.
* When accessing hardware registers, both offsets are normally zero.
*/
void edma3_set_dest_index(u32 base, unsigned slot, int bidx, int cidx)
{
u32 src_dst_bidx;
u32 src_dst_cidx;
struct edma3_slot_layout *rg;
rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
src_dst_bidx = __raw_readl(&rg->src_dst_bidx);
src_dst_cidx = __raw_readl(&rg->src_dst_cidx);
__raw_writel((src_dst_bidx & 0x0000ffff) | (bidx << 16),
&rg->src_dst_bidx);
__raw_writel((src_dst_cidx & 0x0000ffff) | (cidx << 16),
&rg->src_dst_cidx);
}
/**
* edma3_set_dest_addr - set destination address for slot only
*/
void edma3_set_dest_addr(u32 base, int slot, u32 dst)
{
struct edma3_slot_layout *rg;
rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
__raw_writel(dst, &rg->dst);
}
/**
* edma3_set_src - set initial DMA source address in parameter RAM slot
* @base: base address of edma
* @slot: parameter RAM slot being configured
* @src_port: physical address of source (memory, controller FIFO, etc)
* @mode: INCR, except in very rare cases
* @width: ignored unless @addressMode is FIFO, else specifies the
* width to use when addressing the fifo (e.g. W8BIT, W32BIT)
*
* Note that the source address is modified during the DMA transfer
* according to edma3_set_src_index().
*/
void edma3_set_src(u32 base, int slot, u32 src, enum edma3_address_mode mode,
enum edma3_fifo_width width)
{
u32 opt;
struct edma3_slot_layout *rg;
rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
opt = __raw_readl(&rg->opt);
if (mode == FIFO)
opt = (opt & EDMA3_SLOPT_FIFO_WIDTH_MASK) |
(EDMA3_SLOPT_DST_ADDR_CONST_MODE |
EDMA3_SLOPT_FIFO_WIDTH_SET(width));
else
opt &= ~EDMA3_SLOPT_DST_ADDR_CONST_MODE;
__raw_writel(opt, &rg->opt);
__raw_writel(src, &rg->src);
}
/**
* edma3_set_src_index - configure DMA source address indexing
* @base: base address of edma
* @slot: parameter RAM slot being configured
* @bidx: byte offset between source arrays in a frame
* @cidx: byte offset between source frames in a block
*
* Offsets are specified to support either contiguous or discontiguous
* memory transfers, or repeated access to a hardware register, as needed.
* When accessing hardware registers, both offsets are normally zero.
*/
void edma3_set_src_index(u32 base, unsigned slot, int bidx, int cidx)
{
u32 src_dst_bidx;
u32 src_dst_cidx;
struct edma3_slot_layout *rg;
rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
src_dst_bidx = __raw_readl(&rg->src_dst_bidx);
src_dst_cidx = __raw_readl(&rg->src_dst_cidx);
__raw_writel((src_dst_bidx & 0xffff0000) | bidx,
&rg->src_dst_bidx);
__raw_writel((src_dst_cidx & 0xffff0000) | cidx,
&rg->src_dst_cidx);
}
/**
* edma3_set_src_addr - set source address for slot only
*/
void edma3_set_src_addr(u32 base, int slot, u32 src)
{
struct edma3_slot_layout *rg;
rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
__raw_writel(src, &rg->src);
}
/**
* edma3_set_transfer_params - configure DMA transfer parameters
* @base: base address of edma
* @slot: parameter RAM slot being configured
* @acnt: how many bytes per array (at least one)
* @bcnt: how many arrays per frame (at least one)
* @ccnt: how many frames per block (at least one)
* @bcnt_rld: used only for A-Synchronized transfers; this specifies
* the value to reload into bcnt when it decrements to zero
* @sync_mode: ASYNC or ABSYNC
*
* See the EDMA3 documentation to understand how to configure and link
* transfers using the fields in PaRAM slots. If you are not doing it
* all at once with edma3_write_slot(), you will use this routine
* plus two calls each for source and destination, setting the initial
* address and saying how to index that address.
*
* An example of an A-Synchronized transfer is a serial link using a
* single word shift register. In that case, @acnt would be equal to
* that word size; the serial controller issues a DMA synchronization
* event to transfer each word, and memory access by the DMA transfer
* controller will be word-at-a-time.
*
* An example of an AB-Synchronized transfer is a device using a FIFO.
* In that case, @acnt equals the FIFO width and @bcnt equals its depth.
* The controller with the FIFO issues DMA synchronization events when
* the FIFO threshold is reached, and the DMA transfer controller will
* transfer one frame to (or from) the FIFO. It will probably use
* efficient burst modes to access memory.
*/
void edma3_set_transfer_params(u32 base, int slot, int acnt,
int bcnt, int ccnt, u16 bcnt_rld,
enum edma3_sync_dimension sync_mode)
{
u32 opt;
u32 link_bcntrld;
struct edma3_slot_layout *rg;
rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
link_bcntrld = __raw_readl(&rg->link_bcntrld);
__raw_writel((bcnt_rld << 16) | (0x0000ffff & link_bcntrld),
&rg->link_bcntrld);
opt = __raw_readl(&rg->opt);
if (sync_mode == ASYNC)
__raw_writel(opt & ~EDMA3_SLOPT_AB_SYNC, &rg->opt);
else
__raw_writel(opt | EDMA3_SLOPT_AB_SYNC, &rg->opt);
/* Set the acount, bcount, ccount registers */
__raw_writel((bcnt << 16) | (acnt & 0xffff), &rg->a_b_cnt);
__raw_writel(0xffff & ccnt, &rg->ccnt);
}
/**
* edma3_write_slot - write parameter RAM data for slot
* @base: base address of edma
* @slot: number of parameter RAM slot being modified
* @param: data to be written into parameter RAM slot
*
* Use this to assign all parameters of a transfer at once. This
* allows more efficient setup of transfers than issuing multiple
* calls to set up those parameters in small pieces, and provides
* complete control over all transfer options.
*/
void edma3_write_slot(u32 base, int slot, struct edma3_slot_layout *param)
{
int i;
u32 *p = (u32 *)param;
u32 *addr = (u32 *)(base + EDMA3_SL_BASE(slot));
for (i = 0; i < sizeof(struct edma3_slot_layout)/4; i += 4)
__raw_writel(*p++, addr++);
}
/**
* edma3_read_slot - read parameter RAM data from slot
* @base: base address of edma
* @slot: number of parameter RAM slot being copied
* @param: where to store copy of parameter RAM data
*
* Use this to read data from a parameter RAM slot, perhaps to
* save them as a template for later reuse.
*/
void edma3_read_slot(u32 base, int slot, struct edma3_slot_layout *param)
{
int i;
u32 *p = (u32 *)param;
u32 *addr = (u32 *)(base + EDMA3_SL_BASE(slot));
for (i = 0; i < sizeof(struct edma3_slot_layout)/4; i += 4)
*p++ = __raw_readl(addr++);
}
void edma3_slot_configure(u32 base, int slot, struct edma3_slot_config *cfg)
{
struct edma3_slot_layout *rg;
rg = (struct edma3_slot_layout *)(base + EDMA3_SL_BASE(slot));
__raw_writel(cfg->opt, &rg->opt);
__raw_writel(cfg->src, &rg->src);
__raw_writel((cfg->bcnt << 16) | (cfg->acnt & 0xffff), &rg->a_b_cnt);
__raw_writel(cfg->dst, &rg->dst);
__raw_writel((cfg->dst_bidx << 16) |
(cfg->src_bidx & 0xffff), &rg->src_dst_bidx);
__raw_writel((cfg->bcntrld << 16) |
(cfg->link & 0xffff), &rg->link_bcntrld);
__raw_writel((cfg->dst_cidx << 16) |
(cfg->src_cidx & 0xffff), &rg->src_dst_cidx);
__raw_writel(0xffff & cfg->ccnt, &rg->ccnt);
}
/**
* edma3_check_for_transfer - check if transfer coplete by checking
* interrupt pending bit. Clear interrupt pending bit if complete.
* @base: base address of edma
* @cfg: pinter to struct edma3_channel_config which was passed
* to qedma3_start when you started qdma channel
*
* Return 0 if complete, 1 if not.
*/
int edma3_check_for_transfer(u32 base, struct edma3_channel_config *cfg)
{
u32 inum;
u32 ipr_base;
u32 icr_base;
if (cfg->complete_code < 32) {
ipr_base = base + EDMA3_IPR;
icr_base = base + EDMA3_ICR;
inum = 1 << cfg->complete_code;
} else {
ipr_base = base + EDMA3_IPRH;
icr_base = base + EDMA3_ICRH;
inum = 1 << (cfg->complete_code - 32);
}
/* check complete interrupt */
if (!(__raw_readl(ipr_base) & inum))
return 1;
/* clean up the pending int bit */
__raw_writel(inum, icr_base);
return 0;
}
/**
* qedma3_stop - stops dma on the channel passed
* @base: base address of edma
* @cfg: pinter to struct edma3_channel_config which was passed
* to qedma3_start when you started qdma channel
*/
void qedma3_stop(u32 base, struct edma3_channel_config *cfg)
{
/* Disable qdma channel event */
__raw_writel(1 << cfg->chnum, base + EDMA3_QEECR);
/* clean up the interrupt indication */
if (cfg->complete_code < 32)
__raw_writel(1 << cfg->complete_code, base + EDMA3_ICR);
else
__raw_writel(1 << cfg->complete_code, base + EDMA3_ICRH);
/* Clear missed event if set*/
__raw_writel(1 << cfg->chnum, base + EDMA3_QSECR);
__raw_writel(1 << cfg->chnum, base + EDMA3_QEMCR);
/* Clear the channel map */
__raw_writel(0, base + EDMA3_QCHMAP(cfg->chnum));
}

406
drivers/net/keystone_net.c
View file

@ -10,15 +10,16 @@
#include <command.h>
#include <net.h>
#include <phy.h>
#include <errno.h>
#include <miiphy.h>
#include <malloc.h>
#include <asm/arch/emac_defs.h>
#include <asm/arch/psc_defs.h>
#include <asm/arch/keystone_nav.h>
unsigned int emac_dbg;
#include <asm/ti-common/keystone_nav.h>
#include <asm/ti-common/keystone_net.h>
#include <asm/ti-common/keystone_serdes.h>
unsigned int emac_open;
static struct mii_dev *mdio_bus;
static unsigned int sys_has_mdio = 1;
#ifdef KEYSTONE2_EMAC_GIG_ENABLE
@ -30,6 +31,7 @@ static unsigned int sys_has_mdio = 1;
#define RX_BUFF_NUMS 24
#define RX_BUFF_LEN 1520
#define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
#define SGMII_ANEG_TIMEOUT 4000
static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
@ -40,15 +42,7 @@ struct rx_buff_desc net_rx_buffs = {
.rx_flow = 22,
};
static void keystone2_eth_mdio_enable(void);
static int gen_get_link_speed(int phy_addr);
/* EMAC Addresses */
static volatile struct emac_regs *adap_emac =
(struct emac_regs *)EMAC_EMACSL_BASE_ADDR;
static volatile struct mdio_regs *adap_mdio =
(struct mdio_regs *)EMAC_MDIO_BASE_ADDR;
static void keystone2_net_serdes_setup(void);
int keystone2_eth_read_mac_addr(struct eth_device *dev)
{
@ -74,64 +68,67 @@ int keystone2_eth_read_mac_addr(struct eth_device *dev)
return 0;
}
static void keystone2_eth_mdio_enable(void)
/* MDIO */
static int keystone2_mdio_reset(struct mii_dev *bus)
{
u_int32_t clkdiv;
struct mdio_regs *adap_mdio = bus->priv;
clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
writel((clkdiv & 0xffff) |
MDIO_CONTROL_ENABLE |
MDIO_CONTROL_FAULT |
MDIO_CONTROL_FAULT_ENABLE,
writel((clkdiv & 0xffff) | MDIO_CONTROL_ENABLE |
MDIO_CONTROL_FAULT | MDIO_CONTROL_FAULT_ENABLE,
&adap_mdio->control);
while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE)
;
return 0;
}
/* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
int keystone2_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
/**
* keystone2_mdio_read - read a PHY register via MDIO interface.
* Blocks until operation is complete.
*/
static int keystone2_mdio_read(struct mii_dev *bus,
int addr, int devad, int reg)
{
int tmp;
struct mdio_regs *adap_mdio = bus->priv;
while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
;
writel(MDIO_USERACCESS0_GO |
MDIO_USERACCESS0_WRITE_READ |
((reg_num & 0x1f) << 21) |
((phy_addr & 0x1f) << 16),
writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_READ |
((reg & 0x1f) << 21) | ((addr & 0x1f) << 16),
&adap_mdio->useraccess0);
/* Wait for command to complete */
while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO)
;
if (tmp & MDIO_USERACCESS0_ACK) {
*data = tmp & 0xffff;
return 0;
}
if (tmp & MDIO_USERACCESS0_ACK)
return tmp & 0xffff;
*data = -1;
return -1;
}
/*
* Write to a PHY register via MDIO inteface.
/**
* keystone2_mdio_write - write to a PHY register via MDIO interface.
* Blocks until operation is complete.
*/
int keystone2_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
static int keystone2_mdio_write(struct mii_dev *bus,
int addr, int devad, int reg, u16 val)
{
struct mdio_regs *adap_mdio = bus->priv;
while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
;
writel(MDIO_USERACCESS0_GO |
MDIO_USERACCESS0_WRITE_WRITE |
((reg_num & 0x1f) << 21) |
((phy_addr & 0x1f) << 16) |
(data & 0xffff),
&adap_mdio->useraccess0);
writel(MDIO_USERACCESS0_GO | MDIO_USERACCESS0_WRITE_WRITE |
((reg & 0x1f) << 21) | ((addr & 0x1f) << 16) |
(val & 0xffff), &adap_mdio->useraccess0);
/* Wait for command to complete */
while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO)
@ -140,19 +137,6 @@ int keystone2_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data)
return 0;
}
/* PHY functions for a generic PHY */
static int gen_get_link_speed(int phy_addr)
{
u_int16_t tmp;
if ((!keystone2_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp)) &&
(tmp & 0x04)) {
return 0;
}
return -1;
}
static void __attribute__((unused))
keystone2_eth_gigabit_enable(struct eth_device *dev)
{
@ -160,8 +144,10 @@ static void __attribute__((unused))
struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
if (sys_has_mdio) {
if (keystone2_eth_phy_read(eth_priv->phy_addr, 0, &data) ||
!(data & (1 << 6))) /* speed selection MSB */
data = keystone2_mdio_read(mdio_bus, eth_priv->phy_addr,
MDIO_DEVAD_NONE, 0);
/* speed selection MSB */
if (!(data & (1 << 6)))
return;
}
@ -169,10 +155,10 @@ static void __attribute__((unused))
* Check if link detected is giga-bit
* If Gigabit mode detected, enable gigbit in MAC
*/
writel(readl(&(adap_emac[eth_priv->slave_port - 1].maccontrol)) |
writel(readl(DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) +
CPGMACSL_REG_CTL) |
EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
&(adap_emac[eth_priv->slave_port - 1].maccontrol))
;
DEVICE_EMACSL_BASE(eth_priv->slave_port - 1) + CPGMACSL_REG_CTL);
}
int keystone_sgmii_link_status(int port)
@ -181,38 +167,11 @@ int keystone_sgmii_link_status(int port)
status = __raw_readl(SGMII_STATUS_REG(port));
return status & SGMII_REG_STATUS_LINK;
return (status & SGMII_REG_STATUS_LOCK) &&
(status & SGMII_REG_STATUS_LINK);
}
int keystone_get_link_status(struct eth_device *dev)
{
struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
int sgmii_link;
int link_state = 0;
#if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1
int j;
for (j = 0; (j < CONFIG_GET_LINK_STATUS_ATTEMPTS) && (link_state == 0);
j++) {
#endif
sgmii_link =
keystone_sgmii_link_status(eth_priv->slave_port - 1);
if (sgmii_link) {
link_state = 1;
if (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY)
if (gen_get_link_speed(eth_priv->phy_addr))
link_state = 0;
}
#if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1
}
#endif
return link_state;
}
int keystone_sgmii_config(int port, int interface)
int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
{
unsigned int i, status, mask;
unsigned int mr_adv_ability, control;
@ -273,12 +232,36 @@ int keystone_sgmii_config(int port, int interface)
if (control & SGMII_REG_CONTROL_AUTONEG)
mask |= SGMII_REG_STATUS_AUTONEG;
for (i = 0; i < 1000; i++) {
status = __raw_readl(SGMII_STATUS_REG(port));
if ((status & mask) == mask)
break;
return 0;
printf("\n%s Waiting for SGMII auto negotiation to complete",
phy_dev->dev->name);
while ((status & mask) != mask) {
/*
* Timeout reached ?
*/
if (i > SGMII_ANEG_TIMEOUT) {
puts(" TIMEOUT !\n");
phy_dev->link = 0;
return 0;
}
if (ctrlc()) {
puts("user interrupt!\n");
phy_dev->link = 0;
return -EINTR;
}
if ((i++ % 500) == 0)
printf(".");
udelay(1000); /* 1 ms */
status = __raw_readl(SGMII_STATUS_REG(port));
}
puts(" done\n");
return 0;
}
@ -332,6 +315,11 @@ int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
#ifdef CONFIG_K2E_EVM
/* Map RX packet flow priority to 0 */
writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
#endif
return ret;
}
@ -393,15 +381,15 @@ int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num)
if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE)
num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE;
return netcp_send(buffer, num_bytes, (slave_port_num) << 16);
return ksnav_send(&netcp_pktdma, buffer,
num_bytes, (slave_port_num) << 16);
}
/* Eth device open */
static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
{
u_int32_t clkdiv;
int link;
struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
struct phy_device *phy_dev = eth_priv->phy_dev;
debug("+ emac_open\n");
@ -410,15 +398,9 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
sys_has_mdio =
(eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;
psc_enable_module(KS2_LPSC_PA);
psc_enable_module(KS2_LPSC_CPGMAC);
keystone2_net_serdes_setup();
sgmii_serdes_setup_156p25mhz();
if (sys_has_mdio)
keystone2_eth_mdio_enable();
keystone_sgmii_config(eth_priv->slave_port - 1,
keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1,
eth_priv->sgmii_link_type);
udelay(10000);
@ -431,7 +413,7 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
printf("ERROR: qm_init()\n");
return -1;
}
if (netcp_init(&net_rx_buffs)) {
if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) {
qm_close();
printf("ERROR: netcp_init()\n");
return -1;
@ -445,18 +427,11 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
hw_config_streaming_switch();
if (sys_has_mdio) {
/* Init MDIO & get link state */
clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE |
MDIO_CONTROL_FAULT, &adap_mdio->control)
;
keystone2_mdio_reset(mdio_bus);
/* We need to wait for MDIO to start */
udelay(1000);
link = keystone_get_link_status(dev);
if (link == 0) {
netcp_close();
phy_startup(phy_dev);
if (phy_dev->link == 0) {
ksnav_close(&netcp_pktdma);
qm_close();
return -1;
}
@ -476,6 +451,9 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
/* Eth device close */
void keystone2_eth_close(struct eth_device *dev)
{
struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
struct phy_device *phy_dev = eth_priv->phy_dev;
debug("+ emac_close\n");
if (!emac_open)
@ -483,16 +461,15 @@ void keystone2_eth_close(struct eth_device *dev)
ethss_stop();
netcp_close();
ksnav_close(&netcp_pktdma);
qm_close();
phy_shutdown(phy_dev);
emac_open = 0;
debug("- emac_close\n");
}
static int tx_send_loop;
/*
* This function sends a single packet on the network and returns
* positive number (number of bytes transmitted) or negative for error
@ -502,22 +479,15 @@ static int keystone2_eth_send_packet(struct eth_device *dev,
{
int ret_status = -1;
struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv;
struct phy_device *phy_dev = eth_priv->phy_dev;
tx_send_loop = 0;
if (keystone_get_link_status(dev) == 0)
genphy_update_link(phy_dev);
if (phy_dev->link == 0)
return -1;
emac_gigabit_enable(dev);
if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0)
return ret_status;
if (keystone_get_link_status(dev) == 0)
return -1;
emac_gigabit_enable(dev);
return length;
}
@ -530,13 +500,13 @@ static int keystone2_eth_rcv_packet(struct eth_device *dev)
int pkt_size;
u32 *pkt;
hd = netcp_recv(&pkt, &pkt_size);
hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size);
if (hd == NULL)
return 0;
NetReceive((uchar *)pkt, pkt_size);
netcp_release_rxhd(hd);
ksnav_release_rxhd(&netcp_pktdma, hd);
return pkt_size;
}
@ -546,7 +516,9 @@ static int keystone2_eth_rcv_packet(struct eth_device *dev)
*/
int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
{
int res;
struct eth_device *dev;
struct phy_device *phy_dev;
dev = malloc(sizeof(struct eth_device));
if (dev == NULL)
@ -567,145 +539,55 @@ int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
eth_register(dev);
/* Register MDIO bus if it's not registered yet */
if (!mdio_bus) {
mdio_bus = mdio_alloc();
mdio_bus->read = keystone2_mdio_read;
mdio_bus->write = keystone2_mdio_write;
mdio_bus->reset = keystone2_mdio_reset;
mdio_bus->priv = (void *)EMAC_MDIO_BASE_ADDR;
sprintf(mdio_bus->name, "ethernet-mdio");
res = mdio_register(mdio_bus);
if (res)
return res;
}
/* Create phy device and bind it with driver */
#ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr,
dev, PHY_INTERFACE_MODE_SGMII);
phy_config(phy_dev);
#else
phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr,
PHY_INTERFACE_MODE_SGMII);
phy_dev->dev = dev;
#endif
eth_priv->phy_dev = phy_dev;
return 0;
}
void sgmii_serdes_setup_156p25mhz(void)
struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
.clk = SERDES_CLOCK_156P25M,
.rate = SERDES_RATE_5G,
.rate_mode = SERDES_QUARTER_RATE,
.intf = SERDES_PHY_SGMII,
.loopback = 0,
};
static void keystone2_net_serdes_setup(void)
{
unsigned int cnt;
ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
&ks2_serdes_sgmii_156p25mhz,
CONFIG_KSNET_SERDES_LANES_PER_SGMII);
/*
* configure Serializer/Deserializer (SerDes) hardware. SerDes IP
* hardware vendor published only register addresses and their values
* to be used for configuring SerDes. So had to use hardcoded values
* below.
*/
clrsetbits_le32(0x0232a000, 0xffff0000, 0x00800000);
clrsetbits_le32(0x0232a014, 0x0000ffff, 0x00008282);
clrsetbits_le32(0x0232a060, 0x00ffffff, 0x00142438);
clrsetbits_le32(0x0232a064, 0x00ffff00, 0x00c3c700);
clrsetbits_le32(0x0232a078, 0x0000ff00, 0x0000c000);
#ifdef CONFIG_SOC_K2E
ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
&ks2_serdes_sgmii_156p25mhz,
CONFIG_KSNET_SERDES_LANES_PER_SGMII);
#endif
clrsetbits_le32(0x0232a204, 0xff0000ff, 0x38000080);
clrsetbits_le32(0x0232a208, 0x000000ff, 0x00000000);
clrsetbits_le32(0x0232a20c, 0xff000000, 0x02000000);
clrsetbits_le32(0x0232a210, 0xff000000, 0x1b000000);
clrsetbits_le32(0x0232a214, 0x0000ffff, 0x00006fb8);
clrsetbits_le32(0x0232a218, 0xffff00ff, 0x758000e4);
clrsetbits_le32(0x0232a2ac, 0x0000ff00, 0x00004400);
clrsetbits_le32(0x0232a22c, 0x00ffff00, 0x00200800);
clrsetbits_le32(0x0232a280, 0x00ff00ff, 0x00820082);
clrsetbits_le32(0x0232a284, 0xffffffff, 0x1d0f0385);
clrsetbits_le32(0x0232a404, 0xff0000ff, 0x38000080);
clrsetbits_le32(0x0232a408, 0x000000ff, 0x00000000);
clrsetbits_le32(0x0232a40c, 0xff000000, 0x02000000);
clrsetbits_le32(0x0232a410, 0xff000000, 0x1b000000);
clrsetbits_le32(0x0232a414, 0x0000ffff, 0x00006fb8);
clrsetbits_le32(0x0232a418, 0xffff00ff, 0x758000e4);
clrsetbits_le32(0x0232a4ac, 0x0000ff00, 0x00004400);
clrsetbits_le32(0x0232a42c, 0x00ffff00, 0x00200800);
clrsetbits_le32(0x0232a480, 0x00ff00ff, 0x00820082);
clrsetbits_le32(0x0232a484, 0xffffffff, 0x1d0f0385);
clrsetbits_le32(0x0232a604, 0xff0000ff, 0x38000080);
clrsetbits_le32(0x0232a608, 0x000000ff, 0x00000000);
clrsetbits_le32(0x0232a60c, 0xff000000, 0x02000000);
clrsetbits_le32(0x0232a610, 0xff000000, 0x1b000000);
clrsetbits_le32(0x0232a614, 0x0000ffff, 0x00006fb8);
clrsetbits_le32(0x0232a618, 0xffff00ff, 0x758000e4);
clrsetbits_le32(0x0232a6ac, 0x0000ff00, 0x00004400);
clrsetbits_le32(0x0232a62c, 0x00ffff00, 0x00200800);
clrsetbits_le32(0x0232a680, 0x00ff00ff, 0x00820082);
clrsetbits_le32(0x0232a684, 0xffffffff, 0x1d0f0385);
clrsetbits_le32(0x0232a804, 0xff0000ff, 0x38000080);
clrsetbits_le32(0x0232a808, 0x000000ff, 0x00000000);
clrsetbits_le32(0x0232a80c, 0xff000000, 0x02000000);
clrsetbits_le32(0x0232a810, 0xff000000, 0x1b000000);
clrsetbits_le32(0x0232a814, 0x0000ffff, 0x00006fb8);
clrsetbits_le32(0x0232a818, 0xffff00ff, 0x758000e4);
clrsetbits_le32(0x0232a8ac, 0x0000ff00, 0x00004400);
clrsetbits_le32(0x0232a82c, 0x00ffff00, 0x00200800);
clrsetbits_le32(0x0232a880, 0x00ff00ff, 0x00820082);
clrsetbits_le32(0x0232a884, 0xffffffff, 0x1d0f0385);
clrsetbits_le32(0x0232aa00, 0x0000ff00, 0x00000800);
clrsetbits_le32(0x0232aa08, 0xffff0000, 0x38a20000);
clrsetbits_le32(0x0232aa30, 0x00ffff00, 0x008a8a00);
clrsetbits_le32(0x0232aa84, 0x0000ff00, 0x00000600);
clrsetbits_le32(0x0232aa94, 0xff000000, 0x10000000);
clrsetbits_le32(0x0232aaa0, 0xff000000, 0x81000000);
clrsetbits_le32(0x0232aabc, 0xff000000, 0xff000000);
clrsetbits_le32(0x0232aac0, 0x000000ff, 0x0000008b);
clrsetbits_le32(0x0232ab08, 0xffff0000, 0x583f0000);
clrsetbits_le32(0x0232ab0c, 0x000000ff, 0x0000004e);
clrsetbits_le32(0x0232a000, 0x000000ff, 0x00000003);
clrsetbits_le32(0x0232aa00, 0x000000ff, 0x0000005f);
clrsetbits_le32(0x0232aa48, 0x00ffff00, 0x00fd8c00);
clrsetbits_le32(0x0232aa54, 0x00ffffff, 0x002fec72);
clrsetbits_le32(0x0232aa58, 0xffffff00, 0x00f92100);
clrsetbits_le32(0x0232aa5c, 0xffffffff, 0x00040060);
clrsetbits_le32(0x0232aa60, 0xffffffff, 0x00008000);
clrsetbits_le32(0x0232aa64, 0xffffffff, 0x0c581220);
clrsetbits_le32(0x0232aa68, 0xffffffff, 0xe13b0602);
clrsetbits_le32(0x0232aa6c, 0xffffffff, 0xb8074cc1);
clrsetbits_le32(0x0232aa70, 0xffffffff, 0x3f02e989);
clrsetbits_le32(0x0232aa74, 0x000000ff, 0x00000001);
clrsetbits_le32(0x0232ab20, 0x00ff0000, 0x00370000);
clrsetbits_le32(0x0232ab1c, 0xff000000, 0x37000000);
clrsetbits_le32(0x0232ab20, 0x000000ff, 0x0000005d);
/*Bring SerDes out of Reset if SerDes is Shutdown & is in Reset Mode*/
clrbits_le32(0x0232a010, 1 << 28);
/* Enable TX and RX via the LANExCTL_STS 0x0000 + x*4 */
clrbits_le32(0x0232a228, 1 << 29);
writel(0xF800F8C0, 0x0232bfe0);
clrbits_le32(0x0232a428, 1 << 29);
writel(0xF800F8C0, 0x0232bfe4);
clrbits_le32(0x0232a628, 1 << 29);
writel(0xF800F8C0, 0x0232bfe8);
clrbits_le32(0x0232a828, 1 << 29);
writel(0xF800F8C0, 0x0232bfec);
/*Enable pll via the pll_ctrl 0x0014*/
writel(0xe0000000, 0x0232bff4)
;
/*Waiting for SGMII Serdes PLL lock.*/
for (cnt = 10000; cnt > 0 && ((readl(0x02090114) & 0x10) == 0); cnt--)
;
for (cnt = 10000; cnt > 0 && ((readl(0x02090214) & 0x10) == 0); cnt--)
;
for (cnt = 10000; cnt > 0 && ((readl(0x02090414) & 0x10) == 0); cnt--)
;
for (cnt = 10000; cnt > 0 && ((readl(0x02090514) & 0x10) == 0); cnt--)
;
udelay(45000);
}
void sgmii_serdes_shutdown(void)
{
/*
* shutdown SerDes hardware. SerDes hardware vendor published only
* register addresses and their values. So had to use hardcoded
* values below.
*/
clrbits_le32(0x0232bfe0, 3 << 29 | 3 << 13);
setbits_le32(0x02320228, 1 << 29);
clrbits_le32(0x0232bfe4, 3 << 29 | 3 << 13);
setbits_le32(0x02320428, 1 << 29);
clrbits_le32(0x0232bfe8, 3 << 29 | 3 << 13);
setbits_le32(0x02320628, 1 << 29);
clrbits_le32(0x0232bfec, 3 << 29 | 3 << 13);
setbits_le32(0x02320828, 1 << 29);
clrbits_le32(0x02320034, 3 << 29);
setbits_le32(0x02320010, 1 << 28);
/* wait till setup */
udelay(5000);
}

2
drivers/net/phy/phy.c
View file

@ -648,7 +648,7 @@ static struct phy_device *get_phy_device_by_mask(struct mii_dev *bus,
if (phydev)
return phydev;
}
printf("Phy not found\n");
printf("Phy %d not found\n", ffs(phy_mask) - 1);
return phy_device_create(bus, ffs(phy_mask) - 1, 0xffffffff, interface);
}

5
drivers/soc/Makefile Normal file
View file

@ -0,0 +1,5 @@
#
# Makefile for the U-boot SOC specific device drivers.
#
obj-$(CONFIG_ARCH_KEYSTONE) += keystone/

1
drivers/soc/keystone/Makefile Normal file
View file

@ -0,0 +1 @@
obj-$(CONFIG_TI_KEYSTONE_SERDES) += keystone_serdes.o

210
drivers/soc/keystone/keystone_serdes.c Normal file
View file

@ -0,0 +1,210 @@
/*
* TI serdes driver for keystone2.
*
* (C) Copyright 2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <errno.h>
#include <common.h>
#include <asm/ti-common/keystone_serdes.h>
#define SERDES_CMU_REGS(x) (0x0000 + (0x0c00 * (x)))
#define SERDES_LANE_REGS(x) (0x0200 + (0x200 * (x)))
#define SERDES_COMLANE_REGS 0x0a00
#define SERDES_WIZ_REGS 0x1fc0
#define SERDES_CMU_REG_000(x) (SERDES_CMU_REGS(x) + 0x000)
#define SERDES_CMU_REG_010(x) (SERDES_CMU_REGS(x) + 0x010)
#define SERDES_COMLANE_REG_000 (SERDES_COMLANE_REGS + 0x000)
#define SERDES_LANE_REG_000(x) (SERDES_LANE_REGS(x) + 0x000)
#define SERDES_LANE_REG_028(x) (SERDES_LANE_REGS(x) + 0x028)
#define SERDES_LANE_CTL_STATUS_REG(x) (SERDES_WIZ_REGS + 0x0020 + (4 * (x)))
#define SERDES_PLL_CTL_REG (SERDES_WIZ_REGS + 0x0034)
#define SERDES_RESET BIT(28)
#define SERDES_LANE_RESET BIT(29)
#define SERDES_LANE_LOOPBACK BIT(30)
#define SERDES_LANE_EN_VAL(x, y, z) (x[y] | (z << 26) | (z << 10))
#define SERDES_CMU_CFG_NUM 5
#define SERDES_COMLANE_CFG_NUM 10
#define SERDES_LANE_CFG_NUM 10
struct serdes_cfg {
u32 ofs;
u32 val;
u32 mask;
};
struct cfg_entry {
enum ks2_serdes_clock clk;
enum ks2_serdes_rate rate;
struct serdes_cfg cmu[SERDES_CMU_CFG_NUM];
struct serdes_cfg comlane[SERDES_COMLANE_CFG_NUM];
struct serdes_cfg lane[SERDES_LANE_CFG_NUM];
};
/* SERDES PHY lane enable configuration value, indexed by PHY interface */
static u32 serdes_cfg_lane_enable[] = {
0xf000f0c0, /* SGMII */
0xf0e9f038, /* PCSR */
};
/* SERDES PHY PLL enable configuration value, indexed by PHY interface */
static u32 serdes_cfg_pll_enable[] = {
0xe0000000, /* SGMII */
0xee000000, /* PCSR */
};
/**
* Array to hold all possible serdes configurations.
* Combination for 5 clock settings and 6 baud rates.
*/
static struct cfg_entry cfgs[] = {
{
.clk = SERDES_CLOCK_156P25M,
.rate = SERDES_RATE_5G,
.cmu = {
{0x0000, 0x00800000, 0xffff0000},
{0x0014, 0x00008282, 0x0000ffff},
{0x0060, 0x00142438, 0x00ffffff},
{0x0064, 0x00c3c700, 0x00ffff00},
{0x0078, 0x0000c000, 0x0000ff00}
},
.comlane = {
{0x0a00, 0x00000800, 0x0000ff00},
{0x0a08, 0x38a20000, 0xffff0000},
{0x0a30, 0x008a8a00, 0x00ffff00},
{0x0a84, 0x00000600, 0x0000ff00},
{0x0a94, 0x10000000, 0xff000000},
{0x0aa0, 0x81000000, 0xff000000},
{0x0abc, 0xff000000, 0xff000000},
{0x0ac0, 0x0000008b, 0x000000ff},
{0x0b08, 0x583f0000, 0xffff0000},
{0x0b0c, 0x0000004e, 0x000000ff}
},
.lane = {
{0x0004, 0x38000080, 0xff0000ff},
{0x0008, 0x00000000, 0x000000ff},
{0x000c, 0x02000000, 0xff000000},
{0x0010, 0x1b000000, 0xff000000},
{0x0014, 0x00006fb8, 0x0000ffff},
{0x0018, 0x758000e4, 0xffff00ff},
{0x00ac, 0x00004400, 0x0000ff00},
{0x002c, 0x00100800, 0x00ffff00},
{0x0080, 0x00820082, 0x00ff00ff},
{0x0084, 0x1d0f0385, 0xffffffff}
},
},
};
static inline void ks2_serdes_rmw(u32 addr, u32 value, u32 mask)
{
writel(((readl(addr) & (~mask)) | (value & mask)), addr);
}
static void ks2_serdes_cfg_setup(u32 base, struct serdes_cfg *cfg, u32 size)
{
u32 i;
for (i = 0; i < size; i++)
ks2_serdes_rmw(base + cfg[i].ofs, cfg[i].val, cfg[i].mask);
}
static void ks2_serdes_lane_config(u32 base, struct serdes_cfg *cfg_lane,
u32 size, u32 lane)
{
u32 i;
for (i = 0; i < size; i++)
ks2_serdes_rmw(base + cfg_lane[i].ofs + SERDES_LANE_REGS(lane),
cfg_lane[i].val, cfg_lane[i].mask);
}
static int ks2_serdes_init_cfg(u32 base, struct cfg_entry *cfg, u32 num_lanes)
{
u32 i;
ks2_serdes_cfg_setup(base, cfg->cmu, SERDES_CMU_CFG_NUM);
ks2_serdes_cfg_setup(base, cfg->comlane, SERDES_COMLANE_CFG_NUM);
for (i = 0; i < num_lanes; i++)
ks2_serdes_lane_config(base, cfg->lane, SERDES_LANE_CFG_NUM, i);
return 0;
}
static void ks2_serdes_cmu_comlane_enable(u32 base, struct ks2_serdes *serdes)
{
/* Bring SerDes out of Reset */
ks2_serdes_rmw(base + SERDES_CMU_REG_010(0), 0x0, SERDES_RESET);
if (serdes->intf == SERDES_PHY_PCSR)
ks2_serdes_rmw(base + SERDES_CMU_REG_010(1), 0x0, SERDES_RESET);
/* Enable CMU and COMLANE */
ks2_serdes_rmw(base + SERDES_CMU_REG_000(0), 0x03, 0x000000ff);
if (serdes->intf == SERDES_PHY_PCSR)
ks2_serdes_rmw(base + SERDES_CMU_REG_000(1), 0x03, 0x000000ff);
ks2_serdes_rmw(base + SERDES_COMLANE_REG_000, 0x5f, 0x000000ff);
}
static void ks2_serdes_pll_enable(u32 base, struct ks2_serdes *serdes)
{
writel(serdes_cfg_pll_enable[serdes->intf],
base + SERDES_PLL_CTL_REG);
}
static void ks2_serdes_lane_reset(u32 base, u32 reset, u32 lane)
{
if (reset)
ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane),
0x1, SERDES_LANE_RESET);
else
ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane),
0x0, SERDES_LANE_RESET);
}
static void ks2_serdes_lane_enable(u32 base,
struct ks2_serdes *serdes, u32 lane)
{
/* Bring lane out of reset */
ks2_serdes_lane_reset(base, 0, lane);
writel(SERDES_LANE_EN_VAL(serdes_cfg_lane_enable, serdes->intf,
serdes->rate_mode),
base + SERDES_LANE_CTL_STATUS_REG(lane));
/* Set NES bit if Loopback Enabled */
if (serdes->loopback)
ks2_serdes_rmw(base + SERDES_LANE_REG_000(lane),
0x1, SERDES_LANE_LOOPBACK);
}
int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes)
{
int i;
int ret = 0;
for (i = 0; i < ARRAY_SIZE(cfgs); i++)
if (serdes->clk == cfgs[i].clk && serdes->rate == cfgs[i].rate)
break;
if (i >= ARRAY_SIZE(cfgs)) {
puts("Cannot find keystone SerDes configuration");
return -EINVAL;
}
ks2_serdes_init_cfg(base, &cfgs[i], num_lanes);
ks2_serdes_cmu_comlane_enable(base, serdes);
for (i = 0; i < num_lanes; i++)
ks2_serdes_lane_enable(base, serdes, i);
ks2_serdes_pll_enable(base, serdes);
return ret;
}

1
drivers/usb/host/Makefile
View file

@ -43,6 +43,7 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
# xhci
obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o

329
drivers/usb/host/xhci-keystone.c Normal file
View file

@ -0,0 +1,329 @@
/*
* USB 3.0 DRD Controller
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <watchdog.h>
#include <usb.h>
#include <asm/arch/psc_defs.h>
#include <asm/io.h>
#include <linux/usb/dwc3.h>
#include <asm/arch/xhci-keystone.h>
#include <asm-generic/errno.h>
#include <linux/list.h>
#include "xhci.h"
struct kdwc3_irq_regs {
u32 revision; /* 0x000 */
u32 rsvd0[3];
u32 sysconfig; /* 0x010 */
u32 rsvd1[1];
u32 irq_eoi;
u32 rsvd2[1];
struct {
u32 raw_status;
u32 status;
u32 enable_set;
u32 enable_clr;
} irqs[16];
};
struct keystone_xhci {
struct xhci_hccr *hcd;
struct dwc3 *dwc3_reg;
struct xhci_hcor *hcor;
struct kdwc3_irq_regs *usbss;
struct keystone_xhci_phy *phy;
};
struct keystone_xhci keystone;
static void keystone_xhci_phy_set(struct keystone_xhci_phy *phy)
{
u32 val;
/*
* VBUSVLDEXTSEL has a default value of 1 in BootCfg but shouldn't.
* It should always be cleared because our USB PHY has an onchip VBUS
* analog comparator.
*/
val = readl(&phy->phy_clock);
/* quit selecting the vbusvldextsel by default! */
val &= ~USB3_PHY_OTG_VBUSVLDECTSEL;
writel(val, &phy->phy_clock);
}
static void keystone_xhci_phy_unset(struct keystone_xhci_phy *phy)
{
u32 val;
/* Disable the PHY REFCLK clock gate */
val = readl(&phy->phy_clock);
val &= ~USB3_PHY_REF_SSP_EN;
writel(val, &phy->phy_clock);
}
static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
{
clrsetbits_le32(&dwc3_reg->g_ctl,
DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
DWC3_GCTL_PRTCAPDIR(mode));
}
static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
{
/* Before Resetting PHY, put Core in Reset */
setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
/* Assert USB3 PHY reset */
setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
/* Assert USB2 PHY reset */
setbits_le32(&dwc3_reg->g_usb2phycfg[0], DWC3_GUSB2PHYCFG_PHYSOFTRST);
mdelay(100);
/* Clear USB3 PHY reset */
clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
/* Clear USB2 PHY reset */
clrbits_le32(&dwc3_reg->g_usb2phycfg[0], DWC3_GUSB2PHYCFG_PHYSOFTRST);
/* After PHYs are stable we can take Core out of reset state */
clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
}
static int dwc3_core_init(struct dwc3 *dwc3_reg)
{
u32 revision, val;
unsigned long t_rst;
unsigned int dwc3_hwparams1;
revision = readl(&dwc3_reg->g_snpsid);
/* This should read as U3 followed by revision number */
if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
puts("this is not a DesignWare USB3 DRD Core\n");
return -EINVAL;
}
/* issue device SoftReset too */
writel(DWC3_DCTL_CSFTRST, &dwc3_reg->d_ctl);
t_rst = get_timer(0);
do {
val = readl(&dwc3_reg->d_ctl);
if (!(val & DWC3_DCTL_CSFTRST))
break;
WATCHDOG_RESET();
} while (get_timer(t_rst) < 500);
if (val & DWC3_DCTL_CSFTRST) {
debug("Reset timed out\n");
return -2;
}
dwc3_core_soft_reset(dwc3_reg);
dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
val = readl(&dwc3_reg->g_ctl);
val &= ~DWC3_GCTL_SCALEDOWN_MASK;
val &= ~DWC3_GCTL_DISSCRAMBLE;
switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
val &= ~DWC3_GCTL_DSBLCLKGTNG;
break;
default:
printf("No power optimization available\n");
}
/*
* WORKAROUND: DWC3 revisions <1.90a have a bug
* where the device can fail to connect at SuperSpeed
* and falls back to high-speed mode which causes
* the device to enter a Connect/Disconnect loop
*/
if ((revision & DWC3_REVISION_MASK) < 0x190a)
val |= DWC3_GCTL_U2RSTECN;
writel(val, &dwc3_reg->g_ctl);
return 0;
}
static int keystone_xhci_core_init(struct dwc3 *dwc3_reg)
{
int ret;
ret = dwc3_core_init(dwc3_reg);
if (ret) {
debug("failed to initialize core\n");
return -EINVAL;
}
/* We are hard-coding DWC3 core to Host Mode */
dwc3_set_mode(dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
return 0;
}
int xhci_hcd_init(int index,
struct xhci_hccr **ret_hccr, struct xhci_hcor **ret_hcor)
{
u32 val;
int ret;
struct xhci_hccr *hcd;
struct xhci_hcor *hcor;
struct kdwc3_irq_regs *usbss;
struct keystone_xhci_phy *phy;
usbss = (struct kdwc3_irq_regs *)CONFIG_USB_SS_BASE;
phy = (struct keystone_xhci_phy *)CONFIG_DEV_USB_PHY_BASE;
/* Enable the PHY REFCLK clock gate with phy_ref_ssp_en = 1 */
val = readl(&(phy->phy_clock));
val |= USB3_PHY_REF_SSP_EN;
writel(val, &phy->phy_clock);
mdelay(100);
/* Release USB from reset */
ret = psc_enable_module(KS2_LPSC_USB);
if (ret) {
puts("Cannot enable USB module");
return -1;
}
mdelay(100);
/* Initialize usb phy */
keystone_xhci_phy_set(phy);
/* soft reset usbss */
writel(1, &usbss->sysconfig);
while (readl(&usbss->sysconfig) & 1)
;
val = readl(&usbss->revision);
debug("usbss revision %x\n", val);
/* Initialize usb core */
hcd = (struct xhci_hccr *)CONFIG_USB_HOST_XHCI_BASE;
keystone.dwc3_reg = (struct dwc3 *)(CONFIG_USB_HOST_XHCI_BASE +
DWC3_REG_OFFSET);
keystone_xhci_core_init(keystone.dwc3_reg);
/* set register addresses */
hcor = (struct xhci_hcor *)((uint32_t)hcd +
HC_LENGTH(readl(&hcd->cr_capbase)));
debug("Keystone2-xhci: init hccr %08x and hcor %08x hc_length %d\n",
(u32)hcd, (u32)hcor,
(u32)HC_LENGTH(xhci_readl(&hcd->cr_capbase)));
keystone.usbss = usbss;
keystone.phy = phy;
keystone.hcd = hcd;
keystone.hcor = hcor;
*ret_hccr = hcd;
*ret_hcor = hcor;
return 0;
}
static int keystone_xhci_phy_suspend(void)
{
int loop_cnt = 0;
struct xhci_hcor *hcor;
uint32_t *portsc_1 = NULL;
uint32_t *portsc_2 = NULL;
u32 val, usb2_pls, usb3_pls, event_q;
struct dwc3 *dwc3_reg = keystone.dwc3_reg;
/* set register addresses */
hcor = keystone.hcor;
/* Bypass Scrambling and Set Shorter Training sequence for simulation */
val = DWC3_GCTL_PWRDNSCALE(0x4b0) | DWC3_GCTL_PRTCAPDIR(0x2);
writel(val, &dwc3_reg->g_ctl);
/* GUSB2PHYCFG */
val = readl(&dwc3_reg->g_usb2phycfg[0]);
/* assert bit 6 (SusPhy) */
val |= DWC3_GUSB2PHYCFG_SUSPHY;
writel(val, &dwc3_reg->g_usb2phycfg[0]);
/* GUSB3PIPECTL */
val = readl(&dwc3_reg->g_usb3pipectl[0]);
/*
* assert bit 29 to allow PHY to go to suspend when idle
* and cause the USB3 SS PHY to enter suspend mode
*/
val |= (BIT(29) | DWC3_GUSB3PIPECTL_SUSPHY);
writel(val, &dwc3_reg->g_usb3pipectl[0]);
/*
* Steps necessary to allow controller to suspend even when
* VBUS is HIGH:
* - Init DCFG[2:0] (DevSpd) to: 1=FS
* - Init GEVNTADR0 to point to an eventQ
* - Init GEVNTSIZ0 to 0x0100 to specify the size of the eventQ
* - Init DCTL::Run_nStop = 1
*/
writel(0x00020001, &dwc3_reg->d_cfg);
/* TODO: local2global( (Uint32) eventQ )? */
writel((u32)&event_q, &dwc3_reg->g_evnt_buf[0].g_evntadrlo);
writel(0, &dwc3_reg->g_evnt_buf[0].g_evntadrhi);
writel(0x4, &dwc3_reg->g_evnt_buf[0].g_evntsiz);
/* Run */
writel(DWC3_DCTL_RUN_STOP, &dwc3_reg->d_ctl);
mdelay(100);
/* Wait for USB2 & USB3 PORTSC::PortLinkState to indicate suspend */
portsc_1 = (uint32_t *)(&hcor->portregs[0].or_portsc);
portsc_2 = (uint32_t *)(&hcor->portregs[1].or_portsc);
usb2_pls = 0;
usb3_pls = 0;
do {
++loop_cnt;
usb2_pls = (readl(portsc_1) & PORT_PLS_MASK) >> 5;
usb3_pls = (readl(portsc_2) & PORT_PLS_MASK) >> 5;
} while (((usb2_pls != 0x4) || (usb3_pls != 0x4)) && loop_cnt < 1000);
if (usb2_pls != 0x4 || usb3_pls != 0x4) {
debug("USB suspend failed - PLS USB2=%02x, USB3=%02x\n",
usb2_pls, usb3_pls);
return -1;
}
debug("USB2 and USB3 PLS - Disabled, loop_cnt=%d\n", loop_cnt);
return 0;
}
void xhci_hcd_stop(int index)
{
/* Disable USB */
if (keystone_xhci_phy_suspend())
return;
if (psc_disable_module(KS2_LPSC_USB)) {
debug("PSC disable module USB failed!\n");
return;
}
/* Disable PHY */
keystone_xhci_phy_unset(keystone.phy);
/* memset(&keystone, 0, sizeof(struct keystone_xhci)); */
debug("xhci_hcd_stop OK.\n");
}

10
include/configs/am335x_evm.h
View file

@ -352,10 +352,10 @@
"boot part 0 1;" \
"rootfs part 0 2;" \
"MLO fat 0 1;" \
"MLO.raw mmc 0x100 0x100;" \
"u-boot.img.raw mmc 0x300 0x400;" \
"spl-os-args.raw mmc 0x80 0x80;" \
"spl-os-image.raw mmc 0x900 0x2000;" \
"MLO.raw raw 0x100 0x100;" \
"u-boot.img.raw raw 0x300 0x400;" \
"spl-os-args.raw raw 0x80 0x80;" \
"spl-os-image.raw raw 0x900 0x2000;" \
"spl-os-args fat 0 1;" \
"spl-os-image fat 0 1;" \
"u-boot.img fat 0 1;" \
@ -382,7 +382,7 @@
"fdt ram 0x80F80000 0x80000;" \
"ramdisk ram 0x81000000 0x4000000\0"
#define DFUARGS \
"dfu_alt_info_emmc=rawemmc mmc 0 3751936\0" \
"dfu_alt_info_emmc=rawemmc raw 0 3751936\0" \
DFU_ALT_INFO_MMC \
DFU_ALT_INFO_RAM \
DFU_ALT_INFO_NAND

11
include/configs/am43xx_evm.h
View file

@ -11,6 +11,9 @@
#define CONFIG_AM43XX
#define CONFIG_CMD_FAT
#define CONFIG_CMD_SAVEENV
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_CACHELINE_SIZE 32
@ -82,7 +85,11 @@
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_IS_IN_FAT
#define FAT_ENV_INTERFACE "mmc"
#define FAT_ENV_DEVICE_AND_PART "0:1"
#define FAT_ENV_FILE "uboot.env"
#define CONFIG_FAT_WRITE
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
@ -103,7 +110,7 @@
#ifdef CONFIG_QSPI_BOOT
#define CONFIG_SYS_TEXT_BASE 0x30000000
#undef CONFIG_ENV_IS_NOWHERE
#undef CONFIG_ENV_IS_IN_FAT
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED

11
include/configs/k2e_evm.h
View file

@ -34,4 +34,15 @@
/* NAND Configuration */
#define CONFIG_SYS_NAND_PAGE_2K
/* Network */
#define CONFIG_DRIVER_TI_KEYSTONE_NET
#define CONFIG_TI_KSNAV
#define CONFIG_KSNAV_PKTDMA_NETCP
#define CONFIG_KSNET_NETCP_V1_5
#define CONFIG_KSNET_CPSW_NUM_PORTS 9
#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
/* SerDes */
#define CONFIG_TI_KEYSTONE_SERDES
#endif /* __CONFIG_K2E_EVM_H */

7
include/configs/k2hk_evm.h
View file

@ -36,5 +36,12 @@
/* Network */
#define CONFIG_DRIVER_TI_KEYSTONE_NET
#define CONFIG_TI_KSNAV
#define CONFIG_KSNAV_PKTDMA_NETCP
#define CONFIG_KSNET_NETCP_V1_0
#define CONFIG_KSNET_CPSW_NUM_PORTS 5
/* SerDes */
#define CONFIG_TI_KEYSTONE_SERDES
#endif /* __CONFIG_K2HK_EVM_H */

37
include/configs/k2l_evm.h Normal file
View file

@ -0,0 +1,37 @@
/*
* Configuration header file for TI's k2l-evm
*
* (C) Copyright 2012-2014
* Texas Instruments Incorporated, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_K2L_EVM_H
#define __CONFIG_K2L_EVM_H
/* Platform type */
#define CONFIG_SOC_K2L
#define CONFIG_K2L_EVM
/* U-Boot general configuration */
#define CONFIG_SYS_PROMPT "K2L EVM # "
#define KS2_ARGS_UBI "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
"root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,4096\0"
#define KS2_FDT_NAME "name_fdt=k2l-evm.dtb\0"
#define KS2_ADDR_MON "addr_mon=0x0c140000\0"
#define KS2_NAME_MON "name_mon=skern-k2l-evm.bin\0"
#define NAME_UBOOT "name_uboot=u-boot-spi-k2l-evm.gph\0"
#define NAME_UBI "name_ubi=k2l-evm-ubifs.ubi\0"
#include <configs/ks2_evm.h>
/* SPL SPI Loader Configuration */
#define CONFIG_SPL_TEXT_BASE 0x0c100000
/* NAND Configuration */
#define CONFIG_SYS_NAND_PAGE_4K
#endif /* __CONFIG_K2L_EVM_H */

59
include/configs/ks2_evm.h
View file

@ -91,6 +91,8 @@
#define CONFIG_SYS_SPI2_NUM_CS 4
/* Network Configuration */
#define CONFIG_PHYLIB
#define CONFIG_PHY_MARVELL
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
@ -98,11 +100,46 @@
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 32
#define CONFIG_NET_MULTI
#define CONFIG_GET_LINK_STATUS_ATTEMPTS 5
#define CONFIG_SYS_SGMII_REFCLK_MHZ 312
#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250
#define CONFIG_SYS_SGMII_RATESCALE 2
/* Keyston Navigator Configuration */
#define CONFIG_KSNAV_QM_BASE_ADDRESS KS2_QM_BASE_ADDRESS
#define CONFIG_KSNAV_QM_CONF_BASE KS2_QM_CONF_BASE
#define CONFIG_KSNAV_QM_DESC_SETUP_BASE KS2_QM_DESC_SETUP_BASE
#define CONFIG_KSNAV_QM_STATUS_RAM_BASE KS2_QM_STATUS_RAM_BASE
#define CONFIG_KSNAV_QM_INTD_CONF_BASE KS2_QM_INTD_CONF_BASE
#define CONFIG_KSNAV_QM_PDSP1_CMD_BASE KS2_QM_PDSP1_CMD_BASE
#define CONFIG_KSNAV_QM_PDSP1_CTRL_BASE KS2_QM_PDSP1_CTRL_BASE
#define CONFIG_KSNAV_QM_PDSP1_IRAM_BASE KS2_QM_PDSP1_IRAM_BASE
#define CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE KS2_QM_MANAGER_QUEUES_BASE
#define CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE KS2_QM_MANAGER_Q_PROXY_BASE
#define CONFIG_KSNAV_QM_QUEUE_STATUS_BASE KS2_QM_QUEUE_STATUS_BASE
#define CONFIG_KSNAV_QM_LINK_RAM_BASE KS2_QM_LINK_RAM_BASE
#define CONFIG_KSNAV_QM_REGION_NUM KS2_QM_REGION_NUM
#define CONFIG_KSNAV_QM_QPOOL_NUM KS2_QM_QPOOL_NUM
/* NETCP pktdma */
#define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE KS2_NETCP_PDMA_CTRL_BASE
#define CONFIG_KSNAV_NETCP_PDMA_TX_BASE KS2_NETCP_PDMA_TX_BASE
#define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM KS2_NETCP_PDMA_TX_CH_NUM
#define CONFIG_KSNAV_NETCP_PDMA_RX_BASE KS2_NETCP_PDMA_RX_BASE
#define CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM KS2_NETCP_PDMA_RX_CH_NUM
#define CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE KS2_NETCP_PDMA_SCHED_BASE
#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE KS2_NETCP_PDMA_RX_FLOW_BASE
#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM KS2_NETCP_PDMA_RX_FLOW_NUM
#define CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE KS2_NETCP_PDMA_RX_FREE_QUEUE
#define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE KS2_NETCP_PDMA_RX_RCV_QUEUE
#define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE
/* Keystone net */
#define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR
#define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE
#define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE
#define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE
#define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES
/* AEMIF */
#define CONFIG_TI_AEMIF
#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
@ -153,6 +190,20 @@
"1024k(bootloader)ro,512k(params)ro," \
"-(ubifs)"
/* USB Configuration */
#define CONFIG_USB_XHCI
#define CONFIG_USB_XHCI_KEYSTONE
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_FS_FAT
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_USB_SS_BASE KS2_USB_SS_BASE
#define CONFIG_USB_HOST_XHCI_BASE KS2_USB_HOST_XHCI_BASE
#define CONFIG_DEV_USB_PHY_BASE KS2_DEV_USB_PHY_BASE
#define CONFIG_USB_PHY_CFG_BASE KS2_USB_PHY_CFG_BASE
/* U-Boot command configuration */
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
@ -166,9 +217,11 @@
#define CONFIG_CMD_UBIFS
#define CONFIG_CMD_SF
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_USB
/* U-Boot general configuration */
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_MISC_INIT_R
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_PBSIZE 2048
#define CONFIG_SYS_MAXARGS 16
@ -265,8 +318,4 @@
#include <asm/arch/clock.h>
#define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6)
/* Maximum memory size for relocated U-boot at the end of the DDR3 memory
which is NOT applicable for DDR ECC test */
#define CONFIG_MAX_UBOOT_MEM_SIZE (4 << 20) /* 4 MiB */
#endif /* __CONFIG_KS2_EVM_H */

13
include/configs/omap3_overo.h
View file

@ -35,6 +35,13 @@
/* TWL4030 LED */
#define CONFIG_TWL4030_LED
/* USB EHCI */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_OMAP
#define CONFIG_USB_STORAGE
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 183
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
/* Initialize GPIOs by default */
#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO Bank 2 */
#define CONFIG_OMAP3_GPIO_3 /* GPIO64..95 is in GPIO Bank 3 */
@ -44,6 +51,7 @@
/* commands to include */
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_USB
#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
#undef CONFIG_CMD_IMI /* iminfo */
#undef CONFIG_CMD_NFS /* NFS support */
@ -131,8 +139,9 @@
"bootz ${loadaddr} - ${fdtaddr}\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
"nand read ${loadaddr} linux; " \
"bootm ${loadaddr}\0" \
"if nand read ${loadaddr} linux; then " \
"bootm ${loadaddr};" \
"fi;\0" \
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \

8
include/linux/usb/dwc3.h
View file

@ -41,7 +41,8 @@
#define DWC3_REG_OFFSET 0xC100
struct g_event_buffer {
u64 g_evntadr;
u32 g_evntadrlo;
u32 g_evntadrhi;
u32 g_evntsiz;
u32 g_evntcount;
};
@ -185,4 +186,9 @@ struct dwc3 { /* offset: 0xC100 */
#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
/* Device Control Register */
#define DWC3_DCTL_RUN_STOP (1 << 31)
#define DWC3_DCTL_CSFTRST (1 << 30)
#define DWC3_DCTL_LSFTRST (1 << 29)
#endif /* __DWC3_H_ */