Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-24 13:43:28 +00:00
Code Issues Projects Releases Packages Wiki Activity

* Patch by Robin Getz, 13 Oct 2004:

Browse source 
Add standalone application to change SMC91C111 MAC addresses,
  see examples/README.smc91111_eeprom

* Patch by Xiaogeng (Shawn) Jin, 12 Oct 2004:
  Fix Flash support for ARM Integrator CP.
This commit is contained in:
wdenk 2005-01-12 00:38:03 +00:00
parent 289f932c5f
commit 5a95f6fbd2
11 changed files with 850 additions and 115 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
CHANGELOG
View file

@ -2,6 +2,13 @@
Changes for U-Boot 1.1.3:
======================================================================
* Patch by Robin Getz, 13 Oct 2004:
Add standalone application to change SMC91C111 MAC addresses,
see examples/README.smc91111_eeprom
* Patch by Xiaogeng (Shawn) Jin, 12 Oct 2004:
Fix Flash support for ARM Integrator CP.
* Patch by Richard Woodruff, 10 Jan 2005:
Update support for OMAP2420 (ARM11) and H4 board:
o clean up and add new types to H4 memory probe code.

233
board/integratorcp/flash.c
View file

@ -1,4 +1,7 @@
/*
* (C) Copyright 2004
* Xiaogeng (Shawn) Jin, Agilent Technologies, xiaogeng_jin@agilent.com
*
* (C) Copyright 2001
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
@ -31,20 +34,22 @@
#include <common.h>
#include <linux/byteorder/swab.h>
#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
#define DEBUG
#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/* Board support for 1 or 2 flash devices */
#undef FLASH_PORT_WIDTH32
#define FLASH_PORT_WIDTH16
#define FLASH_PORT_WIDTH32
#undef FLASH_PORT_WIDTH16
#ifdef FLASH_PORT_WIDTH16
#define FLASH_PORT_WIDTH ushort
#define FLASH_PORT_WIDTHV vu_short
#define FLASH_PORT_WIDTH ushort
#define FLASH_PORT_WIDTHV vu_short
#define SWAP(x) __swab16(x)
#else
#define FLASH_PORT_WIDTH ulong
#define FLASH_PORT_WIDTHV vu_long
#define FLASH_PORT_WIDTH ulong
#define FLASH_PORT_WIDTHV vu_long
#define SWAP(x) __swab32(x)
#endif
@ -67,6 +72,12 @@ OrgDef OrgIntel_28F256L18T[] = {
{255, 128 * 1024}, /* 255 * 128kBytes sectors */
};
/* CP control register base address */
#define CPCR_BASE 0xCB000000
#define CPCR_EXTRABANK 0x8
#define CPCR_FLASHSIZE 0x4
#define CPCR_FLWREN 0x2
#define CPCR_FLVPPEN 0x1
/*-----------------------------------------------------------------------
* Functions
@ -83,29 +94,50 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
int i;
int i, nbanks;
ulong size = 0;
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
switch (i) {
case 0:
flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
break;
default:
panic ("configured too many flash banks!\n");
break;
}
vu_long *cpcr = (vu_long *)CPCR_BASE;
/* Check if there is an extra bank of flash */
if (cpcr[1] & CPCR_EXTRABANK)
nbanks = 2;
else
nbanks = 1;
if (nbanks > CFG_MAX_FLASH_BANKS)
nbanks = CFG_MAX_FLASH_BANKS;
/* Enable flash write */
cpcr[1] |= 3;
for (i = 0; i < nbanks; i++) {
flash_get_size ((FPW *)(CFG_FLASH_BASE + size), &flash_info[i]);
flash_get_offsets (CFG_FLASH_BASE + size, &flash_info[i]);
size += flash_info[i].size;
}
/* Protect monitor and environment sectors
*/
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* monitor protection */
flash_protect (FLAG_PROTECT_SET,
CFG_FLASH_BASE,
CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
#endif
#ifdef CFG_ENV_IS_IN_FLASH
/* ENV protection ON */
flash_protect(FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
&flash_info[0]);
#endif
/* Protect SIB (0x24800000) and bootMonitor (0x24c00000) */
flash_protect (FLAG_PROTECT_SET,
flash_info[0].start[62],
flash_info[0].start[63] + PHYS_FLASH_SECT_SIZE - 1,
&flash_info[0]);
return size;
}
@ -115,23 +147,15 @@ unsigned long flash_init (void)
static void flash_get_offsets (ulong base, flash_info_t * info)
{
int i;
OrgDef *pOrgDef;
pOrgDef = OrgIntel_28F256L18T;
if (info->flash_id == FLASH_UNKNOWN) {
return;
}
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
for (i = 0; i < info->sector_count; i++) {
if (i > 255) {
info->start[i] = base + (i * 0x8000);
info->protect[i] = 0;
} else {
info->start[i] = base +
(i * PHYS_FLASH_SECT_SIZE);
info->protect[i] = 0;
}
info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE);
info->protect[i] = 0;
}
}
}
@ -156,10 +180,20 @@ void flash_print_info (flash_info_t * info)
break;
}
/* Integrator CP board uses 28F640J3C or 28F128J3C parts,
* which have the same device id numbers as 28F640J3A or
* 28F128J3A
*/
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_28F256L18T:
printf ("FLASH 28F256L18T\n");
break;
case FLASH_28F640J3A:
printf ("FLASH 28F640J3C\n");
break;
case FLASH_28F128J3A:
printf ("FLASH 28F128J3C\n");
break;
default:
printf ("Unknown Chip Type\n");
break;
@ -185,6 +219,17 @@ void flash_print_info (flash_info_t * info)
static ulong flash_get_size (FPW * addr, flash_info_t * info)
{
volatile FPW value;
vu_long *cpcr = (vu_long *)CPCR_BASE;
int nsects;
/* Check the flash size */
if (cpcr[1] & CPCR_FLASHSIZE)
nsects = 128;
else
nsects = 64;
if (nsects > CFG_MAX_FLASH_SECT)
nsects = CFG_MAX_FLASH_SECT;
/* Write auto select command: read Manufacturer ID */
addr[0x5555] = (FPW) 0x00AA00AA;
@ -204,19 +249,31 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info)
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
return (0); /* no or unknown flash */
addr[0] = (FPW) 0x00FF00FF; /* restore read mode */
return (0); /* no or unknown flash */
}
mb ();
value = addr[1]; /* device ID */
value = addr[1]; /* device ID */
switch (value) {
case (FPW) (INTEL_ID_28F256L18T):
info->flash_id += FLASH_28F256L18T;
info->sector_count = 259;
info->size = 0x02000000;
break; /* => 32 MB */
break; /* => 32 MB */
case (FPW) (INTEL_ID_28F640J3A):
info->flash_id += FLASH_28F640J3A;
info->sector_count = nsects;
info->size = nsects * PHYS_FLASH_SECT_SIZE;
break;
case (FPW) (INTEL_ID_28F128J3A):
info->flash_id += FLASH_28F128J3A;
info->sector_count = nsects;
info->size = nsects * PHYS_FLASH_SECT_SIZE;
break;
default:
info->flash_id = FLASH_UNKNOWN;
@ -241,23 +298,32 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info)
*/
void flash_unprotect_sectors (FPWV * addr)
{
#define PD_FINTEL_WSMS_READY_MASK 0x0080
FPW status;
*addr = (FPW) 0x00500050; /* clear status register */
/* this sends the clear lock bit command */
*addr = (FPW) 0x00600060;
*addr = (FPW) 0x00D000D0;
reset_timer_masked();
while (((status = *addr) & (FPW)0x00800080) != 0x00800080) {
if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
printf("Timeout");
break;
}
}
*addr = (FPW) 0x00FF00FF;
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect;
ulong type, start, last;
ulong type;
int rcode = 0;
if ((s_first < 0) || (s_first > s_last)) {
@ -290,13 +356,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
printf ("\n");
}
start = get_timer (0);
last = start;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
@ -305,36 +364,53 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
printf ("Erasing sector %2d ... ", sect);
flash_unprotect_sectors (addr);
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
/* flash_unprotect_sectors (addr); */
/* arm simple, non interrupt dependent timer */
reset_timer_masked ();
*addr = (FPW) 0x00500050;/* clear status register */
*addr = (FPW) 0x00200020;/* erase setup */
*addr = (FPW) 0x00D000D0;/* erase confirm */
*addr = (FPW) 0x00500050; /* clear status register */
*addr = (FPW) 0x00200020; /* erase setup */
*addr = (FPW) 0x00D000D0; /* erase confirm */
mb();
while (((status =
*addr) & (FPW) 0x00800080) !=
(FPW) 0x00800080) {
if (get_timer_masked () >
CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
/* suspend erase */
*addr = (FPW) 0x00B000B0;
/* reset to read mode */
*addr = (FPW) 0x00FF00FF;
rcode = 1;
break;
udelay(1000); /* Let's wait 1 ms */
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
*addr = (FPW)0x00700070;
status = *addr;
if ((status & (FPW) 0x00400040) == (FPW) 0x00400040) {
/* erase suspended? Resume it */
reset_timer_masked();
*addr = (FPW) 0x00D000D0;
} else {
#ifdef DEBUG
printf ("Timeout,0x%08x\n", status);
#else
printf("Timeout\n");
#endif
*addr = (FPW) 0x00500050;
*addr = (FPW) 0x00FF00FF; /* reset to read mode */
rcode = 1;
break;
}
}
}
/* clear status register cmd. */
*addr = (FPW) 0x00500050;
*addr = (FPW) 0x00FF00FF;/* resest to read mode */
*addr = (FPW) 0x00FF00FF; /* resest to read mode */
printf (" done\n");
}
}
return rcode;
}
@ -345,7 +421,6 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
* 2 - Flash not erased
* 4 - Flash not identified
*/
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
ulong cp, wp;
@ -443,23 +518,39 @@ static int write_data (flash_info_t * info, ulong dest, FPW data)
printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
return (2);
}
flash_unprotect_sectors (addr);
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts ();
/* flash_unprotect_sectors (addr); */
*addr = (FPW) 0x00400040; /* write setup */
*addr = data;
mb();
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* arm simple, non interrupt dependent timer */
reset_timer_masked ();
/* wait while polling the status register */
while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
*addr = (FPW) 0x00FF00FF; /* restore read mode */
#ifdef DEBUG
*addr = (FPW) 0x00700070;
status = *addr;
printf("## status=0x%08x, addr=0x%08x\n", status, addr);
#endif
*addr = (FPW) 0x00500050; /* clear status register cmd */
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (1);
}
}
*addr = (FPW) 0x00FF00FF; /* restore read mode */
*addr = (FPW) 0x00FF00FF; /* restore read mode */
return (0);
}

1
board/omap2420h4/config.mk
View file

@ -20,4 +20,3 @@ TEXT_BASE = 0x80e80000
# This is either with a GP system or a signed boot image.
# easiest, and safest way to go if you can.
#TEXT_BASE = 0x40280000

22
board/omap2420h4/mem.c
View file

@ -74,9 +74,9 @@ void prcm_init(void)
if(running_in_sram()){
/* If running fully from SRAM this is OK. The Flash bus drops out for just a little.
* but then comes back. If running from Flash this sequence kills you, thus you need
* to run it using CONFIG_PARTIAL_SRAM.
*/
* but then comes back. If running from Flash this sequence kills you, thus you need
* to run it using CONFIG_PARTIAL_SRAM.
*/
__raw_writel(MODE_BYPASS_FAST, CM_CLKEN_PLL); /* go to bypass, fast relock */
wait_on_value(BIT0|BIT1, BIT0, CM_IDLEST_CKGEN, LDELAY); /* wait till in bypass */
sdelay(1000);
@ -172,14 +172,13 @@ void do_sdrc_init(u32 offset, u32 early)
cpu = get_cpu_type();
/* warning generated, though code generation is correct. this may bite later,
* but is ok for now. there is only so much C code you can do on stack only
* operation.
* but is ok for now. there is only so much C code you can do on stack only
* operation.
*/
if (cpu == CPU_2422){
sdata = (sdrc_data_t *)&sdrc_2422;
pass_type = STACKED;
}
else{
} else{
sdata = (sdrc_data_t *)&sdrc_2420;
pass_type = IP_DDR;
}
@ -187,10 +186,10 @@ void do_sdrc_init(u32 offset, u32 early)
__asm__ __volatile__("": : :"memory"); /* limit compiler scope */
/* u-boot is compiled to run in DDR or SRAM at 8xxxxxxx or 4xxxxxxx.
* If we are running in flash prior to relocation and we use data
* here which is not pc relative we need to get the address correct.
* We need to find the current flash mapping to dress up the initial
* pointer load. As long as this is const data we should be ok.
* If we are running in flash prior to relocation and we use data
* here which is not pc relative we need to get the address correct.
* We need to find the current flash mapping to dress up the initial
* pointer load. As long as this is const data we should be ok.
*/
if((early) && running_in_flash()){
sdata = (sdrc_data_t *)(((u32)sdata & 0x0003FFFF) | get_gpmc0_base());
@ -344,4 +343,3 @@ void gpmc_init(void)
__raw_writel(H4_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1); /* enable mapping */
sdelay(2000);
}

6
board/omap2420h4/omap2420h4.c
View file

@ -36,7 +36,6 @@
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
#endif
static void wait_for_command_complete(unsigned int wd_base);
/*******************************************************
@ -694,8 +693,6 @@ void muxSetupGPMC(void)
/* signal - Gpmc_ncs2; pin - E2; offset - 0x008C; mode - 0; Byte-2 Pull/up - N/A */
MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2,
*MuxConfigReg = 0x00 ;
}
/****************************************************************
@ -860,6 +857,3 @@ void nand_init(void)
#endif
}
#endif

1
board/omap2420h4/platform.S
View file

@ -183,4 +183,3 @@ VAL_INTH_SETUP:
.word PERIFERAL_PORT_BASE
SRAM_STACK:
.word LOW_LEVEL_SRAM_STACK

3
board/omap2420h4/sys_info.c
View file

@ -251,8 +251,6 @@ static u32 get_base2(void)
return(val);
}
/********************************************************
* running_in_flash() - tell if currently running in
* flash.
@ -302,4 +300,3 @@ u32 running_from_internal_boot(void)
else
return(0);
}

246
examples/README.smc91111_eeprom Normal file
View file

@ -0,0 +1,246 @@
This is the readme for the Das U-Boot standalone program smc91111
The main purpose of this is to manage MAC addresses on platforms
which include the SMC91111 integrated 10/100 MAC Phy, with attached
EEPROMs.
Contents:
------------------------
1. Ensuring U-boot's MAC address can be set in hardware
2. Running the smc91111_eeprom program
3. Setting MAC addresses
4. Other things you can do with this
5. Things to be done.
1. Ensuring U-boot's MAC address can be set in hardware
--------------------------------------------------------------------------
On the Internet - MAC addresses are very important. Short for Media
Access Control address, a hardware address that uniquely identifies
each node of a network. When things are not unique - bad things
can happen. This is why U-Boot makes it difficult to change MAC
addresses.
To find out who has a MAC address, or to purchase MAC addresses, goto
the IEEE, at:
http://standards.ieee.org/regauth/oui/index.shtml
To change your MAC address, there can not be a MAC address predefined in
U-Boot. To ensure that this does not occur, check your
include/configs/<board_name>.h file, and check to see that the following
settings are _not_ or commented out there.
#define HARDCODE_MAC 1
#define CONFIG_ETHADDR 02:80:ad:20:31:b8
The purpose of HARDCODE_MAC is to hardcode the MAC address in software,
(not what we want), or to preset it to 02:80:ad:20:31:b8 (not what we
want either).
You can check this in a running U-Boot, by doing a power cycle, then
before U-Boot tries to do any networking, running the 'printenv' command
BOOT> printenv
ethaddr=02:80:ad:20:31:b8
If you see the 'ethaddr' variable show up, like the above, you need to
recompile U-Boot, with the above settings commented out of the
include/configs/<board_name>.h file.
2. Running the smc91111_eeprom program
---------------------------------------------------------------------
After Uboot is compiled, there should be three files of interest:
-rwxr-xr-x 1 8806 2004-10-11 14:00 smc91111_eeprom <- ELF
-rwxr-xr-x 1 3440 2004-10-11 14:00 smc91111_eeprom.bin <- BIN
-rwxr-xr-x 1 9524 2004-10-11 14:00 smc91111_eeprom.srec <- SREC
if there is not, check the examples/Makefile, and ensure there is something
like for your architecture:
ifeq ($(ARCH),blackfin)
SREC += smc91111_eeprom.srec
BIN += smc91111_eeprom.bin smc91111_eeprom
endif
To load the files: there are two methods: a) serial or b) network. Since
it is not a good idea to start doing things on the network before the
MAC address is set, this example will do things over serial.
a) Loading the elf file via the serial port
--------------------------------------------
Loading the elf is very easy - just ensure that the location
you specify things to load as is not the load address specified
in the Makefile.
BOOT> loadb 0x1000000
## Ready for binary (kermit) download to 0x01000000 at 57600 bps...
(type CNTL-\ then C)
(Back at local machine)
----------------------------------------------------
Kermit>send ~/u-boot_1.1.1/examples/smc91111_eeprom
Kermit>connect
Connecting to /dev/ttyS0, speed 57600
Escape character: Ctrl-\ (ASCII 28, FS): enabled
Type the escape character followed by C to get back,
or followed by ? to see other options.
----------------------------------------------------
## Total Size = 0x00002266 = 8806 Bytes
## Start Addr = 0x01000000
BOOT> bootelf 0x1000000
Loading .text @ 0x00001000 (3440 bytes)
## Starting application at 0x000010d8 ...
SMC91111>
b) Loading the binary file via the serial port
-----------------------------------------------
For many toolchains, the entry point is not the load point.
The Load point is a hard coded address from the
examples/Makefile. The entry point can be found by doing something
like:
u-boot_1.1.1/examples> bfin-elf-objdump -d smc91111_eeprom |less
smc91111_eeprom: file format elf32-bfin
Disassembly of section .text:
00001000 <smc91111_eeprom-0xd8>:
1000:
000010d8 <smc91111_eeprom>:
You can see that the entry point (or the address that should be
jumped to is 0x10d8). This is also the same as the entry point
of the elf file.
Now we load it to the actual load location:
BOOT> loadb 0x1000
## Ready for binary (kermit) download to 0x00001000 at 57600 bps...
(Back at pinky.dsl-only.net)
----------------------------------------------------
Kermit>send /tftpboot/eeprom.bin
Kermit>connect
Connecting to /dev/ttyS0, speed 57600
Escape character: Ctrl-\ (ASCII 28, FS): enabled
Type the escape character followed by C to get back,
or followed by ? to see other options.
----------------------------------------------------
## Total Size = 0x00000d70 = 3440 Bytes
## Start Addr = 0x00001000
BOOT> go 0x10D8
## Starting application at 0x000010D8 ...
SMC91111>
3. Setting MAC addresses
--------------------------------------------------------------------------
The MAC address can be stored in four locations:
-Boot environmental variable in Flash <- can not change, without
re-flashing U-boot.
U-Boot environental variable <- can not change, without
resetting board/U-Boot
LAN91C111 Registers <- volitle
LAN91C111 EEPROM <- Non Volitle
If you have not activated the network, and do not have a hardcoded
or pre-assigned MAC address in U-boot, the environmental variables
should be blank, and allow you to set things one time.
To set the EEPROM MAC address to 12:34:56:78:9A:BC
SMC91111> W E 20 3412
Writing EEPROM register 20 with 3412
SMC91111> W E 21 7856
Writing EEPROM register 21 with 7856
SMC91111> W E 22 BC9A
Writing EEPROM register 22 with bc9a
EEPROM contents copied to MAC
SMC91111> P
Current MAC Address in SMSC91111 12:34:56:78:9a:bc
Current MAC Address in EEPROM 12:34:56:78:9a:bc
(CNTRL-C to exit)
SMC91111> ## Application terminated, rc = 0x0
BOOT> reset
U-Boot 1.1.1 (gcc version: 3.3.3)
Release Version Beta released on Oct 10 2004 - 00:34:35
Blackfin support by LG Soft India
For further information please check this link http://www.blackfin.uclinux.org
BOOT> ping 192.168.0.4
Using MAC Address 12:34:56:78:9A:BC
host 192.168.0.4 is alive
4. Other things that you can do
--------------------------------------------------------------------------
After the stand alone application is running, there are a few options:
- P : Print the MAC
- D : Dump the LAN91C111 EEPROM contents
- M : Dump the LAN91C111 MAC contents
- C : Copies the MAC address from the EEPROM to the LAN91C111
- W : Write a register in the EEPROM or in the MAC
SMC91111> P
Current MAC Address in SMSC91111 12:34:56:78:9a:bc
Current MAC Address in EEPROM 12:34:56:78:9a:bc
SMC91111> D
IOS2-0 000 001 002 003 004 005 006 007
CONFIG 00:ffff 04:ffff 08:ffff 0c:ffff 10:ffff 14:ffff 18:ffff 1c:ffff
BASE 01:ffff 05:ffff 09:ffff 0d:ffff 11:ffff 15:ffff 19:ffff 1d:ffff
02:ffff 06:ffff 0a:ffff 0e:0020 12:ffff 16:ffff 1a:ffff 1e:ffff
03:ffff 07:ffff 0b:ffff 0f:ffff 13:ffff 17:ffff 1b:ffff 1f:ffff
20:3412 21:7856 22:bc9a 23:ffff 24:ffff 25:ffff 26:ffff 27:ffff
28:ffff 29:ffff 2a:ffff 2b:ffff 2c:ffff 2d:ffff 2e:ffff 2f:ffff
30:ffff 31:ffff 32:ffff 33:ffff 34:ffff 35:ffff 36:ffff 37:ffff
38:ffff 39:ffff 3a:ffff 3b:ffff 3c:ffff 3d:ffff 3e:ffff 3f:ffff
SMC91111> M
Bank0 Bank1 Bank2 Bank3
00 0000 a0b1 3332 0000
02 0000 1801 8000 0000
04 0000 3412 8080 0000
06 0000 7856 003f 0000
08 0404 bc9a 02df 3332
0a 0000 ffff 02df 3391
0c 0000 1214 0004 001f
0e 3300 3301 3302 3303
SMC91111> C
EEPROM contents copied to MAC
SMC91111> W E 2A ABCD
Writing EEPROM register 2a with abcd
SMC91111> W M 14 FF00
Writing MAC register bank 1, reg 04 with ff00

391
examples/smc91111_eeprom.c Normal file
View file

@ -0,0 +1,391 @@
/*
* (C) Copyright 2004
* Robin Getz rgetz@blacfin.uclinux.org
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Heavily borrowed from the following peoples GPL'ed software:
* - Wolfgang Denk, DENX Software Engineering, wd@denx.de
* Das U-boot
* - Ladislav Michl ladis@linux-mips.org
* A rejected patch on the U-Boot mailing list
*/
#include <common.h>
#include <exports.h>
#include "../drivers/smc91111.h"
#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
#define EEPROM 0x1;
#define MAC 0x2;
#define UNKNOWN 0x4;
void dump_reg (void);
void dump_eeprom (void);
int write_eeprom_reg (int, int);
void copy_from_eeprom (void);
void print_MAC (void);
int read_eeprom_reg (int);
void print_macaddr (void);
int smc91111_eeprom (int argc, char *argv[])
{
int c, i, j, done, line, reg, value, start, what;
char input[50];
/* Print the ABI version */
app_startup (argv);
if (XF_VERSION != (int) get_version ()) {
printf ("Expects ABI version %d\n", XF_VERSION);
printf ("Actual U-Boot ABI version %d\n",
(int) get_version ());
printf ("Can't run\n\n");
return (0);
}
asm ("p2.h = 0xFFC0;");
asm ("p2.l = 0x0730;");
asm ("r0 = 0x01;");
asm ("w[p2] = r0;");
asm ("ssync;");
asm ("p2.h = 0xffc0;");
asm ("p2.l = 0x0708;");
asm ("r0 = 0x01;");
asm ("w[p2] = r0;");
asm ("ssync;");
if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) {
printf ("Can't find SMSC91111\n");
return (0);
}
done = 0;
what = UNKNOWN;
printf ("\n");
while (!done) {
/* print the prompt */
printf ("SMC91111> ");
line = 0;
i = 0;
start = 1;
while (!line) {
/* Wait for a keystroke */
while (!tstc ());
c = getc ();
/* Make Uppercase */
if (c >= 'Z')
c -= ('a' - 'A');
/* printf(" |%02x| ",c); */
switch (c) {
case '\r': /* Enter */
case '\n':
input[i] = 0;
puts ("\r\n");
line = 1;
break;
case '\0': /* nul */
continue;
case 0x03: /* ^C - break */
input[0] = 0;
i = 0;
line = 1;
done = 1;
break;
case 0x5F:
case 0x08: /* ^H - backspace */
case 0x7F: /* DEL - backspace */
if (i > 0) {
puts ("\b \b");
i--;
}
break;
default:
if (start) {
if ((c == 'W') || (c == 'D')
|| (c == 'M') || (c == 'C')
|| (c == 'P')) {
putc (c);
input[i] = c;
if (i <= 45)
i++;
start = 0;
}
} else {
if ((c >= '0' && c <= '9')
|| (c >= 'A' && c <= 'F')
|| (c == 'E') || (c == 'M')
|| (c == ' ')) {
putc (c);
input[i] = c;
if (i <= 45)
i++;
break;
}
}
break;
}
}
for (; i < 49; i++)
input[i] = 0;
switch (input[0]) {
case ('W'):
/* Line should be w reg value */
i = 0;
reg = 0;
value = 0;
/* Skip to the next space or end) */
while ((input[i] != ' ') && (input[i] != 0))
i++;
if (input[i] != 0)
i++;
/* Are we writing to EEPROM or MAC */
switch (input[i]) {
case ('E'):
what = EEPROM;
break;
case ('M'):
what = MAC;
break;
default:
what = UNKNOWN;
break;
}
/* skip to the next space or end */
while ((input[i] != ' ') && (input[i] != 0))
i++;
if (input[i] != 0)
i++;
/* Find register to write into */
j = 0;
while ((input[i] != ' ') && (input[i] != 0)) {
j = input[i] - 0x30;
if (j >= 0xA) {
j -= 0x07;
}
reg = (reg * 0x10) + j;
i++;
}
while ((input[i] != ' ') && (input[i] != 0))
i++;
if (input[i] != 0)
i++;
else
what = UNKNOWN;
/* Get the value to write */
j = 0;
while ((input[i] != ' ') && (input[i] != 0)) {
j = input[i] - 0x30;
if (j >= 0xA) {
j -= 0x07;
}
value = (value * 0x10) + j;
i++;
}
switch (what) {
case 1:
printf ("Writing EEPROM register %02x with %04x\n",
reg, value);
write_eeprom_reg (value, reg);
break;
case 2:
printf ("Writing MAC register bank %i,
reg %02x with %04x\n", reg >> 4, reg & 0xE, value);
SMC_SELECT_BANK (reg >> 4);
SMC_outw (value, reg & 0xE);
break;
default:
printf ("Wrong\n");
break;
}
break;
case ('D'):
dump_eeprom ();
break;
case ('M'):
dump_reg ();
break;
case ('C'):
copy_from_eeprom ();
break;
case ('P'):
print_macaddr ();
break;
default:
break;
}
}
return (0);
}
void copy_from_eeprom (void)
{
int i;
SMC_SELECT_BANK (1);
SMC_outw ((SMC_inw (CTL_REG) & !CTL_EEPROM_SELECT) | CTL_RELOAD,
CTL_REG);
i = 100;
while ((SMC_inw (CTL_REG) & CTL_RELOAD) && --i)
udelay (100);
if (i == 0) {
printf ("Timeout Refreshing EEPROM registers\n");
} else {
printf ("EEPROM contents copied to MAC\n");
}
}
void print_macaddr (void)
{
int i, j, k, mac[6];
printf ("Current MAC Address in SMSC91111 ");
SMC_SELECT_BANK (1);
for (i = 0; i < 5; i++) {
printf ("%02x:", SMC_inb (ADDR0_REG + i));
}
printf ("%02x\n", SMC_inb (ADDR0_REG + 5));
i = 0;
for (j = 0x20; j < 0x23; j++) {
k = read_eeprom_reg (j);
mac[i] = k & 0xFF;
i++;
mac[i] = k >> 8;
i++;
}
printf ("Current MAC Address in EEPROM ");
for (i = 0; i < 5; i++)
printf ("%02x:", mac[i]);
printf ("%02x\n", mac[5]);
}
void dump_eeprom (void)
{
int j, k;
printf ("IOS2-0 ");
for (j = 0; j < 8; j++) {
printf ("%03x ", j);
}
printf ("\n");
for (k = 0; k < 4; k++) {
if (k == 0)
printf ("CONFIG ");
if (k == 1)
printf ("BASE ");
if ((k == 2) || (k == 3))
printf (" ");
for (j = 0; j < 0x20; j += 4) {
printf ("%02x:%04x ", j + k, read_eeprom_reg (j + k));
}
printf ("\n");
}
for (j = 0x20; j < 0x40; j++) {
if ((j & 0x07) == 0)
printf ("\n");
printf ("%02x:%04x ", j, read_eeprom_reg (j));
}
printf ("\n");
}
int read_eeprom_reg (int reg)
{
int timeout;
SMC_SELECT_BANK (2);
SMC_outw (reg, PTR_REG);
SMC_SELECT_BANK (1);
SMC_outw (SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD,
CTL_REG);
timeout = 100;
while ((SMC_inw (CTL_REG) & CTL_RELOAD) && --timeout)
udelay (100);
if (timeout == 0) {
printf ("Timeout Reading EEPROM register %02x\n", reg);
return 0;
}
return SMC_inw (GP_REG);
}
int write_eeprom_reg (int value, int reg)
{
int timeout;
SMC_SELECT_BANK (2);
SMC_outw (reg, PTR_REG);
SMC_SELECT_BANK (1);
SMC_outw (value, GP_REG);
SMC_outw (SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG);
timeout = 100;
while ((SMC_inw (CTL_REG) & CTL_STORE) && --timeout)
udelay (100);
if (timeout == 0) {
printf ("Timeout Writing EEPROM register %02x\n", reg);
return 0;
}
return 1;
}
void dump_reg (void)
{
int i, j;
printf (" ");
for (j = 0; j < 4; j++) {
printf ("Bank%i ", j);
}
printf ("\n");
for (i = 0; i < 0xF; i += 2) {
printf ("%02x ", i);
for (j = 0; j < 4; j++) {
SMC_SELECT_BANK (j);
printf ("%04x ", SMC_inw (i));
}
printf ("\n");
}
}

49
include/configs/integratorcp.h
View file

@ -35,7 +35,11 @@
* High Level Configuration Options
* (easy to change)
*/
#if 1
#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
#else
#define CONFIG_ARM946ES 1 /* This is an arm946es CPU core */
#endif
#define CONFIG_INTEGRATOR 1 /* in an Integrator board */
#define CONFIG_ARCH_CINTEGRATOR 1 /* Specifically, a CP */
@ -51,7 +55,7 @@
/*
* Size of malloc() pool
*/
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
/*
@ -69,31 +73,39 @@
#define CONFIG_PL011_CLOCK 14745600
#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 }
#define CONFIG_CONS_INDEX 0
#define CONFIG_BAUDRATE 38400
#define CONFIG_BAUDRATE 38400
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CFG_SERIAL0 0x16000000
#define CFG_SERIAL1 0x17000000
#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_MEMORY)
#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
/*
#define CONFIG_COMMANDS (CFG_CMD_DFL | CFG_CMD_PCI)
*/
#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | \
CFG_CMD_BDI | CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_ENV \
)
/* #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#if 0
#define CONFIG_BOOTDELAY 2
#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0"
#define CONFIG_BOOTCOMMAND "bootp ; bootm"
#endif
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "Integrator-CP # " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CFG_LOAD_ADDR 0x7fc0 /* default load address */
@ -112,23 +124,24 @@
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
#define CFG_FLASH_BASE 0x24000000
#define PHYS_FLASH_1 (CFG_FLASH_BASE)
#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CFG_ENV_IS_NOWHERE
#define CFG_FLASH_BASE 0x24000000
#define CFG_MAX_FLASH_SECT 64
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */
/* timeout values are in ticks */
#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */
#define CFG_MAX_FLASH_SECT 128
#define CFG_ENV_SIZE 32768
#endif /* __CONFIG_H */
#define CFG_MONITOR_BASE 0x24F40000
#define CFG_ENV_IS_IN_FLASH
#define CFG_ENV_ADDR 0x24F00000
#define CFG_ENV_SECT_SIZE 0x40000 /* 256KB */
#define CFG_ENV_SIZE 8192 /* 8KB */
#endif /* __CONFIG_H */

6
include/configs/omap2420h4.h
View file

@ -40,17 +40,17 @@
/* Clock config to target*/
#define PRCM_CONFIG_II 1
//#define PRCM_CONFIG_III 1
/*#define PRCM_CONFIG_III 1 */
/* Memory configuration on board */
//#define CONFIG_OPTIMIZE_DDR 1
/*#define CONFIG_OPTIMIZE_DDR 1 */
#include <asm/arch/omap2420.h> /* get chip and board defs */
/* On H4, NOR and NAND flash are mutual exclusive.
Define this if you want to use NAND
*/
//#define CFG_NAND_BOOT
/*#define CFG_NAND_BOOT */
#ifdef CONFIG_APTIX
#define V_SCLK 1500000