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ppc4xx: Fix incorrect 33/66MHz PCI clock log-message on Sequoia & Yosemite
The BCSR status bit for the 66MHz PCI operation was correctly addressed (MSB/LSB problem). Now the correct currently setup PCI frequency is displayed upon bootup. This patch also fixes this problem on Rainier & Yellowstone, since these boards use the same souce code as Sequoia & Yosemite do. Signed-off-by: Stefan Roese <sr@denx.de>
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4 changed files with 13 additions and 5 deletions
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@ -1,5 +1,5 @@
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/*
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/*
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* (C) Copyright 2006
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* (C) Copyright 2006-2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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*
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* (C) Copyright 2006
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* (C) Copyright 2006
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@ -24,6 +24,7 @@
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#include <common.h>
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <ppc440.h>
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#include <ppc440.h>
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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@ -362,8 +363,8 @@ int checkboard(void)
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printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
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printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
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#endif
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#endif
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rev = in8(CFG_BCSR_BASE + 0);
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rev = in_8((void *)(CFG_BCSR_BASE + 0));
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val = in8(CFG_BCSR_BASE + 5) & 0x01;
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val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
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printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
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printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
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if (s != NULL) {
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if (s != NULL) {
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@ -1,4 +1,6 @@
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/*
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/*
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* (C) Copyright 2006-2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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*
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* See file CREDITS for list of people who contributed to this
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* See file CREDITS for list of people who contributed to this
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* project.
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* project.
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@ -22,6 +24,7 @@
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#include <common.h>
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#include <common.h>
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#include <ppc4xx.h>
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#include <ppc4xx.h>
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#include <asm/processor.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <spd_sdram.h>
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#include <spd_sdram.h>
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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@ -181,8 +184,8 @@ int checkboard(void)
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printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
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printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
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#endif
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#endif
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rev = *(u8 *)(CFG_CPLD + 0);
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rev = in_8((void *)(CFG_BCSR_BASE + 0));
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val = *(u8 *)(CFG_CPLD + 5) & 0x01;
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val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
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printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
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printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
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if (s != NULL) {
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if (s != NULL) {
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@ -450,6 +450,8 @@
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#define CFG_EBC_PB2AP 0x24814580
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#define CFG_EBC_PB2AP 0x24814580
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#define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x38000)
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#define CFG_EBC_PB2CR (CFG_BCSR_BASE | 0x38000)
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#define CFG_BCSR5_PCI66EN 0x80
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/*-----------------------------------------------------------------------
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/*-----------------------------------------------------------------------
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* NAND FLASH
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* NAND FLASH
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*----------------------------------------------------------------------*/
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*----------------------------------------------------------------------*/
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@ -359,6 +359,8 @@
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#define CFG_EBC_PB2AP 0x04814500
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#define CFG_EBC_PB2AP 0x04814500
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#define CFG_EBC_PB2CR (CFG_CPLD | 0x18000)
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#define CFG_EBC_PB2CR (CFG_CPLD | 0x18000)
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#define CFG_BCSR5_PCI66EN 0x80
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/*-----------------------------------------------------------------------
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/*-----------------------------------------------------------------------
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* Cache Configuration
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* Cache Configuration
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*/
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*/
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