From 59f0978a7e78d20277ddbde7caf0ea877f3cfd98 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sat, 7 Feb 2009 05:43:21 -0500 Subject: [PATCH] Blackfin: fix SIC_RVECT definition: it is 16bits, not 32bits Signed-off-by: Mike Frysinger --- .../asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h | 6 +++--- .../asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/include/asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h b/include/asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h index dec7c63bad..f65b439c17 100644 --- a/include/asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h +++ b/include/asm-blackfin/mach-bf527/ADSP-EDN-BF52x-extended_cdef.h @@ -6,9 +6,9 @@ #ifndef __BFIN_CDEF_ADSP_EDN_BF52x_extended__ #define __BFIN_CDEF_ADSP_EDN_BF52x_extended__ -#define pSIC_RVECT ((uint32_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */ -#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT) -#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) +#define pSIC_RVECT ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */ +#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT) +#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val) #define pSIC_IMASK0 ((uint32_t volatile *)SIC_IMASK0) /* Interrupt Mask Register */ #define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0) #define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val) diff --git a/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h b/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h index 58df301617..07008755f0 100644 --- a/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h +++ b/include/asm-blackfin/mach-bf537/ADSP-EDN-BF534-extended_cdef.h @@ -27,9 +27,9 @@ #define pSYSCR ((uint16_t volatile *)SYSCR) /* System Configuration Register */ #define bfin_read_SYSCR() bfin_read16(SYSCR) #define bfin_write_SYSCR(val) bfin_write16(SYSCR, val) -#define pSIC_RVECT ((uint32_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */ -#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT) -#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val) +#define pSIC_RVECT ((uint16_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */ +#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT) +#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val) #define pSIC_IMASK ((uint32_t volatile *)SIC_IMASK) /* Interrupt Mask Register */ #define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK) #define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val)