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ColdFire: Queued SPI driver

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This patch adds a driver for Freescale Colfire Queued SPI bus.
Coded to work with 8 bits per transfer to use with SPI flash.
CPOL, CPHA, and CS_ACTIVE_HIGH can be configured.

Tested with MCF5270 which have 4 chip selects.

Activate by #define CONFIG_CF_QSPI in board config.

Signed-off-by: Richard Retanubun <richardretanubun@ruggedcom.com>
This commit is contained in:
Richard Retanubun 2011-03-24 08:58:11 +00:00 committed by jason
parent 198cafbf2c
commit 59d0612252
5 changed files with 415 additions and 2 deletions
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15
arch/m68k/cpu/mcf52x2/cpu_init.c
View file

@ -333,7 +333,20 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
return 0;
}
#endif /* CONFIG_CMD_NET */
#endif
#if defined(CONFIG_CF_QSPI)
/* Configure PIOs for SIN, SOUT, and SCK */
void cfspi_port_conf(void)
{
mbar_writeByte(MCF_GPIO_PAR_QSPI,
MCF_GPIO_PAR_QSPI_SIN_SIN |
MCF_GPIO_PAR_QSPI_SOUT_SOUT |
MCF_GPIO_PAR_QSPI_SCK_SCK);
}
#endif /* CONFIG_CF_QSPI */
#endif /* CONFIG_M5271 */
#if defined(CONFIG_M5272)
/*

2
arch/m68k/include/asm/coldfire/qspi.h
View file

@ -98,7 +98,7 @@ typedef struct qspi_ctrl {
#define QSPI_QAR_RECV (0x0010)
#define QSPI_QAR_CMD (0x0020)
/* DR */
/* DR with RAM command word definitions */
#define QSPI_QDR_CONT (0x8000)
#define QSPI_QDR_BITSE (0x4000)
#define QSPI_QDR_DT (0x2000)

26
arch/m68k/include/asm/m5271.h
View file

@ -171,6 +171,32 @@
#define MCF_GPIO_PAR_UART_U1RXD_UART1 0x0C00
#define MCF_GPIO_PAR_UART_U1TXD_UART1 0x0300
/* Bit definitions and macros for PAR_QSPI */
#define MCF_GPIO_PAR_QSPI_PCS1_UNMASK 0x3F
#define MCF_GPIO_PAR_QSPI_PCS1_PCS1 0xC0
#define MCF_GPIO_PAR_QSPI_PCS1_SDRAM_SCKE 0x80
#define MCF_GPIO_PAR_QSPI_PCS1_GPIO 0x00
#define MCF_GPIO_PAR_QSPI_PCS0_UNMASK 0xDF
#define MCF_GPIO_PAR_QSPI_PCS0_PCS0 0x20
#define MCF_GPIO_PAR_QSPI_PCS0_GPIO 0x00
#define MCF_GPIO_PAR_QSPI_SIN_UNMASK 0xE7
#define MCF_GPIO_PAR_QSPI_SIN_SIN 0x18
#define MCF_GPIO_PAR_QSPI_SIN_I2C_SDA 0x10
#define MCF_GPIO_PAR_QSPI_SIN_GPIO 0x00
#define MCF_GPIO_PAR_QSPI_SOUT_UNMASK 0xFB
#define MCF_GPIO_PAR_QSPI_SOUT_SOUT 0x04
#define MCF_GPIO_PAR_QSPI_SOUT_GPIO 0x00
#define MCF_GPIO_PAR_QSPI_SCK_UNMASK 0xFC
#define MCF_GPIO_PAR_QSPI_SCK_SCK 0x03
#define MCF_GPIO_PAR_QSPI_SCK_I2C_SCL 0x02
#define MCF_GPIO_PAR_QSPI_SCK_GPIO 0x00
/* Bit definitions and macros for PAR_TIMER for QSPI */
#define MCF_GPIO_PAR_TIMER_T3IN_UNMASK 0x3FFF
#define MCF_GPIO_PAR_TIMER_T3IN_QSPI_PCS2 0x4000
#define MCF_GPIO_PAR_TIMER_T3OUT_UNMASK 0xFF3F
#define MCF_GPIO_PAR_TIMER_T3OUT_QSPI_PCS3 0x0040
#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6)
#define MCF_SDRAMC_DCR 0x000040

1
drivers/spi/Makefile
View file

@ -32,6 +32,7 @@ COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o
COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o
COBJS-$(CONFIG_CF_SPI) += cf_spi.o
COBJS-$(CONFIG_CF_QSPI) += cf_qspi.o
COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o

373
drivers/spi/cf_qspi.c Normal file
View file

@ -0,0 +1,373 @@
/*
* Freescale Coldfire Queued SPI driver
*
* NOTE:
* This driver is written to transfer 8 bit at-a-time and uses the dedicated
* SPI slave select pins as bit-banged GPIO to work with spi_flash subsystem.
*
*
* Copyright (C) 2011 Ruggedcom, Inc.
* Richard Retanubun (richardretanubun@freescale.com)
*
* See file CREDITS for list of people who contributed to this project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <malloc.h>
#include <spi.h>
#include <asm/immap.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
#define clamp(x, low, high) (min(max(low, x), high))
#define to_cf_qspi_slave(s) container_of(s, struct cf_qspi_slave, s)
struct cf_qspi_slave {
struct spi_slave slave; /* Specific bus:cs ID for each device */
qspi_t *regs; /* Pointer to SPI controller registers */
u16 qmr; /* QMR: Queued Mode Register */
u16 qwr; /* QWR: Queued Wrap Register */
u16 qcr; /* QCR: Queued Command Ram */
};
/* Register write wrapper functions */
static void write_qmr(volatile qspi_t *qspi, u16 val) { qspi->mr = val; }
static void write_qdlyr(volatile qspi_t *qspi, u16 val) { qspi->dlyr = val; }
static void write_qwr(volatile qspi_t *qspi, u16 val) { qspi->wr = val; }
static void write_qir(volatile qspi_t *qspi, u16 val) { qspi->ir = val; }
static void write_qar(volatile qspi_t *qspi, u16 val) { qspi->ar = val; }
static void write_qdr(volatile qspi_t *qspi, u16 val) { qspi->dr = val; }
/* Register read wrapper functions */
static u16 read_qdlyr(volatile qspi_t *qspi) { return qspi->dlyr; }
static u16 read_qwr(volatile qspi_t *qspi) { return qspi->wr; }
static u16 read_qir(volatile qspi_t *qspi) { return qspi->ir; }
static u16 read_qdr(volatile qspi_t *qspi) { return qspi->dr; }
/* These call points may be different for each ColdFire CPU */
extern void cfspi_port_conf(void);
static void cfspi_cs_activate(uint bus, uint cs, uint cs_active_high);
static void cfspi_cs_deactivate(uint bus, uint cs, uint cs_active_high);
int spi_claim_bus(struct spi_slave *slave)
{
return 0;
}
void spi_release_bus(struct spi_slave *slave)
{
}
__attribute__((weak))
void spi_init(void)
{
cfspi_port_conf();
}
__attribute__((weak))
void spi_cs_activate(struct spi_slave *slave)
{
struct cf_qspi_slave *dev = to_cf_qspi_slave(slave);
cfspi_cs_activate(slave->bus, slave->cs, !(dev->qwr & QSPI_QWR_CSIV));
}
__attribute__((weak))
void spi_cs_deactivate(struct spi_slave *slave)
{
struct cf_qspi_slave *dev = to_cf_qspi_slave(slave);
cfspi_cs_deactivate(slave->bus, slave->cs, !(dev->qwr & QSPI_QWR_CSIV));
}
__attribute__((weak))
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
/* Only 1 bus and 4 chipselect per controller */
if (bus == 0 && (cs >= 0 && cs < 4))
return 1;
else
return 0;
}
void spi_free_slave(struct spi_slave *slave)
{
struct cf_qspi_slave *dev = to_cf_qspi_slave(slave);
free(dev);
}
/* Translate information given by spi_setup_slave to members of cf_qspi_slave */
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct cf_qspi_slave *dev = NULL;
if (!spi_cs_is_valid(bus, cs))
return NULL;
dev = malloc(sizeof(struct cf_qspi_slave));
if (!dev)
return NULL;
/* Initialize to known value */
dev->slave.bus = bus;
dev->slave.cs = cs;
dev->regs = (qspi_t *)MMAP_QSPI;
dev->qmr = 0;
dev->qwr = 0;
dev->qcr = 0;
/* Map max_hz to QMR[BAUD] */
if (max_hz == 0) /* Go as fast as possible */
dev->qmr = 2u;
else /* Get the closest baud rate */
dev->qmr = clamp(((gd->bus_clk >> 2) + max_hz - 1)/max_hz,
2u, 255u);
/* Map mode to QMR[CPOL] and QMR[CPHA] */
if (mode & SPI_CPOL)
dev->qmr |= QSPI_QMR_CPOL;
if (mode & SPI_CPHA)
dev->qmr |= QSPI_QMR_CPHA;
/* Hardcode bit length to 8 bit per transter */
dev->qmr |= QSPI_QMR_BITS_8;
/* Set QMR[MSTR] to enable QSPI as master */
dev->qmr |= QSPI_QMR_MSTR;
/*
* Set QCR and QWR to default values for spi flash operation.
* If more custom QCR and QRW are needed, overload mode variable
*/
dev->qcr = (QSPI_QDR_CONT | QSPI_QDR_BITSE);
if (!(mode & SPI_CS_HIGH))
dev->qwr |= QSPI_QWR_CSIV;
return &dev->slave;
}
/* Transfer 8 bit at a time */
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
{
struct cf_qspi_slave *dev = to_cf_qspi_slave(slave);
volatile qspi_t *qspi = dev->regs;
u8 *txbuf = (u8 *)dout;
u8 *rxbuf = (u8 *)din;
u32 count = ((bitlen / 8) + (bitlen % 8 ? 1 : 0));
u32 n, i = 0;
/* Sanitize arguments */
if (slave == NULL) {
printf("%s: NULL slave ptr\n", __func__);
return -1;
}
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(slave);
/* There is something to send, lets process it. spi_xfer is also called
* just to toggle chip select, so bitlen of 0 is valid */
if (count > 0) {
/*
* NOTE: Since chip select is driven as a bit-bang-ed GPIO
* using spi_cs_activate() and spi_cs_deactivate(),
* the chip select settings inside the controller
* (i.e. QCR[CONT] and QWR[CSIV]) are moot. The bits are set to
* keep the controller settings consistent with the actual
* operation of the bus.
*/
/* Write the slave device's settings for the controller.*/
write_qmr(qspi, dev->qmr);
write_qwr(qspi, dev->qwr);
/* Limit transfer to 16 at a time */
n = min(count, 16u);
do {
/* Setup queue end point */
write_qwr(qspi, ((read_qwr(qspi) & QSPI_QWR_ENDQP_MASK)
| QSPI_QWR_ENDQP((n-1))));
/* Write Command RAM */
write_qar(qspi, QSPI_QAR_CMD);
for (i = 0; i < n; ++i)
write_qdr(qspi, dev->qcr);
/* Write TxBuf, if none given, fill with ZEROes */
write_qar(qspi, QSPI_QAR_TRANS);
if (txbuf) {
for (i = 0; i < n; ++i)
write_qdr(qspi, *txbuf++);
} else {
for (i = 0; i < n; ++i)
write_qdr(qspi, 0);
}
/* Clear QIR[SPIF] by writing a 1 to it */
write_qir(qspi, read_qir(qspi) | QSPI_QIR_SPIF);
/* Set QDLYR[SPE] to start sending */
write_qdlyr(qspi, read_qdlyr(qspi) | QSPI_QDLYR_SPE);
/* Poll QIR[SPIF] for transfer completion */
while ((read_qir(qspi) & QSPI_QIR_SPIF) != 1)
udelay(1);
/* If given read RxBuf, load data to it */
if (rxbuf) {
write_qar(qspi, QSPI_QAR_RECV);
for (i = 0; i < n; ++i)
*rxbuf++ = read_qdr(qspi);
}
/* Decrement count */
count -= n;
} while (count);
}
if (flags & SPI_XFER_END)
spi_cs_deactivate(slave);
return 0;
}
/* Each MCF CPU may have different pin assignments for chip selects. */
#if defined(CONFIG_M5271)
/* Assert chip select, val = [1|0] , dir = out, mode = GPIO */
void cfspi_cs_activate(uint bus, uint cs, uint cs_active_high)
{
debug("%s: bus %d cs %d cs_active_high %d\n",
__func__, bus, cs, cs_active_high);
switch (cs) {
case 0: /* QSPI_CS[0] = PQSPI[3] */
if (cs_active_high)
mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x08);
else
mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xF7);
mbar_writeByte(MCF_GPIO_PDDR_QSPI,
mbar_readByte(MCF_GPIO_PDDR_QSPI) | 0x08);
mbar_writeByte(MCF_GPIO_PAR_QSPI,
mbar_readByte(MCF_GPIO_PAR_QSPI) & 0xDF);
break;
case 1: /* QSPI_CS[1] = PQSPI[4] */
if (cs_active_high)
mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x10);
else
mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xEF);
mbar_writeByte(MCF_GPIO_PDDR_QSPI,
mbar_readByte(MCF_GPIO_PDDR_QSPI) | 0x10);
mbar_writeByte(MCF_GPIO_PAR_QSPI,
mbar_readByte(MCF_GPIO_PAR_QSPI) & 0x3F);
break;
case 2: /* QSPI_CS[2] = PTIMER[7] */
if (cs_active_high)
mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x80);
else
mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0x7F);
mbar_writeByte(MCF_GPIO_PDDR_TIMER,
mbar_readByte(MCF_GPIO_PDDR_TIMER) | 0x80);
mbar_writeShort(MCF_GPIO_PAR_TIMER,
mbar_readShort(MCF_GPIO_PAR_TIMER) & 0x3FFF);
break;
case 3: /* QSPI_CS[3] = PTIMER[3] */
if (cs_active_high)
mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x08);
else
mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0xF7);
mbar_writeByte(MCF_GPIO_PDDR_TIMER,
mbar_readByte(MCF_GPIO_PDDR_TIMER) | 0x08);
mbar_writeShort(MCF_GPIO_PAR_TIMER,
mbar_readShort(MCF_GPIO_PAR_TIMER) & 0xFF3F);
break;
}
}
/* Deassert chip select, val = [1|0], dir = in, mode = GPIO
* direction set as IN to undrive the pin, external pullup/pulldown will bring
* bus to deassert state.
*/
void cfspi_cs_deactivate(uint bus, uint cs, uint cs_active_high)
{
debug("%s: bus %d cs %d cs_active_high %d\n",
__func__, bus, cs, cs_active_high);
switch (cs) {
case 0: /* QSPI_CS[0] = PQSPI[3] */
if (cs_active_high)
mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xF7);
else
mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x08);
mbar_writeByte(MCF_GPIO_PDDR_QSPI,
mbar_readByte(MCF_GPIO_PDDR_QSPI) & 0xF7);
mbar_writeByte(MCF_GPIO_PAR_QSPI,
mbar_readByte(MCF_GPIO_PAR_QSPI) & 0xDF);
break;
case 1: /* QSPI_CS[1] = PQSPI[4] */
if (cs_active_high)
mbar_writeByte(MCF_GPIO_PCLRR_QSPI, 0xEF);
else
mbar_writeByte(MCF_GPIO_PPDSDR_QSPI, 0x10);
mbar_writeByte(MCF_GPIO_PDDR_QSPI,
mbar_readByte(MCF_GPIO_PDDR_QSPI) & 0xEF);
mbar_writeByte(MCF_GPIO_PAR_QSPI,
mbar_readByte(MCF_GPIO_PAR_QSPI) & 0x3F);
break;
case 2: /* QSPI_CS[2] = PTIMER[7] */
if (cs_active_high)
mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0x7F);
else
mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x80);
mbar_writeByte(MCF_GPIO_PDDR_TIMER,
mbar_readByte(MCF_GPIO_PDDR_TIMER) & 0x7F);
mbar_writeShort(MCF_GPIO_PAR_TIMER,
mbar_readShort(MCF_GPIO_PAR_TIMER) & 0x3FFF);
break;
case 3: /* QSPI_CS[3] = PTIMER[3] */
if (cs_active_high)
mbar_writeByte(MCF_GPIO_PCLRR_TIMER, 0xF7);
else
mbar_writeByte(MCF_GPIO_PPDSDR_TIMER, 0x08);
mbar_writeByte(MCF_GPIO_PDDR_TIMER,
mbar_readByte(MCF_GPIO_PDDR_TIMER) & 0xF7);
mbar_writeShort(MCF_GPIO_PAR_TIMER,
mbar_readShort(MCF_GPIO_PAR_TIMER) & 0xFF3F);
break;
}
}
#endif /* CONFIG_M5271 */