mirror of
https://github.com/AsahiLinux/u-boot
synced 2025-03-16 23:07:00 +00:00
Merge branch 'next' of git://git.denx.de/u-boot-nand-flash into next
This commit is contained in:
commit
5928da0193
10 changed files with 1538 additions and 12 deletions
|
@ -38,8 +38,11 @@ COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
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|||
COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
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COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
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COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
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COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o
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COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
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COBJS-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
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COBJS-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
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COBJS-$(CONFIG_NAND_MXC) += mxc_nand.o
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COBJS-$(CONFIG_NAND_NDFC) += ndfc.o
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COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
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COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o
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|
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@ -47,6 +47,16 @@
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#include <asm/arch/nand_defs.h>
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#include <asm/arch/emif_defs.h>
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/* Definitions for 4-bit hardware ECC */
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#define NAND_TIMEOUT 10240
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#define NAND_ECC_BUSY 0xC
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#define NAND_4BITECC_MASK 0x03FF03FF
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#define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
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#define ECC_STATE_NO_ERR 0x0
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#define ECC_STATE_TOO_MANY_ERRS 0x1
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#define ECC_STATE_ERR_CORR_COMP_P 0x2
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#define ECC_STATE_ERR_CORR_COMP_N 0x3
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static emif_registers *const emif_regs = (void *) DAVINCI_ASYNC_EMIF_CNTRL_BASE;
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static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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@ -170,6 +180,268 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *
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}
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#endif /* CONFIG_SYS_NAND_HW_ECC */
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#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
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static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
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/*
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* TI uses a different layout for 4K page deviecs. Since the
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* eccpos filed can hold only a limited number of entries, adding
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* support for 4K page will result in compilation warnings
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* 4K Support will be added later
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*/
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#ifdef CONFIG_SYS_NAND_PAGE_2K
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.eccbytes = 40,
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.eccpos = {
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24, 25, 26, 27, 28,
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29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
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39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
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49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
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59, 60, 61, 62, 63,
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},
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.oobfree = {
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{.offset = 2, .length = 22, },
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},
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#endif
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};
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#endif
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static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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u32 val;
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switch (mode) {
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case NAND_ECC_WRITE:
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case NAND_ECC_READ:
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/*
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* Start a new ECC calculation for reading or writing 512 bytes
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* of data.
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*/
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val = (emif_regs->NANDFCR & ~(3 << 4)) | (1 << 12);
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emif_regs->NANDFCR = val;
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break;
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case NAND_ECC_READSYN:
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val = emif_regs->NAND4BITECC1;
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break;
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default:
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break;
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}
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}
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static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
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{
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ecc[0] = emif_regs->NAND4BITECC1 & NAND_4BITECC_MASK;
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ecc[1] = emif_regs->NAND4BITECC2 & NAND_4BITECC_MASK;
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ecc[2] = emif_regs->NAND4BITECC3 & NAND_4BITECC_MASK;
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ecc[3] = emif_regs->NAND4BITECC4 & NAND_4BITECC_MASK;
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return 0;
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}
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static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
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const uint8_t *dat,
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uint8_t *ecc_code)
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{
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unsigned int hw_4ecc[4] = { 0, 0, 0, 0 };
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unsigned int const1 = 0, const2 = 0;
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unsigned char count1 = 0;
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nand_davinci_4bit_readecc(mtd, hw_4ecc);
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/*Convert 10 bit ecc value to 8 bit */
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for (count1 = 0; count1 < 2; count1++) {
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const2 = count1 * 5;
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const1 = count1 * 2;
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/* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
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ecc_code[const2] = hw_4ecc[const1] & 0xFF;
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/*
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* Take 2 bits as LSB bits from val1 (count1=0) or val5
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* (count1=1) and 6 bits from val2 (count1=0) or
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* val5 (count1=1)
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*/
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ecc_code[const2 + 1] =
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((hw_4ecc[const1] >> 8) & 0x3) | ((hw_4ecc[const1] >> 14) &
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0xFC);
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/*
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* Take 4 bits from val2 (count1=0) or val5 (count1=1) and
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* 4 bits from val3 (count1=0) or val6 (count1=1)
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*/
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ecc_code[const2 + 2] =
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((hw_4ecc[const1] >> 22) & 0xF) |
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((hw_4ecc[const1 + 1] << 4) & 0xF0);
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/*
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* Take 6 bits from val3(count1=0) or val6 (count1=1) and
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* 2 bits from val4 (count1=0) or val7 (count1=1)
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*/
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ecc_code[const2 + 3] =
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((hw_4ecc[const1 + 1] >> 4) & 0x3F) |
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((hw_4ecc[const1 + 1] >> 10) & 0xC0);
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/* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
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ecc_code[const2 + 4] = (hw_4ecc[const1 + 1] >> 18) & 0xFF;
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}
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return 0;
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}
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static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
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uint8_t *read_ecc, uint8_t *calc_ecc)
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{
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struct nand_chip *this = mtd->priv;
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unsigned short ecc_10bit[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
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int i;
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unsigned int hw_4ecc[4] = { 0, 0, 0, 0 }, iserror = 0;
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unsigned short *pspare = NULL, *pspare1 = NULL;
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unsigned int numerrors, erroraddress, errorvalue;
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u32 val;
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/*
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* Check for an ECC where all bytes are 0xFF. If this is the case, we
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* will assume we are looking at an erased page and we should ignore
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* the ECC.
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*/
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for (i = 0; i < 10; i++) {
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if (read_ecc[i] != 0xFF)
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break;
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}
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if (i == 10)
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return 0;
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/* Convert 8 bit in to 10 bit */
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pspare = (unsigned short *)&read_ecc[2];
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pspare1 = (unsigned short *)&read_ecc[0];
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/* Take 10 bits from 0th and 1st bytes */
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ecc_10bit[0] = (*pspare1) & 0x3FF;
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/* Take 6 bits from 1st byte and 4 bits from 2nd byte */
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ecc_10bit[1] = (((*pspare1) >> 10) & 0x3F)
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| (((pspare[0]) << 6) & 0x3C0);
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/* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
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ecc_10bit[2] = ((pspare[0]) >> 4) & 0x3FF;
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/*Take 2 bits from 3rd byte and 8 bits from 4th byte */
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ecc_10bit[3] = (((pspare[0]) >> 14) & 0x3)
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| ((((pspare[1])) << 2) & 0x3FC);
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/* Take 8 bits from 5th byte and 2 bits from 6th byte */
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ecc_10bit[4] = ((pspare[1]) >> 8)
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| ((((pspare[2])) << 8) & 0x300);
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/* Take 6 bits from 6th byte and 4 bits from 7th byte */
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ecc_10bit[5] = (pspare[2] >> 2) & 0x3FF;
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/* Take 4 bits from 7th byte and 6 bits from 8th byte */
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ecc_10bit[6] = (((pspare[2]) >> 12) & 0xF)
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| ((((pspare[3])) << 4) & 0x3F0);
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/*Take 2 bits from 8th byte and 8 bits from 9th byte */
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ecc_10bit[7] = ((pspare[3]) >> 6) & 0x3FF;
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/*
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* Write the parity values in the NAND Flash 4-bit ECC Load register.
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* Write each parity value one at a time starting from 4bit_ecc_val8
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* to 4bit_ecc_val1.
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*/
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for (i = 7; i >= 0; i--)
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emif_regs->NAND4BITECCLOAD = ecc_10bit[i];
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/*
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* Perform a dummy read to the EMIF Revision Code and Status register.
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* This is required to ensure time for syndrome calculation after
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* writing the ECC values in previous step.
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*/
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val = emif_regs->NANDFSR;
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/*
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* Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
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* A syndrome value of 0 means no bit errors. If the syndrome is
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* non-zero then go further otherwise return.
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*/
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nand_davinci_4bit_readecc(mtd, hw_4ecc);
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if (hw_4ecc[0] == ECC_STATE_NO_ERR && hw_4ecc[1] == ECC_STATE_NO_ERR &&
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hw_4ecc[2] == ECC_STATE_NO_ERR && hw_4ecc[3] == ECC_STATE_NO_ERR)
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return 0;
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/*
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* Clear any previous address calculation by doing a dummy read of an
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* error address register.
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*/
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val = emif_regs->NANDERRADD1;
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/*
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* Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
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* register to 1.
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*/
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emif_regs->NANDFCR |= 1 << 13;
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/*
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* Wait for the corr_state field (bits 8 to 11)in the
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* NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
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*/
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i = NAND_TIMEOUT;
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do {
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val = emif_regs->NANDFSR;
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val &= 0xc00;
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i--;
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} while ((i > 0) && val);
|
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iserror = emif_regs->NANDFSR;
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iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
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iserror = iserror >> 8;
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/*
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* ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
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* corrected (five or more errors). The number of errors
|
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* calculated (err_num field) differs from the number of errors
|
||||
* searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error
|
||||
* correction complete (errors on bit 8 or 9).
|
||||
* ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
|
||||
* complete (error exists).
|
||||
*/
|
||||
|
||||
if (iserror == ECC_STATE_NO_ERR) {
|
||||
val = emif_regs->NANDERRVAL1;
|
||||
return 0;
|
||||
} else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
|
||||
val = emif_regs->NANDERRVAL1;
|
||||
return -1;
|
||||
}
|
||||
|
||||
numerrors = ((emif_regs->NANDFSR >> 16) & 0x3) + 1;
|
||||
|
||||
/* Read the error address, error value and correct */
|
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for (i = 0; i < numerrors; i++) {
|
||||
if (i > 1) {
|
||||
erroraddress =
|
||||
((emif_regs->NANDERRADD2 >>
|
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(16 * (i & 1))) & 0x3FF);
|
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erroraddress = ((512 + 7) - erroraddress);
|
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errorvalue =
|
||||
((emif_regs->NANDERRVAL2 >>
|
||||
(16 * (i & 1))) & 0xFF);
|
||||
} else {
|
||||
erroraddress =
|
||||
((emif_regs->NANDERRADD1 >>
|
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(16 * (i & 1))) & 0x3FF);
|
||||
erroraddress = ((512 + 7) - erroraddress);
|
||||
errorvalue =
|
||||
((emif_regs->NANDERRVAL1 >>
|
||||
(16 * (i & 1))) & 0xFF);
|
||||
}
|
||||
/* xor the corrupt data with error value */
|
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if (erroraddress < 512)
|
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dat[erroraddress] ^= errorvalue;
|
||||
}
|
||||
|
||||
return numerrors;
|
||||
}
|
||||
|
||||
static int nand_davinci_dev_ready(struct mtd_info *mtd)
|
||||
{
|
||||
return emif_regs->NANDFSR & 0x1;
|
||||
|
@ -215,7 +487,7 @@ void davinci_nand_init(struct nand_chip *nand)
|
|||
{
|
||||
nand->chip_delay = 0;
|
||||
#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
|
||||
nand->options = NAND_USE_FLASH_BBT;
|
||||
nand->options |= NAND_USE_FLASH_BBT;
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_NAND_HW_ECC
|
||||
nand->ecc.mode = NAND_ECC_HW;
|
||||
|
@ -227,7 +499,15 @@ void davinci_nand_init(struct nand_chip *nand)
|
|||
#else
|
||||
nand->ecc.mode = NAND_ECC_SOFT;
|
||||
#endif /* CONFIG_SYS_NAND_HW_ECC */
|
||||
|
||||
#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
|
||||
nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
|
||||
nand->ecc.size = 512;
|
||||
nand->ecc.bytes = 10;
|
||||
nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
|
||||
nand->ecc.correct = nand_davinci_4bit_correct_data;
|
||||
nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
|
||||
nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
|
||||
#endif
|
||||
/* Set address of hardware control function */
|
||||
nand->cmd_ctrl = nand_davinci_hwcontrol;
|
||||
|
||||
|
|
|
@ -662,7 +662,7 @@ static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
|
|||
|
||||
static int fsl_elbc_read_page(struct mtd_info *mtd,
|
||||
struct nand_chip *chip,
|
||||
uint8_t *buf)
|
||||
uint8_t *buf, int page)
|
||||
{
|
||||
fsl_elbc_read_buf(mtd, buf, mtd->writesize);
|
||||
fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
|
||||
|
|
150
drivers/mtd/nand/kb9202_nand.c
Normal file
150
drivers/mtd/nand/kb9202_nand.c
Normal file
|
@ -0,0 +1,150 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* KwikByte <kb9200_dev@kwikbyte.com>
|
||||
*
|
||||
* (C) Copyright 2009
|
||||
* Matthias Kaehlcke <matthias@kaehlcke.net>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/AT91RM9200.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
#include <nand.h>
|
||||
|
||||
/*
|
||||
* hardware specific access to control-lines
|
||||
*/
|
||||
|
||||
#define MASK_ALE (1 << 22) /* our ALE is A22 */
|
||||
#define MASK_CLE (1 << 21) /* our CLE is A21 */
|
||||
|
||||
#define KB9202_NAND_NCE (1 << 28) /* EN* on D28 */
|
||||
#define KB9202_NAND_BUSY (1 << 29) /* RB* on D29 */
|
||||
|
||||
#define KB9202_SMC2_NWS (1 << 2)
|
||||
#define KB9202_SMC2_TDF (1 << 8)
|
||||
#define KB9202_SMC2_RWSETUP (1 << 24)
|
||||
#define KB9202_SMC2_RWHOLD (1 << 29)
|
||||
|
||||
/*
|
||||
* Board-specific function to access device control signals
|
||||
*/
|
||||
static void kb9202_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
|
||||
{
|
||||
struct nand_chip *this = mtd->priv;
|
||||
|
||||
if (ctrl & NAND_CTRL_CHANGE) {
|
||||
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
|
||||
|
||||
/* clear ALE and CLE bits */
|
||||
IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
|
||||
|
||||
if (ctrl & NAND_CLE)
|
||||
IO_ADDR_W |= MASK_CLE;
|
||||
|
||||
if (ctrl & NAND_ALE)
|
||||
IO_ADDR_W |= MASK_ALE;
|
||||
|
||||
this->IO_ADDR_W = (void *) IO_ADDR_W;
|
||||
|
||||
if (ctrl & NAND_NCE)
|
||||
writel(KB9202_NAND_NCE, AT91C_PIOC_CODR);
|
||||
else
|
||||
writel(KB9202_NAND_NCE, AT91C_PIOC_SODR);
|
||||
}
|
||||
|
||||
if (cmd != NAND_CMD_NONE)
|
||||
writeb(cmd, this->IO_ADDR_W);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Board-specific function to access the device ready signal.
|
||||
*/
|
||||
static int kb9202_nand_ready(struct mtd_info *mtd)
|
||||
{
|
||||
return readl(AT91C_PIOC_PDSR) & KB9202_NAND_BUSY;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Board-specific NAND init. Copied from include/linux/mtd/nand.h for reference.
|
||||
*
|
||||
* struct nand_chip - NAND Private Flash Chip Data
|
||||
* @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
|
||||
* @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
|
||||
* @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines
|
||||
* @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
|
||||
* If set to NULL no access to ready/busy is available and the ready/busy information
|
||||
* is read from the chip status register
|
||||
* @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only
|
||||
* be provided if a hardware ECC is available
|
||||
* @eccmode: [BOARDSPECIFIC] mode of ecc, see defines
|
||||
* @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
|
||||
* @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
|
||||
* special functionality. See the defines for further explanation
|
||||
*/
|
||||
/*
|
||||
* This routine initializes controller and GPIOs.
|
||||
*/
|
||||
int board_nand_init(struct nand_chip *nand)
|
||||
{
|
||||
unsigned int value;
|
||||
|
||||
nand->ecc.mode = NAND_ECC_SOFT;
|
||||
nand->cmd_ctrl = kb9202_nand_hwcontrol;
|
||||
nand->dev_ready = kb9202_nand_ready;
|
||||
|
||||
/* in case running outside of bootloader */
|
||||
writel(1 << AT91C_ID_PIOC, AT91C_PMC_PCER);
|
||||
|
||||
/* setup nand flash access (allow ample margin) */
|
||||
/* 4 wait states, 1 setup, 1 hold, 1 float for 8-bit device */
|
||||
writel(AT91C_SMC2_WSEN | KB9202_SMC2_NWS | KB9202_SMC2_TDF |
|
||||
AT91C_SMC2_DBW_8 | KB9202_SMC2_RWSETUP | KB9202_SMC2_RWHOLD,
|
||||
AT91C_SMC_CSR3);
|
||||
|
||||
/* enable internal NAND controller */
|
||||
value = readl(AT91C_EBI_CSA);
|
||||
value |= AT91C_EBI_CS3A_SMC_SmartMedia;
|
||||
writel(value, AT91C_EBI_CSA);
|
||||
|
||||
/* enable SMOE/SMWE */
|
||||
writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_ASR);
|
||||
writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_PDR);
|
||||
writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_OER);
|
||||
|
||||
/* set NCE to high */
|
||||
writel(KB9202_NAND_NCE, AT91C_PIOC_SODR);
|
||||
|
||||
/* disable output on pin connected to the busy line of the NAND */
|
||||
writel(KB9202_NAND_BUSY, AT91C_PIOC_ODR);
|
||||
|
||||
/* enable the PIO to control NCE and BUSY */
|
||||
writel(KB9202_NAND_NCE | KB9202_NAND_BUSY, AT91C_PIOC_PER);
|
||||
|
||||
/* enable output for NCE */
|
||||
writel(KB9202_NAND_NCE, AT91C_PIOC_OER);
|
||||
|
||||
return (0);
|
||||
}
|
135
drivers/mtd/nand/kmeter1_nand.c
Normal file
135
drivers/mtd/nand/kmeter1_nand.c
Normal file
|
@ -0,0 +1,135 @@
|
|||
/*
|
||||
* (C) Copyright 2009
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <nand.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define CONFIG_NAND_MODE_REG (void *)(CONFIG_SYS_NAND_BASE + 0x20000)
|
||||
#define CONFIG_NAND_DATA_REG (void *)(CONFIG_SYS_NAND_BASE + 0x30000)
|
||||
|
||||
#define read_mode() in_8(CONFIG_NAND_MODE_REG)
|
||||
#define write_mode(val) out_8(CONFIG_NAND_MODE_REG, val)
|
||||
#define read_data() in_8(CONFIG_NAND_DATA_REG)
|
||||
#define write_data(val) out_8(CONFIG_NAND_DATA_REG, val)
|
||||
|
||||
#define KPN_RDY2 (1 << 7)
|
||||
#define KPN_RDY1 (1 << 6)
|
||||
#define KPN_WPN (1 << 4)
|
||||
#define KPN_CE2N (1 << 3)
|
||||
#define KPN_CE1N (1 << 2)
|
||||
#define KPN_ALE (1 << 1)
|
||||
#define KPN_CLE (1 << 0)
|
||||
|
||||
#define KPN_DEFAULT_CHIP_DELAY 50
|
||||
|
||||
static int kpn_chip_ready(void)
|
||||
{
|
||||
if (read_mode() & KPN_RDY1)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void kpn_wait_rdy(void)
|
||||
{
|
||||
int cnt = 1000000;
|
||||
|
||||
while (--cnt && !kpn_chip_ready())
|
||||
udelay(1);
|
||||
|
||||
if (!cnt)
|
||||
printf ("timeout while waiting for RDY\n");
|
||||
}
|
||||
|
||||
static void kpn_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
|
||||
{
|
||||
u8 reg_val = read_mode();
|
||||
|
||||
if (ctrl & NAND_CTRL_CHANGE) {
|
||||
reg_val = reg_val & ~(KPN_ALE + KPN_CLE);
|
||||
|
||||
if (ctrl & NAND_CLE)
|
||||
reg_val = reg_val | KPN_CLE;
|
||||
if (ctrl & NAND_ALE)
|
||||
reg_val = reg_val | KPN_ALE;
|
||||
if (ctrl & NAND_NCE)
|
||||
reg_val = reg_val & ~KPN_CE1N;
|
||||
else
|
||||
reg_val = reg_val | KPN_CE1N;
|
||||
|
||||
write_mode(reg_val);
|
||||
}
|
||||
if (cmd != NAND_CMD_NONE)
|
||||
write_data(cmd);
|
||||
|
||||
/* wait until flash is ready */
|
||||
kpn_wait_rdy();
|
||||
}
|
||||
|
||||
static u_char kpn_nand_read_byte(struct mtd_info *mtd)
|
||||
{
|
||||
return read_data();
|
||||
}
|
||||
|
||||
static void kpn_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
write_data(buf[i]);
|
||||
kpn_wait_rdy();
|
||||
}
|
||||
}
|
||||
|
||||
static void kpn_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
buf[i] = read_data();
|
||||
}
|
||||
|
||||
static int kpn_nand_dev_ready(struct mtd_info *mtd)
|
||||
{
|
||||
kpn_wait_rdy();
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int board_nand_init(struct nand_chip *nand)
|
||||
{
|
||||
nand->ecc.mode = NAND_ECC_SOFT;
|
||||
|
||||
/* Reference hardware control function */
|
||||
nand->cmd_ctrl = kpn_nand_hwcontrol;
|
||||
nand->read_byte = kpn_nand_read_byte;
|
||||
nand->write_buf = kpn_nand_write_buf;
|
||||
nand->read_buf = kpn_nand_read_buf;
|
||||
nand->dev_ready = kpn_nand_dev_ready;
|
||||
nand->chip_delay = KPN_DEFAULT_CHIP_DELAY;
|
||||
|
||||
/* reset mode register */
|
||||
write_mode(KPN_CE1N + KPN_CE2N + KPN_WPN);
|
||||
return 0;
|
||||
}
|
880
drivers/mtd/nand/mxc_nand.c
Normal file
880
drivers/mtd/nand/mxc_nand.c
Normal file
|
@ -0,0 +1,880 @@
|
|||
/*
|
||||
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
* Copyright 2008 Sascha Hauer, kernel@pengutronix.de
|
||||
* Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <nand.h>
|
||||
#include <linux/err.h>
|
||||
#include <asm/io.h>
|
||||
#ifdef CONFIG_MX27
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#endif
|
||||
|
||||
#define DRIVER_NAME "mxc_nand"
|
||||
|
||||
struct nfc_regs {
|
||||
/* NFC RAM BUFFER Main area 0 */
|
||||
uint8_t main_area0[0x200];
|
||||
uint8_t main_area1[0x200];
|
||||
uint8_t main_area2[0x200];
|
||||
uint8_t main_area3[0x200];
|
||||
/* SPARE BUFFER Spare area 0 */
|
||||
uint8_t spare_area0[0x10];
|
||||
uint8_t spare_area1[0x10];
|
||||
uint8_t spare_area2[0x10];
|
||||
uint8_t spare_area3[0x10];
|
||||
uint8_t pad[0x5c0];
|
||||
/* NFC registers */
|
||||
uint16_t nfc_buf_size;
|
||||
uint16_t reserved;
|
||||
uint16_t nfc_buf_addr;
|
||||
uint16_t nfc_flash_addr;
|
||||
uint16_t nfc_flash_cmd;
|
||||
uint16_t nfc_config;
|
||||
uint16_t nfc_ecc_status_result;
|
||||
uint16_t nfc_rsltmain_area;
|
||||
uint16_t nfc_rsltspare_area;
|
||||
uint16_t nfc_wrprot;
|
||||
uint16_t nfc_unlockstart_blkaddr;
|
||||
uint16_t nfc_unlockend_blkaddr;
|
||||
uint16_t nfc_nf_wrprst;
|
||||
uint16_t nfc_config1;
|
||||
uint16_t nfc_config2;
|
||||
};
|
||||
|
||||
/*
|
||||
* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
|
||||
* for Command operation
|
||||
*/
|
||||
#define NFC_CMD 0x1
|
||||
|
||||
/*
|
||||
* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
|
||||
* for Address operation
|
||||
*/
|
||||
#define NFC_ADDR 0x2
|
||||
|
||||
/*
|
||||
* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
|
||||
* for Input operation
|
||||
*/
|
||||
#define NFC_INPUT 0x4
|
||||
|
||||
/*
|
||||
* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
|
||||
* for Data Output operation
|
||||
*/
|
||||
#define NFC_OUTPUT 0x8
|
||||
|
||||
/*
|
||||
* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
|
||||
* for Read ID operation
|
||||
*/
|
||||
#define NFC_ID 0x10
|
||||
|
||||
/*
|
||||
* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
|
||||
* for Read Status operation
|
||||
*/
|
||||
#define NFC_STATUS 0x20
|
||||
|
||||
/*
|
||||
* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
|
||||
* Status operation
|
||||
*/
|
||||
#define NFC_INT 0x8000
|
||||
|
||||
#define NFC_SP_EN (1 << 2)
|
||||
#define NFC_ECC_EN (1 << 3)
|
||||
#define NFC_BIG (1 << 5)
|
||||
#define NFC_RST (1 << 6)
|
||||
#define NFC_CE (1 << 7)
|
||||
#define NFC_ONE_CYCLE (1 << 8)
|
||||
|
||||
typedef enum {false, true} bool;
|
||||
|
||||
struct mxc_nand_host {
|
||||
struct mtd_info mtd;
|
||||
struct nand_chip *nand;
|
||||
|
||||
struct nfc_regs __iomem *regs;
|
||||
int spare_only;
|
||||
int status_request;
|
||||
int pagesize_2k;
|
||||
int clk_act;
|
||||
uint16_t col_addr;
|
||||
};
|
||||
|
||||
static struct mxc_nand_host mxc_host;
|
||||
static struct mxc_nand_host *host = &mxc_host;
|
||||
|
||||
/* Define delays in microsec for NAND device operations */
|
||||
#define TROP_US_DELAY 2000
|
||||
/* Macros to get byte and bit positions of ECC */
|
||||
#define COLPOS(x) ((x) >> 3)
|
||||
#define BITPOS(x) ((x) & 0xf)
|
||||
|
||||
/* Define single bit Error positions in Main & Spare area */
|
||||
#define MAIN_SINGLEBIT_ERROR 0x4
|
||||
#define SPARE_SINGLEBIT_ERROR 0x1
|
||||
|
||||
/* OOB placement block for use with hardware ecc generation */
|
||||
#ifdef CONFIG_MXC_NAND_HWECC
|
||||
static struct nand_ecclayout nand_hw_eccoob = {
|
||||
.eccbytes = 5,
|
||||
.eccpos = {6, 7, 8, 9, 10},
|
||||
.oobfree = {{0, 5}, {11, 5}, }
|
||||
};
|
||||
#else
|
||||
static struct nand_ecclayout nand_soft_eccoob = {
|
||||
.eccbytes = 6,
|
||||
.eccpos = {6, 7, 8, 9, 10, 11},
|
||||
.oobfree = {{0, 5}, {12, 4}, }
|
||||
};
|
||||
#endif
|
||||
|
||||
static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
|
||||
{
|
||||
uint32_t *d = dest;
|
||||
|
||||
size >>= 2;
|
||||
while (size--)
|
||||
__raw_writel(__raw_readl(source++), d++);
|
||||
return dest;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function polls the NANDFC to wait for the basic operation to
|
||||
* complete by checking the INT bit of config2 register.
|
||||
*/
|
||||
static void wait_op_done(struct mxc_nand_host *host, int max_retries,
|
||||
uint16_t param)
|
||||
{
|
||||
uint32_t tmp;
|
||||
|
||||
while (max_retries-- > 0) {
|
||||
if (readw(&host->regs->nfc_config2) & NFC_INT) {
|
||||
tmp = readw(&host->regs->nfc_config2);
|
||||
tmp &= ~NFC_INT;
|
||||
writew(tmp, &host->regs->nfc_config2);
|
||||
break;
|
||||
}
|
||||
udelay(1);
|
||||
}
|
||||
if (max_retries < 0) {
|
||||
MTDDEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
|
||||
__func__, param);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* This function issues the specified command to the NAND device and
|
||||
* waits for completion.
|
||||
*/
|
||||
static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
|
||||
{
|
||||
MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
|
||||
|
||||
writew(cmd, &host->regs->nfc_flash_cmd);
|
||||
writew(NFC_CMD, &host->regs->nfc_config2);
|
||||
|
||||
/* Wait for operation to complete */
|
||||
wait_op_done(host, TROP_US_DELAY, cmd);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function sends an address (or partial address) to the
|
||||
* NAND device. The address is used to select the source/destination for
|
||||
* a NAND command.
|
||||
*/
|
||||
static void send_addr(struct mxc_nand_host *host, uint16_t addr)
|
||||
{
|
||||
MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
|
||||
|
||||
writew(addr, &host->regs->nfc_flash_addr);
|
||||
writew(NFC_ADDR, &host->regs->nfc_config2);
|
||||
|
||||
/* Wait for operation to complete */
|
||||
wait_op_done(host, TROP_US_DELAY, addr);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function requests the NANDFC to initate the transfer
|
||||
* of data currently in the NANDFC RAM buffer to the NAND device.
|
||||
*/
|
||||
static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
|
||||
int spare_only)
|
||||
{
|
||||
MTDDEBUG(MTD_DEBUG_LEVEL3, "send_prog_page (%d)\n", spare_only);
|
||||
|
||||
writew(buf_id, &host->regs->nfc_buf_addr);
|
||||
|
||||
/* Configure spare or page+spare access */
|
||||
if (!host->pagesize_2k) {
|
||||
uint16_t config1 = readw(&host->regs->nfc_config1);
|
||||
if (spare_only)
|
||||
config1 |= NFC_SP_EN;
|
||||
else
|
||||
config1 &= ~(NFC_SP_EN);
|
||||
writew(config1, &host->regs->nfc_config1);
|
||||
}
|
||||
|
||||
writew(NFC_INPUT, &host->regs->nfc_config2);
|
||||
|
||||
/* Wait for operation to complete */
|
||||
wait_op_done(host, TROP_US_DELAY, spare_only);
|
||||
}
|
||||
|
||||
/*
|
||||
* Requests NANDFC to initated the transfer of data from the
|
||||
* NAND device into in the NANDFC ram buffer.
|
||||
*/
|
||||
static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
|
||||
int spare_only)
|
||||
{
|
||||
MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
|
||||
|
||||
writew(buf_id, &host->regs->nfc_buf_addr);
|
||||
|
||||
/* Configure spare or page+spare access */
|
||||
if (!host->pagesize_2k) {
|
||||
uint32_t config1 = readw(&host->regs->nfc_config1);
|
||||
if (spare_only)
|
||||
config1 |= NFC_SP_EN;
|
||||
else
|
||||
config1 &= ~NFC_SP_EN;
|
||||
writew(config1, &host->regs->nfc_config1);
|
||||
}
|
||||
|
||||
writew(NFC_OUTPUT, &host->regs->nfc_config2);
|
||||
|
||||
/* Wait for operation to complete */
|
||||
wait_op_done(host, TROP_US_DELAY, spare_only);
|
||||
}
|
||||
|
||||
/* Request the NANDFC to perform a read of the NAND device ID. */
|
||||
static void send_read_id(struct mxc_nand_host *host)
|
||||
{
|
||||
uint16_t tmp;
|
||||
|
||||
/* NANDFC buffer 0 is used for device ID output */
|
||||
writew(0x0, &host->regs->nfc_buf_addr);
|
||||
|
||||
/* Read ID into main buffer */
|
||||
tmp = readw(&host->regs->nfc_config1);
|
||||
tmp &= ~NFC_SP_EN;
|
||||
writew(tmp, &host->regs->nfc_config1);
|
||||
|
||||
writew(NFC_ID, &host->regs->nfc_config2);
|
||||
|
||||
/* Wait for operation to complete */
|
||||
wait_op_done(host, TROP_US_DELAY, 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* This function requests the NANDFC to perform a read of the
|
||||
* NAND device status and returns the current status.
|
||||
*/
|
||||
static uint16_t get_dev_status(struct mxc_nand_host *host)
|
||||
{
|
||||
void __iomem *main_buf = host->regs->main_area1;
|
||||
uint32_t store;
|
||||
uint16_t ret, tmp;
|
||||
/* Issue status request to NAND device */
|
||||
|
||||
/* store the main area1 first word, later do recovery */
|
||||
store = readl(main_buf);
|
||||
/* NANDFC buffer 1 is used for device status */
|
||||
writew(1, &host->regs->nfc_buf_addr);
|
||||
|
||||
/* Read status into main buffer */
|
||||
tmp = readw(&host->regs->nfc_config1);
|
||||
tmp &= ~NFC_SP_EN;
|
||||
writew(tmp, &host->regs->nfc_config1);
|
||||
|
||||
writew(NFC_STATUS, &host->regs->nfc_config2);
|
||||
|
||||
/* Wait for operation to complete */
|
||||
wait_op_done(host, TROP_US_DELAY, 0);
|
||||
|
||||
/*
|
||||
* Status is placed in first word of main buffer
|
||||
* get status, then recovery area 1 data
|
||||
*/
|
||||
ret = readw(main_buf);
|
||||
writel(store, main_buf);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* This function is used by upper layer to checks if device is ready */
|
||||
static int mxc_nand_dev_ready(struct mtd_info *mtd)
|
||||
{
|
||||
/*
|
||||
* NFC handles R/B internally. Therefore, this function
|
||||
* always returns status as ready.
|
||||
*/
|
||||
return 1;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MXC_NAND_HWECC
|
||||
static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
|
||||
{
|
||||
/*
|
||||
* If HW ECC is enabled, we turn it on during init. There is
|
||||
* no need to enable again here.
|
||||
*/
|
||||
}
|
||||
|
||||
static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
|
||||
u_char *read_ecc, u_char *calc_ecc)
|
||||
{
|
||||
struct nand_chip *nand_chip = mtd->priv;
|
||||
struct mxc_nand_host *host = nand_chip->priv;
|
||||
|
||||
/*
|
||||
* 1-Bit errors are automatically corrected in HW. No need for
|
||||
* additional correction. 2-Bit errors cannot be corrected by
|
||||
* HW ECC, so we need to return failure
|
||||
*/
|
||||
uint16_t ecc_status = readw(&host->regs->nfc_ecc_status_result);
|
||||
|
||||
if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
|
||||
MTDDEBUG(MTD_DEBUG_LEVEL0,
|
||||
"MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
|
||||
u_char *ecc_code)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static u_char mxc_nand_read_byte(struct mtd_info *mtd)
|
||||
{
|
||||
struct nand_chip *nand_chip = mtd->priv;
|
||||
struct mxc_nand_host *host = nand_chip->priv;
|
||||
uint8_t ret = 0;
|
||||
uint16_t col;
|
||||
uint16_t __iomem *main_buf =
|
||||
(uint16_t __iomem *)host->regs->main_area0;
|
||||
uint16_t __iomem *spare_buf =
|
||||
(uint16_t __iomem *)host->regs->spare_area0;
|
||||
union {
|
||||
uint16_t word;
|
||||
uint8_t bytes[2];
|
||||
} nfc_word;
|
||||
|
||||
/* Check for status request */
|
||||
if (host->status_request)
|
||||
return get_dev_status(host) & 0xFF;
|
||||
|
||||
/* Get column for 16-bit access */
|
||||
col = host->col_addr >> 1;
|
||||
|
||||
/* If we are accessing the spare region */
|
||||
if (host->spare_only)
|
||||
nfc_word.word = readw(&spare_buf[col]);
|
||||
else
|
||||
nfc_word.word = readw(&main_buf[col]);
|
||||
|
||||
/* Pick upper/lower byte of word from RAM buffer */
|
||||
ret = nfc_word.bytes[host->col_addr & 0x1];
|
||||
|
||||
/* Update saved column address */
|
||||
if (nand_chip->options & NAND_BUSWIDTH_16)
|
||||
host->col_addr += 2;
|
||||
else
|
||||
host->col_addr++;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
|
||||
{
|
||||
struct nand_chip *nand_chip = mtd->priv;
|
||||
struct mxc_nand_host *host = nand_chip->priv;
|
||||
uint16_t col, ret;
|
||||
uint16_t __iomem *p;
|
||||
|
||||
MTDDEBUG(MTD_DEBUG_LEVEL3,
|
||||
"mxc_nand_read_word(col = %d)\n", host->col_addr);
|
||||
|
||||
col = host->col_addr;
|
||||
/* Adjust saved column address */
|
||||
if (col < mtd->writesize && host->spare_only)
|
||||
col += mtd->writesize;
|
||||
|
||||
if (col < mtd->writesize) {
|
||||
p = (uint16_t __iomem *)(host->regs->main_area0 + (col >> 1));
|
||||
} else {
|
||||
p = (uint16_t __iomem *)(host->regs->spare_area0 +
|
||||
((col - mtd->writesize) >> 1));
|
||||
}
|
||||
|
||||
if (col & 1) {
|
||||
union {
|
||||
uint16_t word;
|
||||
uint8_t bytes[2];
|
||||
} nfc_word[3];
|
||||
|
||||
nfc_word[0].word = readw(p);
|
||||
nfc_word[1].word = readw(p + 1);
|
||||
|
||||
nfc_word[2].bytes[0] = nfc_word[0].bytes[1];
|
||||
nfc_word[2].bytes[1] = nfc_word[1].bytes[0];
|
||||
|
||||
ret = nfc_word[2].word;
|
||||
} else {
|
||||
ret = readw(p);
|
||||
}
|
||||
|
||||
/* Update saved column address */
|
||||
host->col_addr = col + 2;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Write data of length len to buffer buf. The data to be
|
||||
* written on NAND Flash is first copied to RAMbuffer. After the Data Input
|
||||
* Operation by the NFC, the data is written to NAND Flash
|
||||
*/
|
||||
static void mxc_nand_write_buf(struct mtd_info *mtd,
|
||||
const u_char *buf, int len)
|
||||
{
|
||||
struct nand_chip *nand_chip = mtd->priv;
|
||||
struct mxc_nand_host *host = nand_chip->priv;
|
||||
int n, col, i = 0;
|
||||
|
||||
MTDDEBUG(MTD_DEBUG_LEVEL3,
|
||||
"mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
|
||||
len);
|
||||
|
||||
col = host->col_addr;
|
||||
|
||||
/* Adjust saved column address */
|
||||
if (col < mtd->writesize && host->spare_only)
|
||||
col += mtd->writesize;
|
||||
|
||||
n = mtd->writesize + mtd->oobsize - col;
|
||||
n = min(len, n);
|
||||
|
||||
MTDDEBUG(MTD_DEBUG_LEVEL3,
|
||||
"%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
|
||||
|
||||
while (n > 0) {
|
||||
void __iomem *p;
|
||||
|
||||
if (col < mtd->writesize) {
|
||||
p = host->regs->main_area0 + (col & ~3);
|
||||
} else {
|
||||
p = host->regs->spare_area0 -
|
||||
mtd->writesize + (col & ~3);
|
||||
}
|
||||
|
||||
MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
|
||||
__LINE__, p);
|
||||
|
||||
if (((col | (unsigned long)&buf[i]) & 3) || n < 4) {
|
||||
union {
|
||||
uint32_t word;
|
||||
uint8_t bytes[4];
|
||||
} nfc_word;
|
||||
|
||||
nfc_word.word = readl(p);
|
||||
nfc_word.bytes[col & 3] = buf[i++];
|
||||
n--;
|
||||
col++;
|
||||
|
||||
writel(nfc_word.word, p);
|
||||
} else {
|
||||
int m = mtd->writesize - col;
|
||||
|
||||
if (col >= mtd->writesize)
|
||||
m += mtd->oobsize;
|
||||
|
||||
m = min(n, m) & ~3;
|
||||
|
||||
MTDDEBUG(MTD_DEBUG_LEVEL3,
|
||||
"%s:%d: n = %d, m = %d, i = %d, col = %d\n",
|
||||
__func__, __LINE__, n, m, i, col);
|
||||
|
||||
mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m);
|
||||
col += m;
|
||||
i += m;
|
||||
n -= m;
|
||||
}
|
||||
}
|
||||
/* Update saved column address */
|
||||
host->col_addr = col;
|
||||
}
|
||||
|
||||
/*
|
||||
* Read the data buffer from the NAND Flash. To read the data from NAND
|
||||
* Flash first the data output cycle is initiated by the NFC, which copies
|
||||
* the data to RAMbuffer. This data of length len is then copied to buffer buf.
|
||||
*/
|
||||
static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
|
||||
{
|
||||
struct nand_chip *nand_chip = mtd->priv;
|
||||
struct mxc_nand_host *host = nand_chip->priv;
|
||||
int n, col, i = 0;
|
||||
|
||||
MTDDEBUG(MTD_DEBUG_LEVEL3,
|
||||
"mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
|
||||
|
||||
col = host->col_addr;
|
||||
|
||||
/* Adjust saved column address */
|
||||
if (col < mtd->writesize && host->spare_only)
|
||||
col += mtd->writesize;
|
||||
|
||||
n = mtd->writesize + mtd->oobsize - col;
|
||||
n = min(len, n);
|
||||
|
||||
while (n > 0) {
|
||||
void __iomem *p;
|
||||
|
||||
if (col < mtd->writesize) {
|
||||
p = host->regs->main_area0 + (col & ~3);
|
||||
} else {
|
||||
p = host->regs->spare_area0 -
|
||||
mtd->writesize + (col & ~3);
|
||||
}
|
||||
|
||||
if (((col | (int)&buf[i]) & 3) || n < 4) {
|
||||
union {
|
||||
uint32_t word;
|
||||
uint8_t bytes[4];
|
||||
} nfc_word;
|
||||
|
||||
nfc_word.word = readl(p);
|
||||
buf[i++] = nfc_word.bytes[col & 3];
|
||||
n--;
|
||||
col++;
|
||||
} else {
|
||||
int m = mtd->writesize - col;
|
||||
|
||||
if (col >= mtd->writesize)
|
||||
m += mtd->oobsize;
|
||||
|
||||
m = min(n, m) & ~3;
|
||||
mxc_nand_memcpy32((uint32_t *)&buf[i], p, m);
|
||||
|
||||
col += m;
|
||||
i += m;
|
||||
n -= m;
|
||||
}
|
||||
}
|
||||
/* Update saved column address */
|
||||
host->col_addr = col;
|
||||
}
|
||||
|
||||
/*
|
||||
* Used by the upper layer to verify the data in NAND Flash
|
||||
* with the data in the buf.
|
||||
*/
|
||||
static int mxc_nand_verify_buf(struct mtd_info *mtd,
|
||||
const u_char *buf, int len)
|
||||
{
|
||||
u_char tmp[256];
|
||||
uint bsize;
|
||||
|
||||
while (len) {
|
||||
bsize = min(len, 256);
|
||||
mxc_nand_read_buf(mtd, tmp, bsize);
|
||||
|
||||
if (memcmp(buf, tmp, bsize))
|
||||
return 1;
|
||||
|
||||
buf += bsize;
|
||||
len -= bsize;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is used by upper layer for select and
|
||||
* deselect of the NAND chip
|
||||
*/
|
||||
static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
|
||||
{
|
||||
struct nand_chip *nand_chip = mtd->priv;
|
||||
struct mxc_nand_host *host = nand_chip->priv;
|
||||
|
||||
switch (chip) {
|
||||
case -1:
|
||||
/* TODO: Disable the NFC clock */
|
||||
if (host->clk_act)
|
||||
host->clk_act = 0;
|
||||
break;
|
||||
case 0:
|
||||
/* TODO: Enable the NFC clock */
|
||||
if (!host->clk_act)
|
||||
host->clk_act = 1;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Used by the upper layer to write command to NAND Flash for
|
||||
* different operations to be carried out on NAND Flash
|
||||
*/
|
||||
static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
|
||||
int column, int page_addr)
|
||||
{
|
||||
struct nand_chip *nand_chip = mtd->priv;
|
||||
struct mxc_nand_host *host = nand_chip->priv;
|
||||
|
||||
MTDDEBUG(MTD_DEBUG_LEVEL3,
|
||||
"mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
|
||||
command, column, page_addr);
|
||||
|
||||
/* Reset command state information */
|
||||
host->status_request = false;
|
||||
|
||||
/* Command pre-processing step */
|
||||
switch (command) {
|
||||
|
||||
case NAND_CMD_STATUS:
|
||||
host->col_addr = 0;
|
||||
host->status_request = true;
|
||||
break;
|
||||
|
||||
case NAND_CMD_READ0:
|
||||
host->col_addr = column;
|
||||
host->spare_only = false;
|
||||
break;
|
||||
|
||||
case NAND_CMD_READOOB:
|
||||
host->col_addr = column;
|
||||
host->spare_only = true;
|
||||
if (host->pagesize_2k)
|
||||
command = NAND_CMD_READ0; /* only READ0 is valid */
|
||||
break;
|
||||
|
||||
case NAND_CMD_SEQIN:
|
||||
if (column >= mtd->writesize) {
|
||||
/*
|
||||
* before sending SEQIN command for partial write,
|
||||
* we need read one page out. FSL NFC does not support
|
||||
* partial write. It alway send out 512+ecc+512+ecc ...
|
||||
* for large page nand flash. But for small page nand
|
||||
* flash, it does support SPARE ONLY operation.
|
||||
*/
|
||||
if (host->pagesize_2k) {
|
||||
/* call ourself to read a page */
|
||||
mxc_nand_command(mtd, NAND_CMD_READ0, 0,
|
||||
page_addr);
|
||||
}
|
||||
|
||||
host->col_addr = column - mtd->writesize;
|
||||
host->spare_only = true;
|
||||
|
||||
/* Set program pointer to spare region */
|
||||
if (!host->pagesize_2k)
|
||||
send_cmd(host, NAND_CMD_READOOB);
|
||||
} else {
|
||||
host->spare_only = false;
|
||||
host->col_addr = column;
|
||||
|
||||
/* Set program pointer to page start */
|
||||
if (!host->pagesize_2k)
|
||||
send_cmd(host, NAND_CMD_READ0);
|
||||
}
|
||||
break;
|
||||
|
||||
case NAND_CMD_PAGEPROG:
|
||||
send_prog_page(host, 0, host->spare_only);
|
||||
|
||||
if (host->pagesize_2k) {
|
||||
/* data in 4 areas datas */
|
||||
send_prog_page(host, 1, host->spare_only);
|
||||
send_prog_page(host, 2, host->spare_only);
|
||||
send_prog_page(host, 3, host->spare_only);
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
/* Write out the command to the device. */
|
||||
send_cmd(host, command);
|
||||
|
||||
/* Write out column address, if necessary */
|
||||
if (column != -1) {
|
||||
/*
|
||||
* MXC NANDFC can only perform full page+spare or
|
||||
* spare-only read/write. When the upper layers
|
||||
* layers perform a read/write buf operation,
|
||||
* we will used the saved column adress to index into
|
||||
* the full page.
|
||||
*/
|
||||
send_addr(host, 0);
|
||||
if (host->pagesize_2k)
|
||||
/* another col addr cycle for 2k page */
|
||||
send_addr(host, 0);
|
||||
}
|
||||
|
||||
/* Write out page address, if necessary */
|
||||
if (page_addr != -1) {
|
||||
/* paddr_0 - p_addr_7 */
|
||||
send_addr(host, (page_addr & 0xff));
|
||||
|
||||
if (host->pagesize_2k) {
|
||||
send_addr(host, (page_addr >> 8) & 0xFF);
|
||||
if (mtd->size >= 0x10000000) {
|
||||
/* paddr_8 - paddr_15 */
|
||||
send_addr(host, (page_addr >> 8) & 0xff);
|
||||
send_addr(host, (page_addr >> 16) & 0xff);
|
||||
} else {
|
||||
/* paddr_8 - paddr_15 */
|
||||
send_addr(host, (page_addr >> 8) & 0xff);
|
||||
}
|
||||
} else {
|
||||
/* One more address cycle for higher density devices */
|
||||
if (mtd->size >= 0x4000000) {
|
||||
/* paddr_8 - paddr_15 */
|
||||
send_addr(host, (page_addr >> 8) & 0xff);
|
||||
send_addr(host, (page_addr >> 16) & 0xff);
|
||||
} else {
|
||||
/* paddr_8 - paddr_15 */
|
||||
send_addr(host, (page_addr >> 8) & 0xff);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Command post-processing step */
|
||||
switch (command) {
|
||||
|
||||
case NAND_CMD_RESET:
|
||||
break;
|
||||
|
||||
case NAND_CMD_READOOB:
|
||||
case NAND_CMD_READ0:
|
||||
if (host->pagesize_2k) {
|
||||
/* send read confirm command */
|
||||
send_cmd(host, NAND_CMD_READSTART);
|
||||
/* read for each AREA */
|
||||
send_read_page(host, 0, host->spare_only);
|
||||
send_read_page(host, 1, host->spare_only);
|
||||
send_read_page(host, 2, host->spare_only);
|
||||
send_read_page(host, 3, host->spare_only);
|
||||
} else {
|
||||
send_read_page(host, 0, host->spare_only);
|
||||
}
|
||||
break;
|
||||
|
||||
case NAND_CMD_READID:
|
||||
host->col_addr = 0;
|
||||
send_read_id(host);
|
||||
break;
|
||||
|
||||
case NAND_CMD_PAGEPROG:
|
||||
break;
|
||||
|
||||
case NAND_CMD_STATUS:
|
||||
break;
|
||||
|
||||
case NAND_CMD_ERASE2:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
int board_nand_init(struct nand_chip *this)
|
||||
{
|
||||
struct system_control_regs *sc_regs =
|
||||
(struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
|
||||
struct mtd_info *mtd;
|
||||
uint16_t tmp;
|
||||
int err = 0;
|
||||
|
||||
/* structures must be linked */
|
||||
mtd = &host->mtd;
|
||||
mtd->priv = this;
|
||||
host->nand = this;
|
||||
|
||||
/* 5 us command delay time */
|
||||
this->chip_delay = 5;
|
||||
|
||||
this->priv = host;
|
||||
this->dev_ready = mxc_nand_dev_ready;
|
||||
this->cmdfunc = mxc_nand_command;
|
||||
this->select_chip = mxc_nand_select_chip;
|
||||
this->read_byte = mxc_nand_read_byte;
|
||||
this->read_word = mxc_nand_read_word;
|
||||
this->write_buf = mxc_nand_write_buf;
|
||||
this->read_buf = mxc_nand_read_buf;
|
||||
this->verify_buf = mxc_nand_verify_buf;
|
||||
|
||||
host->regs = (struct nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
|
||||
host->clk_act = 1;
|
||||
|
||||
#ifdef CONFIG_MXC_NAND_HWECC
|
||||
this->ecc.calculate = mxc_nand_calculate_ecc;
|
||||
this->ecc.hwctl = mxc_nand_enable_hwecc;
|
||||
this->ecc.correct = mxc_nand_correct_data;
|
||||
this->ecc.mode = NAND_ECC_HW;
|
||||
this->ecc.size = 512;
|
||||
this->ecc.bytes = 3;
|
||||
this->ecc.layout = &nand_hw_eccoob;
|
||||
tmp = readw(&host->regs->nfc_config1);
|
||||
tmp |= NFC_ECC_EN;
|
||||
writew(tmp, &host->regs->nfc_config1);
|
||||
#else
|
||||
this->ecc.layout = &nand_soft_eccoob;
|
||||
this->ecc.mode = NAND_ECC_SOFT;
|
||||
tmp = readw(&host->regs->nfc_config1);
|
||||
tmp &= ~NFC_ECC_EN;
|
||||
writew(tmp, &host->regs->nfc_config1);
|
||||
#endif
|
||||
|
||||
/* Reset NAND */
|
||||
this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
|
||||
|
||||
/*
|
||||
* preset operation
|
||||
* Unlock the internal RAM Buffer
|
||||
*/
|
||||
writew(0x2, &host->regs->nfc_config);
|
||||
|
||||
/* Blocks to be unlocked */
|
||||
writew(0x0, &host->regs->nfc_unlockstart_blkaddr);
|
||||
writew(0x4000, &host->regs->nfc_unlockend_blkaddr);
|
||||
|
||||
/* Unlock Block Command for given address range */
|
||||
writew(0x4, &host->regs->nfc_wrprot);
|
||||
|
||||
/* NAND bus width determines access funtions used by upper layer */
|
||||
if (readl(&sc_regs->fmcr) & NF_16BIT_SEL)
|
||||
this->options |= NAND_BUSWIDTH_16;
|
||||
|
||||
host->pagesize_2k = 0;
|
||||
|
||||
return err;
|
||||
}
|
|
@ -895,7 +895,7 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
|
|||
* @buf: buffer to store read data
|
||||
*/
|
||||
static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
uint8_t *buf)
|
||||
uint8_t *buf, int page)
|
||||
{
|
||||
chip->read_buf(mtd, buf, mtd->writesize);
|
||||
chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
|
||||
|
@ -909,7 +909,7 @@ static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
|
|||
* @buf: buffer to store read data
|
||||
*/
|
||||
static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
uint8_t *buf)
|
||||
uint8_t *buf, int page)
|
||||
{
|
||||
int i, eccsize = chip->ecc.size;
|
||||
int eccbytes = chip->ecc.bytes;
|
||||
|
@ -919,7 +919,7 @@ static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
|
|||
uint8_t *ecc_code = chip->buffers->ecccode;
|
||||
uint32_t *eccpos = chip->ecc.layout->eccpos;
|
||||
|
||||
chip->ecc.read_page_raw(mtd, chip, buf);
|
||||
chip->ecc.read_page_raw(mtd, chip, buf, page);
|
||||
|
||||
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
|
||||
chip->ecc.calculate(mtd, p, &ecc_calc[i]);
|
||||
|
@ -1032,7 +1032,7 @@ static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint3
|
|||
* Not for syndrome calculating ecc controllers which need a special oob layout
|
||||
*/
|
||||
static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
uint8_t *buf)
|
||||
uint8_t *buf, int page)
|
||||
{
|
||||
int i, eccsize = chip->ecc.size;
|
||||
int eccbytes = chip->ecc.bytes;
|
||||
|
@ -1067,6 +1067,54 @@ static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
|
|||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
|
||||
* @mtd: mtd info structure
|
||||
* @chip: nand chip info structure
|
||||
* @buf: buffer to store read data
|
||||
*
|
||||
* Hardware ECC for large page chips, require OOB to be read first.
|
||||
* For this ECC mode, the write_page method is re-used from ECC_HW.
|
||||
* These methods read/write ECC from the OOB area, unlike the
|
||||
* ECC_HW_SYNDROME support with multiple ECC steps, follows the
|
||||
* "infix ECC" scheme and reads/writes ECC from the data area, by
|
||||
* overwriting the NAND manufacturer bad block markings.
|
||||
*/
|
||||
static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
|
||||
struct nand_chip *chip, uint8_t *buf, int page)
|
||||
{
|
||||
int i, eccsize = chip->ecc.size;
|
||||
int eccbytes = chip->ecc.bytes;
|
||||
int eccsteps = chip->ecc.steps;
|
||||
uint8_t *p = buf;
|
||||
uint8_t *ecc_code = chip->buffers->ecccode;
|
||||
uint32_t *eccpos = chip->ecc.layout->eccpos;
|
||||
uint8_t *ecc_calc = chip->buffers->ecccalc;
|
||||
|
||||
/* Read the OOB area first */
|
||||
chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
|
||||
chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
|
||||
chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
|
||||
|
||||
for (i = 0; i < chip->ecc.total; i++)
|
||||
ecc_code[i] = chip->oob_poi[eccpos[i]];
|
||||
|
||||
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
|
||||
int stat;
|
||||
|
||||
chip->ecc.hwctl(mtd, NAND_ECC_READ);
|
||||
chip->read_buf(mtd, p, eccsize);
|
||||
chip->ecc.calculate(mtd, p, &ecc_calc[i]);
|
||||
|
||||
stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
|
||||
if (stat < 0)
|
||||
mtd->ecc_stats.failed++;
|
||||
else
|
||||
mtd->ecc_stats.corrected += stat;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
|
||||
* @mtd: mtd info structure
|
||||
|
@ -1077,7 +1125,7 @@ static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
|
|||
* we need a special oob layout and handling.
|
||||
*/
|
||||
static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
uint8_t *buf)
|
||||
uint8_t *buf, int page)
|
||||
{
|
||||
int i, eccsize = chip->ecc.size;
|
||||
int eccbytes = chip->ecc.bytes;
|
||||
|
@ -1219,11 +1267,13 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
|
|||
|
||||
/* Now read the page into the buffer */
|
||||
if (unlikely(ops->mode == MTD_OOB_RAW))
|
||||
ret = chip->ecc.read_page_raw(mtd, chip, bufpoi);
|
||||
ret = chip->ecc.read_page_raw(mtd, chip,
|
||||
bufpoi, page);
|
||||
else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
|
||||
ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
|
||||
else
|
||||
ret = chip->ecc.read_page(mtd, chip, bufpoi);
|
||||
ret = chip->ecc.read_page(mtd, chip, bufpoi,
|
||||
page);
|
||||
if (ret < 0)
|
||||
break;
|
||||
|
||||
|
@ -2728,6 +2778,17 @@ int nand_scan_tail(struct mtd_info *mtd)
|
|||
chip->ecc.write_page_raw = nand_write_page_raw;
|
||||
|
||||
switch (chip->ecc.mode) {
|
||||
case NAND_ECC_HW_OOB_FIRST:
|
||||
/* Similar to NAND_ECC_HW, but a separate read_page handle */
|
||||
if (!chip->ecc.calculate || !chip->ecc.correct ||
|
||||
!chip->ecc.hwctl) {
|
||||
printk(KERN_WARNING "No ECC functions supplied, "
|
||||
"Hardware ECC not possible\n");
|
||||
BUG();
|
||||
}
|
||||
if (!chip->ecc.read_page)
|
||||
chip->ecc.read_page = nand_read_page_hwecc_oob_first;
|
||||
|
||||
case NAND_ECC_HW:
|
||||
/* Use standard hwecc read page function ? */
|
||||
if (!chip->ecc.read_page)
|
||||
|
|
|
@ -55,6 +55,16 @@ typedef struct {
|
|||
dv_reg NANDF2ECC;
|
||||
dv_reg NANDF3ECC;
|
||||
dv_reg NANDF4ECC;
|
||||
u_int8_t RSVD2[60];
|
||||
dv_reg NAND4BITECCLOAD;
|
||||
dv_reg NAND4BITECC1;
|
||||
dv_reg NAND4BITECC2;
|
||||
dv_reg NAND4BITECC3;
|
||||
dv_reg NAND4BITECC4;
|
||||
dv_reg NANDERRADD1;
|
||||
dv_reg NANDERRADD2;
|
||||
dv_reg NANDERRVAL1;
|
||||
dv_reg NANDERRVAL2;
|
||||
} emif_registers;
|
||||
|
||||
typedef emif_registers *emifregs;
|
||||
|
|
|
@ -324,6 +324,12 @@
|
|||
#define CONFIG_SYS_DTT_HYSTERESIS 3
|
||||
#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
|
||||
|
||||
#if defined(CONFIG_CMD_NAND)
|
||||
#define CONFIG_NAND_KMETER1
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE CONFIG_SYS_PIGGY_BASE
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
#define CONFIG_CMD_PCI
|
||||
#endif
|
||||
|
|
|
@ -128,6 +128,7 @@ typedef enum {
|
|||
NAND_ECC_SOFT,
|
||||
NAND_ECC_HW,
|
||||
NAND_ECC_HW_SYNDROME,
|
||||
NAND_ECC_HW_OOB_FIRST,
|
||||
} nand_ecc_modes_t;
|
||||
|
||||
/*
|
||||
|
@ -268,13 +269,13 @@ struct nand_ecc_ctrl {
|
|||
uint8_t *calc_ecc);
|
||||
int (*read_page_raw)(struct mtd_info *mtd,
|
||||
struct nand_chip *chip,
|
||||
uint8_t *buf);
|
||||
uint8_t *buf, int page);
|
||||
void (*write_page_raw)(struct mtd_info *mtd,
|
||||
struct nand_chip *chip,
|
||||
const uint8_t *buf);
|
||||
int (*read_page)(struct mtd_info *mtd,
|
||||
struct nand_chip *chip,
|
||||
uint8_t *buf);
|
||||
uint8_t *buf, int page);
|
||||
int (*read_subpage)(struct mtd_info *mtd,
|
||||
struct nand_chip *chip,
|
||||
uint32_t offs, uint32_t len,
|
||||
|
|
Loading…
Add table
Reference in a new issue