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at91: remove all occourances of CONFIG_AT91_LEGACY
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This commit is contained in:
Andreas Bießmann
parent
1bcdde2499
commit
58fd563ffb
8 changed files with 13 additions and 246 deletions
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@ -151,37 +151,4 @@ int at91_get_pio_value(unsigned port, unsigned pin);
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#define AT91_PIO_PORTD 0x3
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#define AT91_PIO_PORTE 0x4
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#ifdef CONFIG_AT91_LEGACY
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#define PIO_PER 0x00 /* Enable Register */
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#define PIO_PDR 0x04 /* Disable Register */
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#define PIO_PSR 0x08 /* Status Register */
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#define PIO_OER 0x10 /* Output Enable Register */
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#define PIO_ODR 0x14 /* Output Disable Register */
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#define PIO_OSR 0x18 /* Output Status Register */
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#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
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#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
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#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
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#define PIO_SODR 0x30 /* Set Output Data Register */
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#define PIO_CODR 0x34 /* Clear Output Data Register */
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#define PIO_ODSR 0x38 /* Output Data Status Register */
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#define PIO_PDSR 0x3c /* Pin Data Status Register */
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#define PIO_IER 0x40 /* Interrupt Enable Register */
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#define PIO_IDR 0x44 /* Interrupt Disable Register */
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#define PIO_IMR 0x48 /* Interrupt Mask Register */
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#define PIO_ISR 0x4c /* Interrupt Status Register */
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#define PIO_MDER 0x50 /* Multi-driver Enable Register */
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#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
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#define PIO_MDSR 0x58 /* Multi-driver Status Register */
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#define PIO_PUDR 0x60 /* Pull-up Disable Register */
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#define PIO_PUER 0x64 /* Pull-up Enable Register */
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#define PIO_PUSR 0x68 /* Pull-up Status Register */
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#define PIO_ASR 0x70 /* Peripheral A Select Register */
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#define PIO_BSR 0x74 /* Peripheral B Select Register */
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#define PIO_ABSR 0x78 /* AB Status Register */
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#define PIO_OWER 0xa0 /* Output Write Enable Register */
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#define PIO_OWDR 0xa4 /* Output Write Disable Register */
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#define PIO_OWSR 0xa8 /* Output Write Status Register */
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#endif
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#endif
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@ -25,20 +25,4 @@ typedef struct at91_pit {
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#define AT91_PIT_MR_PIV_MASK(x) (x & 0x000fffff)
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#define AT91_PIT_MR_PIV(x) (x & AT91_PIT_MR_PIV_MASK)
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#ifdef CONFIG_AT91_LEGACY
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#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */
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#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
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#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
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#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
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#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */
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#define AT91_PIT_PITS (1 << 0) /* Timer Status */
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#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */
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#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */
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#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
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#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */
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#endif /* CONFIG_AT91_LEGACY */
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#endif
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@ -14,13 +14,15 @@
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#ifndef AT91_PMC_H
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#define AT91_PMC_H
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#ifdef __ASSEMBLY__
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#define AT91_ASM_PMC_MOR (ATMEL_BASE_PMC + 0x20)
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#define AT91_ASM_PMC_PLLAR (ATMEL_BASE_PMC + 0x28)
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#define AT91_ASM_PMC_PLLBR (ATMEL_BASE_PMC + 0x2c)
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#define AT91_ASM_PMC_MCKR (ATMEL_BASE_PMC + 0x30)
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#define AT91_ASM_PMC_SR (ATMEL_BASE_PMC + 0x68)
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#ifndef __ASSEMBLY__
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#else
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#include <asm/types.h>
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@ -137,13 +139,6 @@ typedef struct at91_pmc {
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#define AT91_PMC_IXR_PCKRDY2 0x00000400
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#define AT91_PMC_IXR_PCKRDY3 0x00000800
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#ifdef CONFIG_AT91_LEGACY
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#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
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#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
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#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
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#endif
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#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
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#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
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#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
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@ -159,34 +154,18 @@ typedef struct at91_pmc {
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#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
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#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
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#ifdef CONFIG_AT91_LEGACY
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#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
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#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
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#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
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#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */
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#endif
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#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
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#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
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#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
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#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */
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#ifdef CONFIG_AT91_LEGACY
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#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
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#endif
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#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
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#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */
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#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
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#ifdef CONFIG_AT91_LEGACY
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#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
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#endif
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#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
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#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
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#ifdef CONFIG_AT91_LEGACY
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#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
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#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
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#endif
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#define AT91_PMC_DIV (0xff << 0) /* Divider */
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#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
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#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
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@ -198,9 +177,6 @@ typedef struct at91_pmc {
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#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
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#define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */
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#ifdef CONFIG_AT91_LEGACY
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#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
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#endif
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#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
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#define AT91_PMC_CSS_SLOW (0 << 0)
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#define AT91_PMC_CSS_MAIN (1 << 0)
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@ -228,9 +204,6 @@ typedef struct at91_pmc {
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#define AT91_PMC_PDIV_1 (0 << 12)
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#define AT91_PMC_PDIV_2 (1 << 12)
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#ifdef CONFIG_AT91_LEGACY
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#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register */
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#endif
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#define AT91_PMC_USBS_USB_PLLA (0x0) /* USB Clock Input is PLLA */
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#define AT91_PMC_USBS_USB_UPLL (0x1) /* USB Clock Input is UPLL */
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#define AT91_PMC_USBS_USB_PLLB (0x1) /* USB Clock Input is PLLB, AT91SAM9N12 only */
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@ -238,13 +211,6 @@ typedef struct at91_pmc {
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#define AT91_PMC_USBDIV_8 (0x7 << 8) /* USB Clock divided by 8 */
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#define AT91_PMC_USBDIV_10 (0x9 << 8) /* USB Clock divided by 10 */
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#ifdef CONFIG_AT91_LEGACY
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#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
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#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
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#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
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#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
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#endif
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#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
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#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
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#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
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@ -255,13 +221,6 @@ typedef struct at91_pmc {
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#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
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#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
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#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
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#ifdef CONFIG_AT91_LEGACY
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#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
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#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */
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#endif
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#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
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#ifdef CONFIG_AT91_LEGACY
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#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */
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#endif /* CONFIG_AT91_LEGACY */
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#endif
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@ -118,6 +118,6 @@ typedef struct at91_spi {
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#define AT91_SPI_PTSR 0x0124 /* PDC Transfer Status Register */
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#endif /* CONFIG_AT91_LEGACY */
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#endif /* CONFIG_ATMEL_LEGACY */
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#endif
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@ -40,25 +40,4 @@ typedef struct at91_wdt {
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#define AT91_WDT_MR_WDDBGHLT 0x10000000
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#define AT91_WDT_MR_WDIDLEHLT 0x20000000
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#ifdef CONFIG_AT91_LEGACY
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#define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */
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#define AT91_WDT_WDRSTT (1 << 0) /* Restart */
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#define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */
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#define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */
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#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */
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#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */
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#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */
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#define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */
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#define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */
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#define AT91_WDT_WDD (0xfff << 16) /* Delta Value */
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#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */
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#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */
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#define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */
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#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */
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#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */
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#endif /* CONFIG_AT91_LEGACY */
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#endif
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@ -55,75 +55,6 @@
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#define AT91_RSTC_BASE 0xfffffd00
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#define AT91_PIT_BASE 0xfffffd30
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#ifdef CONFIG_AT91_LEGACY
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/*
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* User Peripheral physical base addresses.
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*/
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#define AT91CAP9_BASE_UDPHS 0xfff78000
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#define AT91CAP9_BASE_TCB0 0xfff7c000
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#define AT91CAP9_BASE_TC0 0xfff7c000
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#define AT91CAP9_BASE_TC1 0xfff7c040
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#define AT91CAP9_BASE_TC2 0xfff7c080
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#define AT91CAP9_BASE_MCI0 0xfff80000
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#define AT91CAP9_BASE_MCI1 0xfff84000
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#define AT91CAP9_BASE_TWI 0xfff88000
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#define AT91CAP9_BASE_US0 0xfff8c000
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#define AT91CAP9_BASE_US1 0xfff90000
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#define AT91CAP9_BASE_US2 0xfff94000
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#define AT91CAP9_BASE_SSC0 0xfff98000
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#define AT91CAP9_BASE_SSC1 0xfff9c000
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#define AT91CAP9_BASE_AC97C 0xfffa0000
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#define AT91CAP9_BASE_SPI0 0xfffa4000
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#define AT91CAP9_BASE_SPI1 0xfffa8000
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#define AT91CAP9_BASE_CAN 0xfffac000
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#define AT91CAP9_BASE_PWMC 0xfffb8000
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#define AT91CAP9_BASE_EMAC 0xfffbc000
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#define AT91CAP9_BASE_ADC 0xfffc0000
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#define AT91CAP9_BASE_ISI 0xfffc4000
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#define AT91_BASE_SYS 0xffffe200
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/*
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* System Peripherals (offset from AT91_BASE_SYS)
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*/
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#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
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#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
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#define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS)
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#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
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#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
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#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS)
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#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
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#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
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#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
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#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
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#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
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#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
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#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
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#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
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#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
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#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
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#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
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#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
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#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
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#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
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#define AT91_GPBR_REVB (0xfffffd50 - AT91_BASE_SYS)
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#define AT91_GPBR_REVC (0xfffffd60 - AT91_BASE_SYS)
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#define AT91_USART0 AT91CAP9_BASE_US0
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#define AT91_USART1 AT91CAP9_BASE_US1
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#define AT91_USART2 AT91CAP9_BASE_US2
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/*
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* SCKCR flags
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*/
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#define AT91CAP9_SCKCR_RCEN (1 << 0) /* RC Oscillator Enable */
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#define AT91CAP9_SCKCR_OSC32EN (1 << 1) /* 32kHz Oscillator Enable */
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#define AT91CAP9_SCKCR_OSC32BYP (1 << 2) /* 32kHz Oscillator Bypass */
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#define AT91CAP9_SCKCR_OSCSEL (1 << 3) /* Slow Clock Selector */
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#define AT91CAP9_SCKCR_OSCSEL_RC (0 << 3)
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#define AT91CAP9_SCKCR_OSCSEL_32 (1 << 3)
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#endif /* CONFIG_AT91_LEGACY */
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/*
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* Internal Memory.
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*/
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@ -73,64 +73,4 @@ typedef struct at91_smc {
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#define AT91_SMC_MODE_PS_16 0x20000000
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#define AT91_SMC_MODE_PS_32 0x30000000
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#ifdef CONFIG_AT91_LEGACY
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#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
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#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
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#define AT91_SMC_NWESETUP_(x) ((x) << 0)
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#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
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#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
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#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
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#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
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#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
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#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
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#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
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#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
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#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
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#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
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#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
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#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
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#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
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#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
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#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
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#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
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#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
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#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
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#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
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#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
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#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
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||||
#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
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#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
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#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
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#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
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#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
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#define AT91_SMC_EXNWMODE_READY (3 << 4)
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||||
#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
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||||
#define AT91_SMC_BAT_SELECT (0 << 8)
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||||
#define AT91_SMC_BAT_WRITE (1 << 8)
|
||||
#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
|
||||
#define AT91_SMC_DBW_8 (0 << 12)
|
||||
#define AT91_SMC_DBW_16 (1 << 12)
|
||||
#define AT91_SMC_DBW_32 (2 << 12)
|
||||
#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
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||||
#define AT91_SMC_TDF_(x) ((x) << 16)
|
||||
#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
|
||||
#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
|
||||
#define AT91_SMC_PS (3 << 28) /* Page Size */
|
||||
#define AT91_SMC_PS_4 (0 << 28)
|
||||
#define AT91_SMC_PS_8 (1 << 28)
|
||||
#define AT91_SMC_PS_16 (2 << 28)
|
||||
#define AT91_SMC_PS_32 (3 << 28)
|
||||
|
||||
#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */
|
||||
#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
|
||||
#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
|
||||
#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
|
||||
#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -39,3 +39,10 @@ The method for updating
|
|||
3. add new structures for SoC access
|
||||
4. Convert arch, driver and boards file to new SoC
|
||||
5. remove legacy code, if all boards and drives are ready
|
||||
|
||||
2013-10-30 Andreas Bießmann <andreas.devel@googlemail.com>:
|
||||
|
||||
The goal is almost reached, we could remove the CONFIG_AT91_LEGACY switch but
|
||||
remain the CONFIG_ATMEL_LEGACY switch until the GPIO disaster is fixed. The
|
||||
AT91 spi driver has also some CONFIG_ATMEL_LEGACY stuff left, so another point
|
||||
to fix until this README can be removed.
|
||||
|
|
|
|||
Loading…
Reference in a new issue