mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 15:41:40 +00:00
serial: mxc: Move cr1 and cr2 write to mxc_serial_setbrg
Control reg write should be part of setbrg for better buadrate generation, so move cr1 and cr2 write to mxc_serial_setbrg Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
parent
62af03ee97
commit
57d3e98f57
1 changed files with 3 additions and 5 deletions
|
@ -162,6 +162,9 @@ static void mxc_serial_setbrg(void)
|
|||
writel(0xf, &mxc_base->bir);
|
||||
writel(clk / (2 * gd->baudrate), &mxc_base->bmr);
|
||||
|
||||
writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
|
||||
&mxc_base->cr2);
|
||||
writel(UCR1_UARTEN, &mxc_base->cr1);
|
||||
}
|
||||
|
||||
static int mxc_serial_getc(void)
|
||||
|
@ -216,11 +219,6 @@ static int mxc_serial_init(void)
|
|||
|
||||
serial_setbrg();
|
||||
|
||||
writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
|
||||
&mxc_base->cr2);
|
||||
|
||||
writel(UCR1_UARTEN, &mxc_base->cr1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in a new issue