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riscv: timer: Update the sifive clint timer driver to support aclint

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This RISC-V ACLINT specification [1] defines a set of memory mapped
devices which provide inter-processor interrupts (IPI) and timer
functionalities for each HART on a multi-HART RISC-V platform.

The RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, however the device tree binding
is a new one. This change updates the sifive clint timer driver to
support ACLINT mtimer device, using a per-driver data field to hold
the mtimer offset to the base address encoded in the mtimer node.

[1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
This commit is contained in:
Bin Meng 2023-06-21 23:11:44 +08:00 committed by Leo Yu-Chi Liang
parent c9745365f5
commit 5764acb261
4 changed files with 14 additions and 7 deletions
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16
drivers/timer/sifive_clint_timer.c
View file

@ -12,12 +12,16 @@
#include <dm/device-internal.h> #include <dm/device-internal.h>
#include <linux/err.h> #include <linux/err.h>
#define CLINT_MTIME_OFFSET 0xbff8
#define ACLINT_MTIME_OFFSET 0
/* mtime register */ /* mtime register */
#define MTIME_REG(base) ((ulong)(base) + 0xbff8) #define MTIME_REG(base, offset) ((ulong)(base) + (offset))
static u64 notrace sifive_clint_get_count(struct udevice *dev) static u64 notrace sifive_clint_get_count(struct udevice *dev)
{ {
return readq((void __iomem *)MTIME_REG(dev_get_priv(dev))); return readq((void __iomem *)MTIME_REG(dev_get_priv(dev),
dev_get_driver_data(dev)));
} }
#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY) #if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
@ -35,7 +39,8 @@ unsigned long notrace timer_early_get_rate(void)
*/ */
u64 notrace timer_early_get_count(void) u64 notrace timer_early_get_count(void)
{ {
return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE)); return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE,
RISCV_MMODE_TIMEROFF));
} }
#endif #endif
@ -53,8 +58,9 @@ static int sifive_clint_probe(struct udevice *dev)
} }
static const struct udevice_id sifive_clint_ids[] = { static const struct udevice_id sifive_clint_ids[] = {
{ .compatible = "riscv,clint0" }, { .compatible = "riscv,clint0", .data = CLINT_MTIME_OFFSET },
{ .compatible = "sifive,clint0" }, { .compatible = "sifive,clint0", .data = CLINT_MTIME_OFFSET },
{ .compatible = "riscv,aclint-mtimer", .data = ACLINT_MTIME_OFFSET },
{ } { }
}; };

2
include/configs/qemu-riscv.h
View file

@ -11,8 +11,8 @@
#define CFG_SYS_SDRAM_BASE 0x80000000 #define CFG_SYS_SDRAM_BASE 0x80000000
#define RISCV_MMODE_TIMERBASE 0x2000000 #define RISCV_MMODE_TIMERBASE 0x2000000
#define RISCV_MMODE_TIMEROFF 0xbff8
#define RISCV_MMODE_TIMER_FREQ 1000000 #define RISCV_MMODE_TIMER_FREQ 1000000
#define RISCV_SMODE_TIMER_FREQ 1000000 #define RISCV_SMODE_TIMER_FREQ 1000000
/* Environment options */ /* Environment options */

2
include/configs/sifive-unleashed.h
View file

@ -14,8 +14,8 @@
#define CFG_SYS_SDRAM_BASE 0x80000000 #define CFG_SYS_SDRAM_BASE 0x80000000
#define RISCV_MMODE_TIMERBASE 0x2000000 #define RISCV_MMODE_TIMERBASE 0x2000000
#define RISCV_MMODE_TIMEROFF 0xbff8
#define RISCV_MMODE_TIMER_FREQ 1000000 #define RISCV_MMODE_TIMER_FREQ 1000000
#define RISCV_SMODE_TIMER_FREQ 1000000 #define RISCV_SMODE_TIMER_FREQ 1000000
/* Environment options */ /* Environment options */

1
include/configs/starfive-visionfive2.h
View file

@ -9,6 +9,7 @@
#define _STARFIVE_VISIONFIVE2_H #define _STARFIVE_VISIONFIVE2_H
#define RISCV_MMODE_TIMERBASE 0x2000000 #define RISCV_MMODE_TIMERBASE 0x2000000
#define RISCV_MMODE_TIMEROFF 0xbff8
#define RISCV_MMODE_TIMER_FREQ 4000000 #define RISCV_MMODE_TIMER_FREQ 4000000
#define RISCV_SMODE_TIMER_FREQ 4000000 #define RISCV_SMODE_TIMER_FREQ 4000000