mirror of
https://github.com/AsahiLinux/u-boot
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sh: rsk7203: Remove the board
Last change to this board was done in 2016, has no prospects of ever being converted to DM, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
This commit is contained in:
Marek Vasut
Marek Vasut
parent
10e91cfdb0
commit
5736453c6f
8 changed files with 0 additions and 387 deletions
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@ -31,10 +31,6 @@ choice
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prompt "Target select"
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optional
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config TARGET_RSK7203
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bool "RSK+ 7203"
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select CPU_SH2A
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config TARGET_RSK7264
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bool "RSK2+SH7264"
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select CPU_SH2A
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@ -130,7 +126,6 @@ source "board/renesas/ap325rxa/Kconfig"
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source "board/renesas/r0p7734/Kconfig"
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source "board/renesas/r2dplus/Kconfig"
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source "board/renesas/r7780mp/Kconfig"
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source "board/renesas/rsk7203/Kconfig"
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source "board/renesas/rsk7264/Kconfig"
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source "board/renesas/rsk7269/Kconfig"
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source "board/renesas/sh7752evb/Kconfig"
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@ -1,12 +0,0 @@
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if TARGET_RSK7203
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config SYS_BOARD
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default "rsk7203"
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config SYS_VENDOR
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default "renesas"
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config SYS_CONFIG_NAME
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default "rsk7203"
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endif
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@ -1,7 +0,0 @@
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RSK7203 BOARD
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M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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S: Maintained
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F: board/renesas/rsk7203/
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F: include/configs/rsk7203.h
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F: configs/rsk7203_defconfig
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@ -1,10 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
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# Copyright (C) 2008 Renesas Solutions Corp.
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#
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# u-boot/board/rsk7203/Makefile
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#
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obj-y := rsk7203.o
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extra-y += lowlevel_init.o
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@ -1,199 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2008 Nobuhiro Iwamatsu
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* Copyright (C) 2008 Renesas Solutions Corp.
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*/
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#include <config.h>
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#include <asm/processor.h>
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#include <asm/macro.h>
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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/* Cache setting */
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write32 CCR1_A ,CCR1_D
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/* ConfigurePortPins */
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write16 PECRL3_A, PECRL3_D
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write16 PCCRL4_A, PCCRL4_D0
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write16 PECRL4_A, PECRL4_D0
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write16 PEIORL_A, PEIORL_D0
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write16 PCIORL_A, PCIORL_D
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write16 PFCRH2_A, PFCRH2_D
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write16 PFCRH3_A, PFCRH3_D
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write16 PFCRH1_A, PFCRH1_D
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write16 PFIORH_A, PFIORH_D
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write16 PECRL1_A, PECRL1_D0
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write16 PEIORL_A, PEIORL_D1
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/* Configure Operating Frequency */
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write16 WTCSR_A, WTCSR_D0
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write16 WTCSR_A, WTCSR_D1
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write16 WTCNT_A, WTCNT_D
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/* Set clock mode*/
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write16 FRQCR_A, FRQCR_D
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/* Configure Bus And Memory */
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init_bsc_cs0:
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write16 PCCRL4_A, PCCRL4_D1
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write16 PECRL1_A, PECRL1_D1
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write32 CMNCR_A, CMNCR_D
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write32 CS0BCR_A, CS0BCR_D
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write32 CS0WCR_A, CS0WCR_D
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init_bsc_cs1:
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write16 PECRL4_A, PECRL4_D1
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write32 CS1WCR_A, CS1WCR_D
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init_sdram:
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write16 PCCRL2_A, PCCRL2_D
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write16 PCCRL4_A, PCCRL4_D2
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write16 PCCRL1_A, PCCRL1_D
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write16 PCCRL3_A, PCCRL3_D
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write32 CS3BCR_A, CS3BCR_D
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write32 CS3WCR_A, CS3WCR_D
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write32 SDCR_A, SDCR_D
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write32 RTCOR_A, RTCOR_D
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write32 RTCSR_A, RTCSR_D
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/* wait 200us */
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mov.l REPEAT_D, r3
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mov #0, r2
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repeat0:
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add #1, r2
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cmp/hs r3, r2
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bf repeat0
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nop
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mov.l SDRAM_MODE, r1
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mov #0, r0
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mov.l r0, @r1
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nop
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rts
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.align 4
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CCR1_A: .long CCR1
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CCR1_D: .long 0x0000090B
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PCCRL4_A: .long 0xFFFE3910
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PCCRL4_D0: .word 0x0000
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.align 2
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PECRL4_A: .long 0xFFFE3A10
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PECRL4_D0: .word 0x0000
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.align 2
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PECRL3_A: .long 0xFFFE3A12
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PECRL3_D: .word 0x0000
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.align 2
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PEIORL_A: .long 0xFFFE3A06
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PEIORL_D0: .word 0x1C00
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PEIORL_D1: .word 0x1C02
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PCIORL_A: .long 0xFFFE3906
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PCIORL_D: .word 0x4000
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.align 2
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PFCRH2_A: .long 0xFFFE3A8C
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PFCRH2_D: .word 0x0000
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.align 2
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PFCRH3_A: .long 0xFFFE3A8A
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PFCRH3_D: .word 0x0000
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.align 2
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PFCRH1_A: .long 0xFFFE3A8E
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PFCRH1_D: .word 0x0000
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.align 2
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PFIORH_A: .long 0xFFFE3A84
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PFIORH_D: .word 0x0729
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.align 2
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PECRL1_A: .long 0xFFFE3A16
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PECRL1_D0: .word 0x0033
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.align 2
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WTCSR_A: .long 0xFFFE0000
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WTCSR_D0: .word 0xA518
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WTCSR_D1: .word 0xA51D
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WTCNT_A: .long 0xFFFE0002
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WTCNT_D: .word 0x5A84
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.align 2
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FRQCR_A: .long 0xFFFE0010
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FRQCR_D: .word 0x0104
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.align 2
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PCCRL4_D1: .word 0x0010
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PECRL1_D1: .word 0x0133
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CMNCR_A: .long 0xFFFC0000
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CMNCR_D: .long 0x00001810
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CS0BCR_A: .long 0xFFFC0004
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CS0BCR_D: .long 0x10000400
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CS0WCR_A: .long 0xFFFC0028
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CS0WCR_D: .long 0x00000B41
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PECRL4_D1: .word 0x0100
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.align 2
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CS1WCR_A: .long 0xFFFC002C
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CS1WCR_D: .long 0x00000B01
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PCCRL4_D2: .word 0x0011
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.align 2
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PCCRL3_A: .long 0xFFFE3912
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PCCRL3_D: .word 0x0011
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.align 2
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PCCRL2_A: .long 0xFFFE3914
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PCCRL2_D: .word 0x1111
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.align 2
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PCCRL1_A: .long 0xFFFE3916
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PCCRL1_D: .word 0x1010
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.align 2
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PDCRL4_A: .long 0xFFFE3990
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PDCRL4_D: .word 0x0011
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.align 2
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PDCRL3_A: .long 0xFFFE3992
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PDCRL3_D: .word 0x00011
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.align 2
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PDCRL2_A: .long 0xFFFE3994
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PDCRL2_D: .word 0x1111
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.align 2
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PDCRL1_A: .long 0xFFFE3996
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PDCRL1_D: .word 0x1000
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.align 2
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CS3BCR_A: .long 0xFFFC0010
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CS3BCR_D: .long 0x00004400
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CS3WCR_A: .long 0xFFFC0034
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CS3WCR_D: .long 0x00002892
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SDCR_A: .long 0xFFFC004C
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SDCR_D: .long 0x00000809
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RTCOR_A: .long 0xFFFC0058
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RTCOR_D: .long 0xA55A0041
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RTCSR_A: .long 0xFFFC0050
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RTCSR_D: .long 0xa55a0010
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SDRAM_MODE: .long 0xFFFC5040
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REPEAT_D: .long 0x00009C40
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@ -1,59 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2008 Nobuhiro Iwamatsu
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* Copyright (C) 2008 Renesas Solutions Corp.
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*
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* u-boot/board/rsk7203/rsk7203.c
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*/
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#include <common.h>
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#include <net.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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int checkboard(void)
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{
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puts("BOARD: Renesas Technology RSK7203\n");
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return 0;
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}
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int board_init(void)
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{
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return 0;
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}
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void led_set_state(unsigned short value)
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{
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}
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/*
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* The RSK board has the SMSC9118 wired up 'incorrectly'.
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* Byte-swapping is necessary, and so poor performance is inevitable.
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* This problem cannot evade by the swap function of CHIP, this can
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* evade by software Byte-swapping.
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* And this has problem by FIFO access only. pkt_data_pull/pkt_data_push
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* functions necessary to solve this problem.
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*/
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u32 pkt_data_pull(struct eth_device *dev, u32 addr)
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{
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volatile u16 *addr_16 = (u16 *)(dev->iobase + addr);
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return (u32)((swab16(*addr_16) << 16) & 0xFFFF0000)\
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| swab16(*(addr_16 + 1));
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}
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void pkt_data_push(struct eth_device *dev, u32 addr, u32 val)
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{
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addr += dev->iobase;
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*(volatile u16 *)(addr + 2) = swab16((u16)val);
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*(volatile u16 *)(addr) = swab16((u16)(val >> 16));
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}
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC911X
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#endif
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return rc;
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}
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@ -1,32 +0,0 @@
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CONFIG_SH=y
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CONFIG_SYS_TEXT_BASE=0xC7C0000
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CONFIG_TARGET_RSK7203=y
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="console=ttySC0,115200"
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CONFIG_VERSION_VARIABLE=y
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# CONFIG_CMDLINE_EDITING is not set
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# CONFIG_AUTO_COMPLETE is not set
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# CONFIG_AUTOBOOT is not set
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# CONFIG_CMD_BDI is not set
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# CONFIG_CMD_CONSOLE is not set
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# CONFIG_CMD_BOOTD is not set
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# CONFIG_CMD_RUN is not set
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# CONFIG_CMD_IMI is not set
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# CONFIG_CMD_XIMG is not set
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# CONFIG_CMD_EDITENV is not set
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# CONFIG_CMD_ENV_EXISTS is not set
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# CONFIG_CMD_LOADB is not set
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# CONFIG_CMD_LOADS is not set
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CONFIG_CMD_SDRAM=y
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# CONFIG_CMD_ECHO is not set
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# CONFIG_CMD_ITEST is not set
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# CONFIG_CMD_SOURCE is not set
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_PING=y
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CONFIG_CMD_CACHE=y
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# CONFIG_CMD_MISC is not set
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_SCIF_CONSOLE=y
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CONFIG_USE_PRIVATE_LIBGCC=y
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@ -1,63 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Configuation settings for the Renesas Technology RSK 7203
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*
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* Copyright (C) 2008 Nobuhiro Iwamatsu
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* Copyright (C) 2008 Renesas Solutions Corp.
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*/
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#ifndef __RSK7203_H
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#define __RSK7203_H
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#define CONFIG_CPU_SH7203 1
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#define CONFIG_LOADADDR 0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */
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#define CONFIG_DISPLAY_BOARDINFO
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#undef CONFIG_SHOW_BOOT_PROGRESS
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/* MEMORY */
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#define RSK7203_SDRAM_BASE 0x0C000000
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#define RSK7203_FLASH_BASE_1 0x20000000 /* Non cache */
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#define RSK7203_FLASH_BANK_SIZE (4 * 1024 * 1024)
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/* List of legal baudrate settings for this board */
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
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/* SCIF */
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#define CONFIG_CONS_SCIF0 1
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#define CONFIG_SYS_MEMTEST_START RSK7203_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (3 * 1024 * 1024))
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#define CONFIG_SYS_SDRAM_BASE RSK7203_SDRAM_BASE
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#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 1024 * 1024)
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#define CONFIG_SYS_MONITOR_BASE RSK7203_FLASH_BASE_1
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#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
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#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
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/* FLASH */
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#undef CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CONFIG_SYS_FLASH_BASE RSK7203_FLASH_BASE_1
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#define CONFIG_SYS_MAX_FLASH_SECT 64
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_ENV_SECT_SIZE (64 * 1024)
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#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_SYS_FLASH_ERASE_TOUT 12000
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 33333333
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
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#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
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#endif /* __RSK7203_H */
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