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doc: board: Add Intel Cherry Hill board doc

Browse source 
This extracts Intel Cherry Hill board specific information from
README.x86, converts plain text documentation to reST format and
adds it to Sphinx TOC tree. No essential content change.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Bin Meng 2019-07-18 00:34:07 -07:00 committed by Tom Rini
parent 14afa22e25
commit 5656d04537
3 changed files with 31 additions and 29 deletions
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29
doc/README.x86
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@ -226,35 +226,6 @@ to the last 2MB of the 8MB chip, address range [600000, 7FFFFF].
---
Intel Cherry Hill specific instructions for bare mode:
This uses Intel FSP for Braswell platform. Download it from Intel FSP website,
put the .fd file to the board directory and rename it to fsp.bin.
Extract descriptor.bin and me.bin from the original BIOS on the board using
ifdtool and put them to the board directory as well.
Note the FSP package for Braswell does not ship a traditional legacy VGA BIOS
image for the integrated graphics device. Instead a new binary called Video
BIOS Table (VBT) is shipped. Put it to the board directory and rename it to
vbt.bin if you want graphics support in U-Boot.
Now you can build U-Boot and obtain u-boot.rom
$ make cherryhill_defconfig
$ make all
An important note for programming u-boot.rom to the on-board SPI flash is that
you need make sure the SPI flash's 'quad enable' bit in its status register
matches the settings in the descriptor.bin, otherwise the board won't boot.
For the on-board SPI flash MX25U6435F, this can be done by writing 0x40 to the
status register by DediProg in: Config > Modify Status Register > Write Status
Register(s) > Register1 Value(Hex). This is is a one-time change. Once set, it
persists in SPI flash part regardless of the u-boot.rom image burned.
---
Intel Galileo instructions for bare mode:
Only one binary blob is needed for Remote Management Unit (RMU) within Intel

30
doc/board/intel/cherryhill.rst Normal file
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@ -0,0 +1,30 @@
.. SPDX-License-Identifier: GPL-2.0+
.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com>
Cherry Hill CRB
===============
This uses Intel FSP for Braswell platform. Download it from Intel FSP website,
put the .fd file to the board directory and rename it to fsp.bin.
Extract descriptor.bin and me.bin from the original BIOS on the board using
ifdtool and put them to the board directory as well.
Note the FSP package for Braswell does not ship a traditional legacy VGA BIOS
image for the integrated graphics device. Instead a new binary called Video
BIOS Table (VBT) is shipped. Put it to the board directory and rename it to
vbt.bin if you want graphics support in U-Boot.
Now you can build U-Boot and obtain u-boot.rom::
$ make cherryhill_defconfig
$ make all
An important note for programming u-boot.rom to the on-board SPI flash is that
you need make sure the SPI flash's 'quad enable' bit in its status register
matches the settings in the descriptor.bin, otherwise the board won't boot.
For the on-board SPI flash MX25U6435F, this can be done by writing 0x40 to the
status register by DediProg in: Config > Modify Status Register > Write Status
Register(s) > Register1 Value(Hex). This is is a one-time change. Once set, it
persists in SPI flash part regardless of the u-boot.rom image burned.

1
doc/board/intel/index.rst
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@ -7,5 +7,6 @@ Intel
:maxdepth: 2
bayleybay
cherryhill
crownbay
minnowmax