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board/freescale/mpc8266ads/mpc8266ads.c: CodingStyle cleanup
Make (mostly) checkpatch clean. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Rune Torgersen <runet@innovsys.com>
This commit is contained in:
Wolfgang Denk
parent
f58902d0aa
commit
55e33279ce
1 changed files with 290 additions and 276 deletions
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@ -1,5 +1,5 @@
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/*
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* (C) Copyright 2001
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* (C) Copyright 2001-2011
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Modified during 2001 by
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@ -280,7 +280,10 @@ phys_size_t initdram(int board_type)
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u_char cksum;
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int j;
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/* Keep the compiler from complaining about potentially uninitialized vars */
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/*
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* Keep the compiler from complaining about
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* potentially uninitialized vars
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*/
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data_width = rows = banks = cols = caslatency = 0;
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/*
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@ -291,57 +294,72 @@ phys_size_t initdram(int board_type)
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i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
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spd_size = data;
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cksum = data;
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for(j = 1; j < 64; j++)
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{ /* read only the checksummed bytes */
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for (j = 1; j < 64; j++) { /* read only the checksummed bytes */
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/* note: the I2C address autoincrements when alen == 0 */
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i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1);
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/*printf("addr %d = 0x%02x\n", j, data); */
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if(j == 5) chipselects = data & 0x0F;
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else if(j == 6) data_width = data;
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else if(j == 7) data_width |= data << 8;
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else if(j == 3) rows = data & 0x0F;
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else if(j == 4) cols = data & 0x0F;
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else if(j == 12)
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{
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if (j == 5)
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chipselects = data & 0x0F;
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else if (j == 6)
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data_width = data;
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else if (j == 7)
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data_width |= data << 8;
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else if (j == 3)
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rows = data & 0x0F;
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else if (j == 4)
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cols = data & 0x0F;
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else if (j == 12) {
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/*
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* Refresh rate: this assumes the prescaler is set to
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* approximately 0.39uSec per tick and the target refresh period
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* is about 85% of maximum.
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* approximately 0.39uSec per tick and the target
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* refresh period is about 85% of maximum.
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*/
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switch(data & 0x7F)
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{
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switch (data & 0x7F) {
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default:
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case 0: psrt = 0x21; /* 15.625uS */ break;
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case 1: psrt = 0x07; /* 3.9uS */ break;
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case 2: psrt = 0x0F; /* 7.8uS */ break;
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case 3: psrt = 0x43; /* 31.3uS */ break;
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case 4: psrt = 0x87; /* 62.5uS */ break;
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case 5: psrt = 0xFF; /* 125uS */ break;
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case 0:
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psrt = 0x21; /* 15.625uS */
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break;
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case 1:
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psrt = 0x07; /* 3.9uS */
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break;
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case 2:
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psrt = 0x0F; /* 7.8uS */
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break;
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case 3:
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psrt = 0x43; /* 31.3uS */
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break;
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case 4:
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psrt = 0x87; /* 62.5uS */
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break;
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case 5:
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psrt = 0xFF; /* 125uS */
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break;
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}
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}
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else if(j == 17) banks = data;
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else if(j == 18)
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{
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} else if (j == 17)
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banks = data;
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else if (j == 18) {
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caslatency = 3; /* default CL */
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#if (PESSIMISTIC_SDRAM)
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if((data & 0x04) != 0) caslatency = 3;
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else if((data & 0x02) != 0) caslatency = 2;
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else if((data & 0x01) != 0) caslatency = 1;
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if ((data & 0x04) != 0)
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caslatency = 3;
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else if ((data & 0x02) != 0)
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caslatency = 2;
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else if ((data & 0x01) != 0)
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caslatency = 1;
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#else
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if((data & 0x01) != 0) caslatency = 1;
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else if((data & 0x02) != 0) caslatency = 2;
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else if((data & 0x04) != 0) caslatency = 3;
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if ((data & 0x01) != 0)
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caslatency = 1;
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else if ((data & 0x02) != 0)
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caslatency = 2;
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else if ((data & 0x04) != 0)
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caslatency = 3;
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#endif
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else
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{
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else {
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printf("WARNING: Unknown CAS latency 0x%02X, using 3\n",
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data);
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}
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}
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else if(j == 63)
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{
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if(data != cksum)
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{
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} else if (j == 63) {
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if (data != cksum) {
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printf("WARNING: Configuration data checksum failure:"
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" is 0x%02x, calculated 0x%02x\n",
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data, cksum);
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@ -356,16 +374,17 @@ phys_size_t initdram(int board_type)
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caslatency = 2;
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}
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if (rows > 14) {
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printf("This doesn't look good, rows = %d, should be <= 14\n", rows);
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printf("This doesn't look good, rows = %d, should be <= 14\n",
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rows);
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rows = 14;
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}
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if (cols > 11) {
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printf("This doesn't look good, columns = %d, should be <= 11\n", cols);
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printf("This doesn't look good, columns = %d, should be <= 11\n",
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cols);
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cols = 11;
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}
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if((data_width != 64) && (data_width != 72))
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{
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if ((data_width != 64) && (data_width != 72)) {
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printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n",
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data_width);
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}
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@ -373,9 +392,12 @@ phys_size_t initdram(int board_type)
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/*
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* Convert banks into log2(banks)
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*/
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if (banks == 2) banks = 1;
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else if(banks == 4) banks = 2;
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else if(banks == 8) banks = 3;
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if (banks == 2)
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banks = 1;
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else if (banks == 4)
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banks = 2;
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else if (banks == 8)
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banks = 3;
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sdram_size = 1 << (rows + cols + banks + width);
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@ -383,18 +405,24 @@ phys_size_t initdram(int board_type)
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/* !!!!! Will ONLY work with Page Based Interleave !!!!!
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( PSDMR[PBI] = 1 )
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*/
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/* mamory actually has 11 column addresses, but the memory controller
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doesn't really care.
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the calculations that follow will however move the rows so that
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they are muxed one bit off if you use 11 bit columns.
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The solution is to tell the memory controller the correct size of the memory
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but change the number of columns to 10 afterwards.
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The 11th column addre will still be mucxed correctly onto the bus.
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Also be aware that the MPC8266ADS board Rev B has not connected
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Row address 13 to anything.
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The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126)
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/*
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* memory actually has 11 column addresses, but the memory
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* controller doesn't really care.
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*
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* the calculations that follow will however move the rows so
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* that they are muxed one bit off if you use 11 bit columns.
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*
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* The solution is to tell the memory controller the correct
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* size of the memory but change the number of columns to 10
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* afterwards.
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*
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* The 11th column addre will still be mucxed correctly onto
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* the bus.
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*
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* Also be aware that the MPC8266ADS board Rev B has not
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* connected Row address 13 to anything.
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*
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* The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126)
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*/
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if (cols > 10)
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cols = 10;
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@ -432,33 +460,19 @@ phys_size_t initdram(int board_type)
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sda10 = sdam;
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#endif
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#if (PESSIMISTIC_SDRAM)
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psdmr = (CONFIG_PBI |\
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PSDMR_RFEN |\
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PSDMR_RFRC_16_CLK |\
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PSDMR_PRETOACT_8W |\
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PSDMR_ACTTORW_8W |\
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PSDMR_WRC_4C |\
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PSDMR_EAMUX |\
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PSDMR_BUFCMD) |\
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caslatency |\
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((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
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(sdam << 24) |\
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(bsma << 21) |\
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(sda10 << 18);
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psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_16_CLK |
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PSDMR_PRETOACT_8W | PSDMR_ACTTORW_8W | PSDMR_WRC_4C |
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PSDMR_EAMUX | PSDMR_BUFCMD) | caslatency |
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((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */
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(sdam << 24) | (bsma << 21) | (sda10 << 18);
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#else
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psdmr = (CONFIG_PBI |\
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PSDMR_RFEN |\
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PSDMR_RFRC_7_CLK |\
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PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ \
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PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ \
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psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_7_CLK |
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PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */
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PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */
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PSDMR_WRC_1C | /* 1 clock + 7nSec */
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EAMUX |\
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BUFCMD) |\
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caslatency |\
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((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
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(sdam << 24) |\
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(bsma << 21) |\
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(sda10 << 18);
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EAMUX | BUFCMD) | caslatency |
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((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */
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(sdam << 24) | (bsma << 21) | (sda10 << 18);
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#endif
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/*printf("psdmr = 0x%08x\n", psdmr); */
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@ -505,8 +519,9 @@ phys_size_t initdram(int board_type)
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* The initial commands are executed by setting P/LSDMR[OP] and
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* accessing the SDRAM with a single-byte transaction."
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*
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* The appropriate BRx/ORx registers have already been set when we
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* get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
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* The appropriate BRx/ORx registers have already been set
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* when we get here. The SDRAM can be accessed at the address
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* CONFIG_SYS_SDRAM_BASE.
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*/
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memctl->memc_mptpr = CONFIG_SYS_MPTPR;
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@ -532,8 +547,7 @@ phys_size_t initdram(int board_type)
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* Do it a second time for the second set of chips if the DIMM has
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* two chip selects (double sided).
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*/
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if(chipselects > 1)
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{
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if (chipselects > 1) {
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ramaddr += sdram_size;
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memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size;
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@ -556,7 +570,8 @@ phys_size_t initdram(int board_type)
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/* print info */
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printf("SDRAM configuration read from SPD\n");
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printf("\tSize per side = %dMB\n", sdram_size >> 20);
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printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n", chipselects, 1<<(banks), cols, rows, data_width);
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printf("\tOrganization: %d sides, %d banks, %d Columns, %d Rows, Data width = %d bits\n",
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chipselects, 1 << (banks), cols, rows, data_width);
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printf("\tRefresh rate = %d, CAS latency = %d", psrt, caslatency);
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#if (CONFIG_PBI == 0) /* bank-based interleaving */
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printf(", Using Bank Based Interleave\n");
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@ -569,10 +584,9 @@ phys_size_t initdram(int board_type)
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* Not needed for any other memory configuration */
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if ((sdram_size * chipselects) == (16 * 1024 * 1024))
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udelay(250000);
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return (sdram_size * chipselects);
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/*return (16 * 1024 * 1024);*/
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}
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return sdram_size * chipselects;
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}
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#ifdef CONFIG_PCI
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struct pci_controller hose;
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