diff --git a/Kconfig b/Kconfig index c8c22555a9..2ea735d38e 100644 --- a/Kconfig +++ b/Kconfig @@ -540,7 +540,7 @@ config PLATFORM_ELFENTRY config STACK_SIZE hex "Define max stack size that can be used by U-Boot" - default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP + default 0x4000000 if ARCH_VERSAL_NET || ARCH_VERSAL || ARCH_ZYNQMP default 0x200000 if MICROBLAZE default 0x1000000 help diff --git a/MAINTAINERS b/MAINTAINERS index d9f9ade7a3..b4b185aacd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -635,6 +635,13 @@ F: arch/arm/mach-uniphier/ F: configs/uniphier_*_defconfig N: uniphier +ARM VERSAL NET +M: Michal Simek +S: Maintained +T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git +F: arch/arm/mach-versal-net/ +N: (? S: Maintained diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9a6c2e8101..2e83394052 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1251,6 +1251,18 @@ config ARCH_VERSAL imply BOARD_LATE_INIT imply ENV_VARS_UBOOT_RUNTIME_CONFIG +config ARCH_VERSAL_NET + bool "Support Xilinx Keystone Platform" + select ARM64 + select CLK + select DM + select DM_ETH if NET + select DM_MMC if MMC + select DM_SERIAL + select OF_CONTROL + imply BOARD_LATE_INIT + imply ENV_VARS_UBOOT_RUNTIME_CONFIG + config ARCH_VF610 bool "Freescale Vybrid" select CPU_V7A @@ -2300,6 +2312,8 @@ source "arch/arm/mach-zynqmp/Kconfig" source "arch/arm/mach-versal/Kconfig" +source "arch/arm/mach-versal-net/Kconfig" + source "arch/arm/mach-zynqmp-r5/Kconfig" source "arch/arm/cpu/armv7/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 1f4a1d5788..ac602aed9c 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -88,6 +88,7 @@ machine-$(CONFIG_ARCH_OCTEONTX) += octeontx machine-$(CONFIG_ARCH_OCTEONTX2) += octeontx2 machine-$(CONFIG_ARCH_UNIPHIER) += uniphier machine-$(CONFIG_ARCH_VERSAL) += versal +machine-$(CONFIG_ARCH_VERSAL_NET) += versal-net machine-$(CONFIG_ARCH_ZYNQ) += zynq machine-$(CONFIG_ARCH_ZYNQMP) += zynqmp machine-$(CONFIG_ARCH_ZYNQMP_R5) += zynqmp-r5 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 885ed5ef6f..71e9bd4da3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -383,6 +383,9 @@ dtb-$(CONFIG_ARCH_VERSAL) += \ versal-mini-emmc0.dtb \ versal-mini-emmc1.dtb \ xilinx-versal-virt.dtb +dtb-$(CONFIG_ARCH_VERSAL_NET) += \ + versal-net-mini.dtb \ + xilinx-versal-net-virt.dtb dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \ zynqmp-r5.dtb dtb-$(CONFIG_AM33XX) += \ diff --git a/arch/arm/dts/versal-net-mini.dts b/arch/arm/dts/versal-net-mini.dts new file mode 100644 index 0000000000..8c29a6ed6b --- /dev/null +++ b/arch/arm/dts/versal-net-mini.dts @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal NET + * + * Copyright (C) 2021 - 2022, Xilinx, Inc. + * Copyright (C) 2022, Advanced Micro Devices, Inc. + * + * Michal Simek + */ + +/dts-v1/; + +#include + +/ { + compatible = "xlnx,versal-net-mini"; + model = "Xilinx Versal NET MINI"; + #address-cells = <2>; + #size-cells = <2>; + + memory: memory@0 { + reg = <0 0xBBF00000 0 0x100000>, <0 0 0 0x80000000>; + device_type = "memory"; + }; + + aliases { + /* serial0 = &serial0; */ + serial0 = &dcc; + }; + + chosen { + stdout-path = "serial0:115200"; + }; + + clk1: clk1 { + u-boot,dm-pre-reloc; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "okay"; + u-boot,dm-pre-reloc; + }; + + amba: axi { + compatible = "simple-bus"; + u-boot,dm-pre-reloc; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + serial0: serial@f1920000 { + u-boot,dm-pre-reloc; + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0xf1920000 0 0x1000>; + reg-io-width = <4>; + clock-names = "uartclk", "apb_pclk"; + clocks = <&clk1>, <&clk1>; + clock = <1000000>; + current-speed = <115200>; + skip-init; + }; + }; +}; diff --git a/arch/arm/dts/xilinx-versal-net-virt.dts b/arch/arm/dts/xilinx-versal-net-virt.dts new file mode 100644 index 0000000000..c99257cb08 --- /dev/null +++ b/arch/arm/dts/xilinx-versal-net-virt.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Empty device tree for versal-net-virt board + * + * Copyright (C) 2022, Advanced Micro Devices, Inc. + */ + +/dts-v1/; + +/ { +}; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index a4e92c8bb1..9d8e551ed2 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -200,13 +200,19 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@21 { - reg = <21>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; - /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@21 { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <21>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 1418cffb20..b9d82afc51 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -109,12 +109,19 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 7fd19ca3a8..6f24e335a1 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -114,12 +114,19 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index e412992ff1..2e95f22c3f 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -172,12 +172,19 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u22 6 GPIO_ACTIVE_LOW>; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index c5cdd58af6..7e7e1577eb 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -169,12 +169,19 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index caae16965d..35a30971cb 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -176,15 +176,21 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + reset-gpios = <&tca6416_u15 6 GPIO_ACTIVE_LOW>; + }; }; }; - &gpio { status = "okay"; gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ diff --git a/arch/arm/mach-versal-net/Kconfig b/arch/arm/mach-versal-net/Kconfig new file mode 100644 index 0000000000..62825e189f --- /dev/null +++ b/arch/arm/mach-versal-net/Kconfig @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: GPL-2.0 + +if ARCH_VERSAL_NET + +config SYS_BOARD + string "Board name" + default "versal-net" + +config SYS_VENDOR + string "Vendor name" + default "xilinx" + +config SYS_SOC + default "versal-net" + +config SYS_CONFIG_NAME + string "Board configuration name" + default "xilinx_versal_net" + help + This option contains information about board configuration name. + Based on this option include/configs/.h header + will be used for board configuration. + +config SYS_MEM_RSVD_FOR_MMU + bool "Reserve memory for MMU Table" + help + If defined this option is used to setup different space for + MMU table than the one which will be allocated during + relocation. + +config GICV3 + def_bool y + +config SYS_MALLOC_LEN + default 0x2000000 + +config ZYNQ_SDHCI_MAX_FREQ + default 200000000 + +source "board/xilinx/Kconfig" +source "board/xilinx/versal-net/Kconfig" + +endif diff --git a/arch/arm/mach-versal-net/Makefile b/arch/arm/mach-versal-net/Makefile new file mode 100644 index 0000000000..e12c4c0e67 --- /dev/null +++ b/arch/arm/mach-versal-net/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2021 - 2022, Xilinx, Inc. +# Copyright (C) 2022, Advanced Micro Devices, Inc. +# +# Michal Simek +# + +obj-y += clk.o +obj-y += cpu.o diff --git a/arch/arm/mach-versal-net/clk.c b/arch/arm/mach-versal-net/clk.c new file mode 100644 index 0000000000..d097de7afa --- /dev/null +++ b/arch/arm/mach-versal-net/clk.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 - 2022, Xilinx, Inc. + * Copyright (C) 2022, Advanced Micro Devices, Inc. + * + * Michal Simek + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_CLOCKS +/** + * set_cpu_clk_info - Initialize clock framework + * + * Return: 0 always. + * + * This function is called from common code after relocation and sets up the + * clock framework. The framework must not be used before this function had been + * called. + */ +int set_cpu_clk_info(void) +{ + gd->cpu_clk = get_tbclk(); + + gd->bd->bi_arm_freq = gd->cpu_clk / 1000000; + gd->bd->bi_dsp_freq = 0; + + return 0; +} +#endif diff --git a/arch/arm/mach-versal-net/cpu.c b/arch/arm/mach-versal-net/cpu.c new file mode 100644 index 0000000000..4c9b15411d --- /dev/null +++ b/arch/arm/mach-versal-net/cpu.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 - 2022, Xilinx, Inc. + * Copyright (C) 2022, Advanced Micro Devices, Inc. + * + * Michal Simek + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define VERSAL_NET_MEM_MAP_USED 5 + +#define DRAM_BANKS CONFIG_NR_DRAM_BANKS + +/* +1 is end of list which needs to be empty */ +#define VERSAL_NET_MEM_MAP_MAX (VERSAL_NET_MEM_MAP_USED + DRAM_BANKS + 1) + +static struct mm_region versal_mem_map[VERSAL_NET_MEM_MAP_MAX] = { + { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x70000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0xf0000000UL, + .phys = 0xf0000000UL, + .size = 0x0fe00000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x400000000UL, + .phys = 0x400000000UL, + .size = 0x200000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x600000000UL, + .phys = 0x600000000UL, + .size = 0x800000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xe00000000UL, + .phys = 0xe00000000UL, + .size = 0xf200000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + } +}; + +void mem_map_fill(void) +{ + int banks = VERSAL_NET_MEM_MAP_USED; + + for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + /* Zero size means no more DDR that's this is end */ + if (!gd->bd->bi_dram[i].size) + break; + + versal_mem_map[banks].virt = gd->bd->bi_dram[i].start; + versal_mem_map[banks].phys = gd->bd->bi_dram[i].start; + versal_mem_map[banks].size = gd->bd->bi_dram[i].size; + versal_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE; + banks = banks + 1; + } +} + +struct mm_region *mem_map = versal_mem_map; + +u64 get_page_table_size(void) +{ + return 0x14000; +} diff --git a/arch/arm/mach-versal-net/include/mach/hardware.h b/arch/arm/mach-versal-net/include/mach/hardware.h new file mode 100644 index 0000000000..808ce48fd1 --- /dev/null +++ b/arch/arm/mach-versal-net/include/mach/hardware.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 - 2022, Xilinx, Inc. + * Copyright (C) 2022, Advanced Micro Devices, Inc. + */ + +#ifndef __ASSEMBLY__ +#include +#endif + +#define PMC_TAP 0xF11A0000 + +#define PMC_TAP_IDCODE (PMC_TAP + 0) +#define PMC_TAP_VERSION (PMC_TAP + 0x4) +# define PMC_VERSION_MASK GENMASK(7, 0) +# define PS_VERSION_MASK GENMASK(15, 8) +# define RTL_VERSION_MASK GENMASK(23, 16) +# define PLATFORM_MASK GENMASK(27, 24) +# define PLATFORM_VERSION_MASK GENMASK(31, 28) +#define PMC_TAP_USERCODE (PMC_TAP + 0x8) + +enum versal_net_platform { + VERSAL_NET_SILICON = 0, + VERSAL_NET_SPP = 1, + VERSAL_NET_EMU = 2, + VERSAL_NET_QEMU = 3, +}; + +#define VERSAL_SLCR_BASEADDR 0xF1060000 +#define VERSAL_AXI_MUX_SEL (VERSAL_SLCR_BASEADDR + 0x504) +#define VERSAL_OSPI_LINEAR_MODE BIT(1) diff --git a/arch/arm/mach-versal-net/include/mach/sys_proto.h b/arch/arm/mach-versal-net/include/mach/sys_proto.h new file mode 100644 index 0000000000..5bba9030f2 --- /dev/null +++ b/arch/arm/mach-versal-net/include/mach/sys_proto.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 - 2022, Xilinx, Inc. + * Copyright (C) 2022, Advanced Micro Devices, Inc. + */ + +#include + +void mem_map_fill(void); + +static inline int zynqmp_mmio_write(const u32 address, const u32 mask, + const u32 value) +{ + BUILD_BUG(); + return -EINVAL; +} diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig index 1788066173..746a2332ad 100644 --- a/board/xilinx/Kconfig +++ b/board/xilinx/Kconfig @@ -42,7 +42,7 @@ endif config XILINX_OF_BOARD_DTB_ADDR hex "Default DTB pickup address" - default 0x1000 if ARCH_VERSAL + default 0x1000 if ARCH_VERSAL || ARCH_VERSAL_NET default 0x8000 if MICROBLAZE default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP depends on OF_BOARD || OF_SEPARATE @@ -51,10 +51,10 @@ config XILINX_OF_BOARD_DTB_ADDR config BOOT_SCRIPT_OFFSET hex "Boot script offset" - depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || MICROBLAZE + depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET || MICROBLAZE default 0xFC0000 if ARCH_ZYNQ || MICROBLAZE default 0x3E80000 if ARCH_ZYNQMP - default 0x7F80000 if ARCH_VERSAL + default 0x7F80000 if ARCH_VERSAL || ARCH_VERSAL_NET help Specifies distro boot script offset in NAND/QSPI/NOR flash. diff --git a/board/xilinx/versal-net/Kconfig b/board/xilinx/versal-net/Kconfig new file mode 100644 index 0000000000..8f94d2bb39 --- /dev/null +++ b/board/xilinx/versal-net/Kconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2020 - 2022, Xilinx, Inc. +# Copyright (C) 2022, Advanced Micro Devices, Inc. +# + +if ARCH_VERSAL_NET + +endif diff --git a/board/xilinx/versal-net/MAINTAINERS b/board/xilinx/versal-net/MAINTAINERS new file mode 100644 index 0000000000..50120a88d6 --- /dev/null +++ b/board/xilinx/versal-net/MAINTAINERS @@ -0,0 +1,8 @@ +XILINX_VERSAL_NET BOARDS +M: Michal Simek +S: Maintained +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git +F: arch/arm/dts/versal-net* +F: board/xilinx/versal-net/ +F: include/configs/xilinx_versal_net* +F: configs/xilinx_versal_net* diff --git a/board/xilinx/versal-net/Makefile b/board/xilinx/versal-net/Makefile new file mode 100644 index 0000000000..2008d4e231 --- /dev/null +++ b/board/xilinx/versal-net/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2021 - 2022, Xilinx, Inc. +# Copyright (C) 2022, Advanced Micro Devices, Inc. +# +# Michal Simek +# + +obj-y := board.o diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c new file mode 100644 index 0000000000..760031927f --- /dev/null +++ b/board/xilinx/versal-net/board.c @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 - 2022, Xilinx, Inc. + * Copyright (C) 2022, Advanced Micro Devices, Inc. + * + * Michal Simek + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/board.h" + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + printf("EL Level:\tEL%d\n", current_el()); + + return 0; +} + +static u32 platform_id, platform_version; + +char *soc_name_decode(void) +{ + char *name, *platform_name; + + switch (platform_id) { + case VERSAL_NET_SPP: + platform_name = "ipp"; + break; + case VERSAL_NET_EMU: + platform_name = "emu"; + break; + case VERSAL_NET_QEMU: + platform_name = "qemu"; + break; + default: + return NULL; + } + + /* + * --rev. are 6 chars + * max platform name is qemu which is 4 chars + * platform version number are 1+1 + * Plus 1 char for \n + */ + name = calloc(1, strlen(CONFIG_SYS_BOARD) + 13); + if (!name) + return NULL; + + sprintf(name, "%s-%s-rev%d.%d", CONFIG_SYS_BOARD, + platform_name, platform_version / 10, + platform_version % 10); + + return name; +} + +bool soc_detection(void) +{ + u32 version; + + version = readl(PMC_TAP_VERSION); + platform_id = FIELD_GET(PLATFORM_MASK, version); + + debug("idcode %x, version %x, usercode %x\n", + readl(PMC_TAP_IDCODE), version, + readl(PMC_TAP_USERCODE)); + + debug("pmc_ver %lx, ps version %lx, rtl version %lx\n", + FIELD_GET(PMC_VERSION_MASK, version), + FIELD_GET(PS_VERSION_MASK, version), + FIELD_GET(RTL_VERSION_MASK, version)); + + platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version); + + if (platform_id == VERSAL_NET_SPP || + platform_id == VERSAL_NET_EMU) { + /* + * 9 is diff for + * 0 means 0.9 version + * 1 means 1.0 version + * 2 means 1.1 version + * etc, + */ + platform_version += 9; + } + + debug("Platform id: %d version: %d.%d\n", platform_id, + platform_version / 10, platform_version % 10); + + return true; +} + +int board_early_init_f(void) +{ + if (IS_ENABLED(CONFIG_DEBUG_UART)) { + /* Uart debug for sure */ + debug_uart_init(); + puts("Debug uart enabled\n"); /* or printch() */ + } + + return 0; +} + +int board_early_init_r(void) +{ + return 0; +} + +int board_late_init(void) +{ + if (!(gd->flags & GD_FLG_ENV_DEFAULT)) { + debug("Saved variables - Skipping\n"); + return 0; + } + + if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG)) + return 0; + + return board_late_init_xilinx(); +} + +int dram_init_banksize(void) +{ + int ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + return ret; + + mem_map_fill(); + + return 0; +} + +int dram_init(void) +{ + int ret; + + if (CONFIG_IS_ENABLED(SYS_MEM_RSVD_FOR_MMU)) + ret = fdtdec_setup_mem_size_base(); + else + ret = fdtdec_setup_mem_size_base_lowest(); + + if (ret) + return -EINVAL; + + return 0; +} + +void reset_cpu(void) +{ +} diff --git a/configs/xilinx_versal_net_mini_defconfig b/configs/xilinx_versal_net_mini_defconfig new file mode 100644 index 0000000000..e8fa08e3ef --- /dev/null +++ b/configs/xilinx_versal_net_mini_defconfig @@ -0,0 +1,72 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_versal_net_mini" +CONFIG_SYS_ICACHE_OFF=y +# CONFIG_ARM64_CRC32 is not set +# CONFIG_ARM64_SUPPORT_AARCH32 is not set +CONFIG_ARCH_VERSAL_NET=y +CONFIG_SYS_TEXT_BASE=0xBBF10000 +CONFIG_SYS_MALLOC_LEN=0x20000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=3 +CONFIG_ENV_SIZE=0x80 +CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini" +CONFIG_SYS_PROMPT="Versal NET> " +CONFIG_SYS_MEM_RSVD_FOR_MMU=y +# CONFIG_PSCI_RESET is not set +CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x00001000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xBBF10000 +# CONFIG_EXPERT is not set +# CONFIG_LEGACY_IMAGE_FORMAT is not set +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +# CONFIG_AUTOBOOT is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +# CONFIG_BOARD_LATE_INIT is not set +# CONFIG_CMDLINE_EDITING is not set +# CONFIG_AUTO_COMPLETE is not set +# CONFIG_SYS_LONGHELP is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_RUN is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MX_CYCLIC=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +# CONFIG_CMD_SLEEP is not set +CONFIG_OF_EMBED=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +# CONFIG_DM_WARN is not set +# CONFIG_DM_DEVICE_REMOVE is not set +# CONFIG_GPIO is not set +# CONFIG_I2C is not set +# CONFIG_INPUT is not set +# CONFIG_MMC is not set +# CONFIG_POWER is not set +CONFIG_ARM_DCC=y +CONFIG_PL01X_SERIAL=y +# CONFIG_GZIP is not set diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig new file mode 100644 index 0000000000..4a9910b7c4 --- /dev/null +++ b/configs/xilinx_versal_net_virt_defconfig @@ -0,0 +1,131 @@ +CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864 +CONFIG_ARCH_VERSAL_NET=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x100000 +CONFIG_DEFAULT_DEVICE_TREE="xilinx-versal-net-virt" +CONFIG_SYS_PROMPT="Versal NET> " +CONFIG_CMD_FRU=y +CONFIG_SYS_LOAD_ADDR=0x8000000 +CONFIG_SYS_MEMTEST_START=0x00000000 +CONFIG_SYS_MEMTEST_END=0x00001000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_BOOTDELAY=5 +CONFIG_USE_PREBOOT=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_CLOCKS=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2073 +CONFIG_SYS_BOOTM_LEN=0x6400000 +CONFIG_CMD_BOOTMENU=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_DM=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_USB=y +CONFIG_BOOTP_MAY_FAIL=y +CONFIG_BOOTP_BOOTFILESIZE=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_SQUASHFS=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_OF_BOARD=y +CONFIG_DTB_RESELECT=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y +CONFIG_IP_DEFRAG=y +CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y +CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_CLK_VERSAL=y +CONFIG_DFU_RAM=y +CONFIG_ZYNQ_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_CADENCE=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_DM_MAILBOX=y +CONFIG_ZYNQMP_IPI=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x0 +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_ZYNQ_SDHCI_MIN_FREQ=100000 +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_MARVELL=y +CONFIG_PHY_NATSEMI=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_TI_DP83867=y +CONFIG_PHY_VITESSE=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_XILINX_AXIEMAC=y +CONFIG_ZYNQ_GEM=y +CONFIG_POWER_DOMAIN=y +CONFIG_ZYNQMP_POWER_DOMAIN=y +CONFIG_DM_RESET=y +CONFIG_RESET_ZYNQMP=y +CONFIG_ARM_DCC=y +CONFIG_PL01X_SERIAL=y +CONFIG_XILINX_UARTLITE=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_CADENCE_OSPI_VERSAL=y +CONFIG_ZYNQ_SPI=y +CONFIG_ZYNQMP_GQSPI=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Xilinx" +CONFIG_USB_GADGET_VENDOR_NUM=0x03FD +CONFIG_USB_GADGET_PRODUCT_NUM=0x0300 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_THOR=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index fd9e1a80c6..09aa97ee8c 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -184,7 +184,7 @@ config CLK_VERSACLOCK config CLK_VERSAL bool "Enable clock driver support for Versal" - depends on ARCH_VERSAL + depends on (ARCH_VERSAL || ARCH_VERSAL_NET) select ZYNQMP_FIRMWARE help This clock driver adds support for clock realted settings for diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index a9dd57b098..b2f62061ce 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -739,6 +739,7 @@ static struct clk_ops versal_clk_ops = { static const struct udevice_id versal_clk_ids[] = { { .compatible = "xlnx,versal-clk" }, + { .compatible = "xlnx,versal-net-clk" }, { } }; diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 76ddc6b4f4..d8e0d79c57 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -370,6 +370,7 @@ int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2, static const struct udevice_id zynqmp_firmware_ids[] = { { .compatible = "xlnx,zynqmp-firmware" }, { .compatible = "xlnx,versal-firmware"}, + { .compatible = "xlnx,versal-net-firmware"}, { } }; diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index acbdce11b7..47f24e0a02 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -54,7 +54,7 @@ config K3_SEC_PROXY config ZYNQMP_IPI bool "Xilinx ZynqMP IPI controller support" - depends on DM_MAILBOX && (ARCH_ZYNQMP || ARCH_VERSAL) + depends on DM_MAILBOX && (ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET) help This enables support for the Xilinx ZynqMP Inter Processor Interrupt communication controller. diff --git a/drivers/reset/reset-zynqmp.c b/drivers/reset/reset-zynqmp.c index 52c08c4722..87b4df5bf8 100644 --- a/drivers/reset/reset-zynqmp.c +++ b/drivers/reset/reset-zynqmp.c @@ -80,6 +80,7 @@ const struct reset_ops zynqmp_reset_ops = { static const struct udevice_id zynqmp_reset_ids[] = { { .compatible = "xlnx,zynqmp-reset" }, { .compatible = "xlnx,versal-reset" }, + { .compatible = "xlnx,versal-net-reset" }, { } }; diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 07e50e240e..2f12081f88 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -148,7 +148,7 @@ config CQSPI_REF_CLK config CADENCE_OSPI_VERSAL bool "Configure Versal OSPI" - depends on ARCH_VERSAL && CADENCE_QSPI + depends on (ARCH_VERSAL || ARCH_VERSAL_NET) && CADENCE_QSPI imply DM_GPIO help This option is used to enable Versal OSPI DMA operations which diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index a25c50bc50..a9547a8200 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -130,6 +130,7 @@ int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv) #if defined(CONFIG_DM_GPIO) int cadence_qspi_versal_flash_reset(struct udevice *dev) { +#ifndef CONFIG_ARCH_VERSAL_NET struct gpio_desc gpio; u32 reset_gpio; int ret; @@ -165,7 +166,7 @@ int cadence_qspi_versal_flash_reset(struct udevice *dev) /* Set value 1 to pin */ dm_gpio_set_value(&gpio, 1); udelay(1); - +#endif return 0; } #else diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 4e718c545c..d3cc8554b8 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -308,7 +308,8 @@ void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval) debug("%s, req_hz:%d, clk_rate:%d, baudrateval:%d\n", __func__, reqhz, clk_rate, baudrateval); - if (!IS_ENABLED(CONFIG_ARCH_VERSAL)) { + if (!(IS_ENABLED(CONFIG_ARCH_VERSAL) || + IS_ENABLED(CONFIG_ARCH_VERSAL_NET))) { if (reqhz <= GQSPI_FREQ_40MHZ) { tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE << TAP_DLY_BYPASS_LQSPI_RX_SHIFT; diff --git a/env/Kconfig b/env/Kconfig index 5329f7585b..24111dfaf4 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -558,7 +558,7 @@ config ENV_OFFSET default 0xF0000 if ARCH_SUNXI default 0xE0000 if ARCH_ZYNQ default 0x1E00000 if ARCH_ZYNQMP - default 0x7F40000 if ARCH_VERSAL + default 0x7F40000 if ARCH_VERSAL || ARCH_VERSAL_NET default 0 if ARC default 0x140000 if ARCH_AT91 default 0x260000 if ARCH_OMAP2PLUS @@ -583,7 +583,7 @@ config ENV_SIZE default 0x10000 if ARCH_SUNXI default 0x8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC default 0x2000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH - default 0x8000 if ARCH_ZYNQMP || ARCH_VERSAL + default 0x8000 if ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET default 0x4000 if ARC default 0x1f000 help @@ -593,7 +593,7 @@ config ENV_SECT_SIZE hex "Environment Sector-Size" depends on ENV_IS_IN_FLASH || ENV_IS_IN_SPI_FLASH default 0x2000 if ARCH_ROCKCHIP - default 0x40000 if ARCH_ZYNQMP || ARCH_VERSAL + default 0x40000 if ARCH_ZYNQMP || ARCH_VERSAL || ARCH_VERSAL_NET default 0x20000 if ARCH_ZYNQ || ARCH_OMAP2PLUS || ARCH_AT91 default 0x20000 if MICROBLAZE && ENV_IS_IN_SPI_FLASH default 0x10000 if ARCH_SUNXI && ENV_IS_IN_SPI_FLASH diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index 971bd69dec..8caf5394ed 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -23,10 +23,6 @@ EFI_GUID(0x20c5fba5, 0x0171, 0x457f, 0xb9, 0xcd, \ 0xf5, 0x12, 0x9c, 0xd0, 0x72, 0x28) -/* Miscellaneous configurable options */ - -/* Console I/O Buffer Size */ - #if defined(CONFIG_CMD_DFU) #define DFU_DEFAULT_POLL_TIMEOUT 300 #define CONFIG_THOR_RESET_OFF diff --git a/include/configs/xilinx_versal_net.h b/include/configs/xilinx_versal_net.h new file mode 100644 index 0000000000..0ccd38b7e6 --- /dev/null +++ b/include/configs/xilinx_versal_net.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Configuration for Xilinx Versal NET + * Copyright (C) 2016 - 2022, Xilinx, Inc. + * Copyright (C) 2022, Advanced Micro Devices, Inc. + * + * Michal Simek + * + * Based on Configuration for Xilinx ZynqMP + */ + +#ifndef __XILINX_VERSAL_NET_H +#define __XILINX_VERSAL_NET_H + +/* FIXME this is causing issue at least on IPP */ +/* #define CONFIG_ARMV8_SWITCH_TO_EL1 */ + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0xF9000000 +#define GICR_BASE 0xF9060000 + +/* Serial setup */ +#define CONFIG_SYS_BAUDRATE_TABLE \ + { 4800, 9600, 19200, 38400, 57600, 115200 } + +#if defined(CONFIG_CMD_DFU) +#define DFU_DEFAULT_POLL_TIMEOUT 300 +#define CONFIG_THOR_RESET_OFF +#define DFU_ALT_INFO_RAM \ + "dfu_ram_info=" \ + "setenv dfu_alt_info " \ + "Image ram 80000 $kernel_size_r\\\\;" \ + "system.dtb ram $fdt_addr_r $fdt_size_r\0" \ + "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \ + "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" + +#define DFU_ALT_INFO \ + DFU_ALT_INFO_RAM +#endif + +#if !defined(DFU_ALT_INFO) +# define DFU_ALT_INFO +#endif + +/* Ethernet driver */ +#if defined(CONFIG_ZYNQ_GEM) +# define PHY_ANEG_TIMEOUT 20000 +#endif + +#define ENV_MEM_LAYOUT_SETTINGS \ + "fdt_addr_r=0x40000000\0" \ + "fdt_size_r=0x400000\0" \ + "pxefile_addr_r=0x10000000\0" \ + "kernel_addr_r=0x18000000\0" \ + "kernel_size_r=0x10000000\0" \ + "kernel_comp_addr_r=0x30000000\0" \ + "kernel_comp_size=0x3C00000\0" \ + "scriptaddr=0x20000000\0" \ + "ramdisk_addr_r=0x02100000\0" \ + "script_size_f=0x80000\0" + +#if defined(CONFIG_MMC_SDHCI_ZYNQ) +# define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) +#else +# define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) +# define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) +#else +# define BOOT_TARGET_DEVICES_PXE(func) +#endif + +#if defined(CONFIG_CMD_DHCP) +# define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) +#else +# define BOOT_TARGET_DEVICES_DHCP(func) +#endif + +#if defined(CONFIG_ZYNQMP_GQSPI) || defined(CONFIG_CADENCE_OSPI_VERSAL_NET) +# define BOOT_TARGET_DEVICES_XSPI(func) func(XSPI, xspi, 0) +#else +# define BOOT_TARGET_DEVICES_XSPI(func) +#endif + +#define BOOTENV_DEV_XSPI(devtypeu, devtypel, instance) \ + "bootcmd_xspi0=sf probe 0 0 0 && " \ + "sf read $scriptaddr $script_offset_f $script_size_f && " \ + "echo XSPI: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo XSPI: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_XSPI(devtypeu, devtypel, instance) \ + "xspi0 " + +#define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na) + +#define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \ + "bootcmd_jtag=echo JTAG: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; echo JTAG: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \ + "jtag " + +#define BOOT_TARGET_DEVICES_DFU_USB(func) func(DFU_USB, dfu_usb, 0) + +#define BOOTENV_DEV_DFU_USB(devtypeu, devtypel, instance) \ + "bootcmd_dfu_usb=setenv dfu_alt_info boot.scr ram $scriptaddr " \ + "$script_size_f; dfu 0 ram 0 && " \ + "echo DFU: Trying to boot script at ${scriptaddr} && " \ + "source ${scriptaddr}; " \ + "echo DFU: SCRIPT FAILED: continuing...;\0" + +#define BOOTENV_DEV_NAME_DFU_USB(devtypeu, devtypel, instance) \ + "" + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_JTAG(func) \ + BOOT_TARGET_DEVICES_MMC(func) \ + BOOT_TARGET_DEVICES_XSPI(func) \ + BOOT_TARGET_DEVICES_DFU_USB(func) \ + BOOT_TARGET_DEVICES_PXE(func) \ + BOOT_TARGET_DEVICES_DHCP(func) + +#include + +/* Initial environment variables */ +#ifndef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + BOOTENV \ + DFU_ALT_INFO +#endif + +#endif /* __XILINX_VERSAL_NET_H */ diff --git a/include/configs/xilinx_versal_net_mini.h b/include/configs/xilinx_versal_net_mini.h new file mode 100644 index 0000000000..1939832a84 --- /dev/null +++ b/include/configs/xilinx_versal_net_mini.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Configuration for Xilinx Versal NET MINI configuration + * + * Copyright (C) 2018 - 2022, Xilinx, Inc. + * Copyright (C) 2022, Advanced Micro Devices, Inc. + * + * Michal Simek + */ + +#ifndef __CONFIG_VERSAL_NET_MINI_H +#define __CONFIG_VERSAL_NET_MINI_H + +#define CONFIG_EXTRA_ENV_SETTINGS + +#include + +/* Undef unneeded configs */ +#undef CONFIG_EXTRA_ENV_SETTINGS + +#endif /* __CONFIG_VERSAL_NET_MINI_H */