board/t104xrdb: Add support of CPLD

T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features.

This support of CPLD includes
 - files and register defintion
 - Commands to swtich alternate bank and default bank

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

board/freescale/t104xrdb/Makefile

@@ -6,6 +6,7 @@
 
 
 obj-y	+= t104xrdb.o
+obj-y	+= cpld.o
 obj-y	+= ddr.o
 obj-y	+= eth.o
 obj-$(CONFIG_PCI)	+= pci.o

board/freescale/t104xrdb/cpld.c

@@ -0,0 +1,112 @@
+/**
+ * Copyright 2014 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * This file provides support for the board-specific CPLD used on some Freescale
+ * reference boards.
+ *
+ * The following macros need to be defined:
+ *
+ * CONFIG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#include "cpld.h"
+
+u8 cpld_read(unsigned int reg)
+{
+	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+	return in_8(p + reg);
+}
+
+void cpld_write(unsigned int reg, u8 value)
+{
+	void *p = (void *)CONFIG_SYS_CPLD_BASE;
+
+	out_8(p + reg, value);
+}
+
+/**
+ * Set the boot bank to the alternate bank
+ */
+void cpld_set_altbank(void)
+{
+	u8 reg = CPLD_READ(flash_ctl_status);
+
+	reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
+
+	CPLD_WRITE(flash_ctl_status, reg);
+	CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
+}
+
+/**
+ * Set the boot bank to the default bank
+ */
+void cpld_set_defbank(void)
+{
+	u8 reg = CPLD_READ(flash_ctl_status);
+
+	reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
+
+	CPLD_WRITE(flash_ctl_status, reg);
+	CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
+}
+
+#ifdef DEBUG
+static void cpld_dump_regs(void)
+{
+	printf("cpld_ver	 = 0x%02x\n", CPLD_READ(cpld_ver));
+	printf("cpld_ver_sub	 = 0x%02x\n", CPLD_READ(cpld_ver_sub));
+	printf("hw_ver		 = 0x%02x\n", CPLD_READ(hw_ver));
+	printf("sw_ver		 = 0x%02x\n", CPLD_READ(sw_ver));
+	printf("reset_ctl1	 = 0x%02x\n", CPLD_READ(reset_ctl1));
+	printf("reset_ctl2	 = 0x%02x\n", CPLD_READ(reset_ctl2));
+	printf("int_status	 = 0x%02x\n", CPLD_READ(int_status));
+	printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status));
+	printf("fan_ctl_status	 = 0x%02x\n", CPLD_READ(fan_ctl_status));
+	printf("led_ctl_status	 = 0x%02x\n", CPLD_READ(led_ctl_status));
+	printf("sfp_ctl_status	 = 0x%02x\n", CPLD_READ(sfp_ctl_status));
+	printf("misc_ctl_status	 = 0x%02x\n", CPLD_READ(misc_ctl_status));
+	printf("boot_override	 = 0x%02x\n", CPLD_READ(boot_override));
+	printf("boot_config1	 = 0x%02x\n", CPLD_READ(boot_config1));
+	printf("boot_config2	 = 0x%02x\n", CPLD_READ(boot_config2));
+	putc('\n');
+}
+#endif
+
+int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int rc = 0;
+
+	if (argc <= 1)
+		return cmd_usage(cmdtp);
+
+	if (strcmp(argv[1], "reset") == 0) {
+		if (strcmp(argv[2], "altbank") == 0)
+			cpld_set_altbank();
+		else
+			cpld_set_defbank();
+#ifdef DEBUG
+	} else if (strcmp(argv[1], "dump") == 0) {
+		cpld_dump_regs();
+#endif
+	} else
+		rc = cmd_usage(cmdtp);
+
+	return rc;
+}
+
+U_BOOT_CMD(
+	cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
+	"Reset the board or alternate bank",
+	"reset - hard reset to default bank\n"
+	"cpld reset altbank - reset to alternate bank\n"
+#ifdef DEBUG
+	"cpld dump - display the CPLD registers\n"
+#endif
+	);

board/freescale/t104xrdb/cpld.h

@@ -0,0 +1,40 @@
+/**
+ * Copyright 2013 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * This file provides support for the ngPIXIS, a board-specific FPGA used on
+ * some Freescale reference boards.
+ */
+
+/*
+ * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
+ */
+struct cpld_data {
+	u8 cpld_ver;		/* 0x00 - CPLD Major Revision Register */
+	u8 cpld_ver_sub;	/* 0x01 - CPLD Minor Revision Register */
+	u8 hw_ver;		/* 0x02 - Hardware Revision Register */
+	u8 sw_ver;		/* 0x03 - Software Revision register */
+	u8 res0[12];		/* 0x04 - 0x0F - not used */
+	u8 reset_ctl1;		/* 0x10 - Reset control Register1 */
+	u8 reset_ctl2;		/* 0x11 - Reset control Register2 */
+	u8 int_status;		/* 0x12 - Interrupt status Register */
+	u8 flash_ctl_status;	/* 0x13 - Flash control and status register */
+	u8 fan_ctl_status;	/* 0x14 - Fan control and status register  */
+	u8 led_ctl_status;	/* 0x15 - LED control and status register */
+	u8 sfp_ctl_status;	/* 0x16 - SFP control and status register  */
+	u8 misc_ctl_status;	/* 0x17 - Miscellanies ctrl & status register*/
+	u8 boot_override;	/* 0x18 - Boot override register */
+	u8 boot_config1;	/* 0x19 - Boot config override register*/
+	u8 boot_config2;	/* 0x1A - Boot config override register*/
+} cpld_data_t;
+
+
+/* Pointer to the CPLD register set */
+
+u8 cpld_read(unsigned int reg);
+void cpld_write(unsigned int reg, u8 value);
+
+#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
+#define CPLD_WRITE(reg, value)\
+		cpld_write(offsetof(struct cpld_data, reg), value)

board/freescale/t104xrdb/t104xrdb.c

@@ -19,14 +19,27 @@
 #include <fm_eth.h>
 
 #include "t104xrdb.h"
+#include "cpld.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
 int checkboard(void)
 {
 	struct cpu_type *cpu = gd->arch.cpu;
+	u8 sw;
 
 	printf("Board: %sRDB\n", cpu->name);
+	printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
+	       CPLD_READ(hw_ver), CPLD_READ(sw_ver));
+
+	sw = CPLD_READ(flash_ctl_status);
+	sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
+
+	if (sw <= 7)
+		printf("vBank: %d\n", sw);
+	else
+		printf("Unsupported Bank=%x\n", sw);
+
 	return 0;
 }
 

include/configs/T104xRDB.h

@@ -179,6 +179,14 @@
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
 
 /* CPLD on IFC */
+#define CPLD_LBMAP_MASK			0x3F
+#define CPLD_BANK_SEL_MASK		0x07
+#define CPLD_BANK_OVERRIDE		0x40
+#define CPLD_LBMAP_ALTBANK		0x44 /* BANK OR | BANK 4 */
+#define CPLD_LBMAP_DFLTBANK		0x40 /* BANK OR | BANK0 */
+#define CPLD_LBMAP_RESET		0xFF
+#define CPLD_LBMAP_SHIFT		0x03
+
 #define CONFIG_SYS_CPLD_BASE	0xffdf0000
 #define CONFIG_SYS_CPLD_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 #define CONFIG_SYS_CSPR2_EXT	(0xf)