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sf: Enable byte program support
Enabled byte program support for sst flashes in sf. Few controllers will only support BP, so this patch gives a tx transfer flag to set the BP so-that sf will operate on byte program transfer. A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI controller to use byte program op for SST flash. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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74c2cee4e8
commit
54ba653ab6
4 changed files with 20 additions and 12 deletions
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@ -40,10 +40,13 @@ enum {
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SECT_4K = 1 << 0,
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SECT_32K = 1 << 1,
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E_FSR = 1 << 2,
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WR_QPP = 1 << 3,
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SST_BP = 1 << 3,
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SST_WP = 1 << 4,
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WR_QPP = 1 << 5,
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};
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#define SST_WR (SST_BP | SST_WP)
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#define SPI_FLASH_3B_ADDR_LEN 3
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#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
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#define SPI_FLASH_16MB_BOUN 0x1000000
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@ -89,16 +89,16 @@ const struct spi_flash_params spi_flash_params_table[] = {
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{"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K},
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#endif
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#ifdef CONFIG_SPI_FLASH_SST /* SST */
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{"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WP},
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{"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WP},
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{"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K | SST_WP},
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{"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K | SST_WP},
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{"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR},
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{"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WR},
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{"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K | SST_WR},
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{"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K | SST_WR},
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{"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
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{"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, RD_NORM, SECT_4K | SST_WP},
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{"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, RD_NORM, SECT_4K | SST_WP},
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{"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K | SST_WP},
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{"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WP},
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{"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WP},
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{"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, RD_NORM, SECT_4K | SST_WR},
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{"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, RD_NORM, SECT_4K | SST_WR},
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{"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K | SST_WR},
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{"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR},
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{"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WR},
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#endif
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#ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
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{"W25P80", 0xef2014, 0x0, 64 * 1024, 16, RD_NORM, 0},
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@ -136,8 +136,12 @@ static int spi_flash_validate_params(struct spi_slave *spi, u8 *idcode,
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#ifndef CONFIG_DM_SPI_FLASH
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flash->write = spi_flash_cmd_write_ops;
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#if defined(CONFIG_SPI_FLASH_SST)
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if (params->flags & SST_WP)
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flash->write = sst_write_wp;
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if (params->flags & SST_WR) {
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if (flash->spi->op_mode_tx & SPI_OPM_TX_BP)
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flash->write = sst_write_bp;
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else
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flash->write = sst_write_wp;
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}
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#endif
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flash->erase = spi_flash_cmd_erase_ops;
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flash->read = spi_flash_cmd_read_ops;
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@ -34,6 +34,7 @@
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/* SPI TX operation modes */
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#define SPI_OPM_TX_QPP (1 << 0)
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#define SPI_OPM_TX_BP (1 << 1)
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/* SPI RX operation modes */
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#define SPI_OPM_RX_AS (1 << 0)
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