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Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv

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- No need to check before free in kendryte clk.
- Only enable OF_BOARD_FIXUP if U-Boot is configured for S-Mode.
- Reduce k210 dts DMA block size
- Move timers into drivers/timer
- Correct fu540 dts reg size of clint node
This commit is contained in:
Tom Rini 2020-10-26 08:25:37 -04:00
commit 54908d9ae1
12 changed files with 66 additions and 54 deletions
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2
MAINTAINERS
View file

@ -938,6 +938,8 @@ S: Maintained
T: git https://gitlab.denx.de/u-boot/custodians/u-boot-riscv.git
F: arch/riscv/
F: cmd/riscv/
F: drivers/timer/andes_plmt_timer.c
F: drivers/timer/sifive_clint_timer.c
F: tools/prelink-riscv.c
RISC-V KENDRYTE

9
arch/riscv/Kconfig
View file

@ -170,13 +170,6 @@ config ANDES_PLIC
The Andes PLIC block holds memory-mapped claim and pending registers
associated with software interrupt.
config ANDES_PLMT
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE
help
The Andes PLMT block holds memory-mapped mtime register
associated with timer tick.
config SYS_MALLOC_F_LEN
default 0x1000
@ -272,6 +265,6 @@ config STACK_SIZE_SHIFT
default 14
config OF_BOARD_FIXUP
default y if OF_SEPARATE
default y if OF_SEPARATE && RISCV_SMODE
endmenu

2
arch/riscv/cpu/ax25/Kconfig
View file

@ -5,7 +5,7 @@ config RISCV_NDS
imply CPU_RISCV
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE)
imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE)
imply SPL_CPU_SUPPORT
imply SPL_OPENSBI
imply SPL_LOAD_FIT

2
arch/riscv/dts/fu540-c000-u-boot.dtsi
View file

@ -62,7 +62,7 @@
&cpu2_intc 3 &cpu2_intc 7
&cpu3_intc 3 &cpu3_intc 7
&cpu4_intc 3 &cpu4_intc 7>;
reg = <0x0 0x2000000 0x0 0xc0000>;
reg = <0x0 0x2000000 0x0 0x10000>;
u-boot,dm-spl;
};
prci: clock-controller@10000000 {

4
arch/riscv/dts/k210.dtsi
View file

@ -200,8 +200,8 @@
dma-channels = <6>;
snps,dma-masters = <2>;
snps,data-width = <5>;
snps,block-size = <0x400000 0x400000 0x400000
0x400000 0x400000 0x400000>;
snps,block-size = <0x200000 0x200000 0x200000
0x200000 0x200000 0x200000>;
snps,axi-max-burst-len = <256>;
status = "disabled";
};

1
arch/riscv/lib/Makefile
View file

@ -13,7 +13,6 @@ obj-y += cache.o
ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o
else
obj-$(CONFIG_SBI) += sbi.o
obj-$(CONFIG_SBI_IPI) += sbi_ipi.o

41
arch/riscv/lib/sifive_clint.c
View file

@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
*
* U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT).
@ -8,19 +9,13 @@
*/
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <timer.h>
#include <asm/io.h>
#include <asm/syscon.h>
#include <asm/smp.h>
#include <linux/err.h>
/* MSIP registers */
#define MSIP_REG(base, hart) ((ulong)(base) + (hart) * 4)
/* mtime compare register */
#define MTIMECMP_REG(base, hart) ((ulong)(base) + 0x4000 + (hart) * 8)
/* mtime register */
#define MTIME_REG(base) ((ulong)(base) + 0xbff8)
DECLARE_GLOBAL_DATA_PTR;
@ -61,35 +56,3 @@ int riscv_get_ipi(int hart, int *pending)
return 0;
}
static u64 sifive_clint_get_count(struct udevice *dev)
{
return readq((void __iomem *)MTIME_REG(dev->priv));
}
static const struct timer_ops sifive_clint_ops = {
.get_count = sifive_clint_get_count,
};
static int sifive_clint_probe(struct udevice *dev)
{
dev->priv = dev_read_addr_ptr(dev);
if (!dev->priv)
return -EINVAL;
return timer_timebase_fallback(dev);
}
static const struct udevice_id sifive_clint_ids[] = {
{ .compatible = "riscv,clint0" },
{ }
};
U_BOOT_DRIVER(sifive_clint) = {
.name = "sifive_clint",
.id = UCLASS_TIMER,
.of_match = sifive_clint_ids,
.probe = sifive_clint_probe,
.ops = &sifive_clint_ops,
.flags = DM_FLAG_PRE_RELOC,
};

3
drivers/clk/kendryte/clk.c
View file

@ -471,8 +471,7 @@ cleanup_gate:
cleanup_div:
free(div);
cleanup_mux:
if (mux)
free(mux);
free(mux);
return comp;
}

7
drivers/timer/Kconfig
View file

@ -53,6 +53,13 @@ config ALTERA_TIMER
Select this to enable a timer for Altera devices. Please find
details on the "Embedded Peripherals IP User Guide" of Altera.
config ANDES_PLMT_TIMER
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE
help
The Andes PLMT block holds memory-mapped mtime register
associated with timer tick.
config ARC_TIMER
bool "ARC timer support"
depends on TIMER && ARC && CLK

2
drivers/timer/Makefile
View file

@ -5,6 +5,7 @@
obj-y += timer-uclass.o
obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
obj-$(CONFIG_ANDES_PLMT_TIMER) += andes_plmt_timer.o
obj-$(CONFIG_ARC_TIMER) += arc_timer.o
obj-$(CONFIG_AST_TIMER) += ast_timer.o
obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o
@ -18,6 +19,7 @@ obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o
obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o
obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint_timer.o
obj-$(CONFIG_STI_TIMER) += sti-timer.o
obj-$(CONFIG_STM32_TIMER) += stm32_timer.o
obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o

0
arch/riscv/lib/andes_plmt.c → drivers/timer/andes_plmt_timer.c
View file

47
drivers/timer/sifive_clint_timer.c Normal file
View file

@ -0,0 +1,47 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
*/
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <timer.h>
#include <asm/io.h>
#include <linux/err.h>
/* mtime register */
#define MTIME_REG(base) ((ulong)(base) + 0xbff8)
static u64 sifive_clint_get_count(struct udevice *dev)
{
return readq((void __iomem *)MTIME_REG(dev->priv));
}
static const struct timer_ops sifive_clint_ops = {
.get_count = sifive_clint_get_count,
};
static int sifive_clint_probe(struct udevice *dev)
{
dev->priv = dev_read_addr_ptr(dev);
if (!dev->priv)
return -EINVAL;
return timer_timebase_fallback(dev);
}
static const struct udevice_id sifive_clint_ids[] = {
{ .compatible = "riscv,clint0" },
{ }
};
U_BOOT_DRIVER(sifive_clint) = {
.name = "sifive_clint",
.id = UCLASS_TIMER,
.of_match = sifive_clint_ids,
.probe = sifive_clint_probe,
.ops = &sifive_clint_ops,
.flags = DM_FLAG_PRE_RELOC,
};