mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
PCU_E: remove code for yet another corpse
The PCU_E board has long reached EOL, and support for it is no longer relevant in current versions of U-Boot. Remove it. Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk
parent
6f984adb31
commit
544d97e9aa
15 changed files with 9 additions and 2163 deletions
|
|
@ -117,7 +117,6 @@ Wolfgang Denk <wd@denx.de>
|
|||
c2mon MPC855
|
||||
hermes MPC860
|
||||
lwmon MPC823
|
||||
pcu_e MPC855
|
||||
|
||||
CU824 MPC8240
|
||||
Sandpoint8240 MPC8240
|
||||
|
|
|
|||
2
README
2
README
|
|
@ -1781,7 +1781,7 @@ The following options need to be configured:
|
|||
|
||||
ETX094, IVMS8, IVML24, SPD8xx, TQM8xxL,
|
||||
HERMES, IP860, RPXlite, LWMON, LANTEC,
|
||||
PCU_E, FLAGADM, TQM8260
|
||||
FLAGADM, TQM8260
|
||||
|
||||
- Error Recovery:
|
||||
CONFIG_PANIC_HANG
|
||||
|
|
|
|||
|
|
@ -73,10 +73,6 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
|
||||
static char *failed = "*** failed ***\n";
|
||||
|
||||
#ifdef CONFIG_PCU_E
|
||||
extern flash_info_t flash_info[];
|
||||
#endif
|
||||
|
||||
#include <environment.h>
|
||||
|
||||
extern ulong __init_end;
|
||||
|
|
|
|||
|
|
@ -156,7 +156,6 @@ void cpu_init_f (volatile immap_t * immr)
|
|||
defined(CONFIG_IVMS8) || \
|
||||
defined(CONFIG_LWMON) || \
|
||||
defined(CONFIG_MHPC) || \
|
||||
defined(CONFIG_PCU_E) || \
|
||||
defined(CONFIG_R360MPI) || \
|
||||
defined(CONFIG_RMU) || \
|
||||
defined(CONFIG_RPXCLASSIC) || \
|
||||
|
|
|
|||
|
|
@ -107,7 +107,7 @@ void doc_init (void);
|
|||
|
||||
static char *failed = "*** failed ***\n";
|
||||
|
||||
#if defined(CONFIG_OXC) || defined(CONFIG_PCU_E) || defined(CONFIG_RMU)
|
||||
#if defined(CONFIG_OXC) || defined(CONFIG_RMU)
|
||||
extern flash_info_t flash_info[];
|
||||
#endif
|
||||
|
||||
|
|
@ -735,7 +735,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
|
|||
#endif
|
||||
|
||||
|
||||
# if defined(CONFIG_PCU_E) || defined(CONFIG_OXC) || defined(CONFIG_RMU)
|
||||
# if defined(CONFIG_OXC) || defined(CONFIG_RMU)
|
||||
/* flash mapped at end of memory map */
|
||||
bd->bi_flashoffset = TEXT_BASE + flash_size;
|
||||
# elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
|
||||
|
|
|
|||
|
|
@ -1,44 +0,0 @@
|
|||
#
|
||||
# (C) Copyright 2001-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o flash.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -1,28 +0,0 @@
|
|||
#
|
||||
# (C) Copyright 2001
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# Siemens PCU E Boards
|
||||
#
|
||||
|
||||
TEXT_BASE = 0xFFF00000
|
||||
|
|
@ -1,700 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc8xx.h>
|
||||
|
||||
#if defined(CONFIG_ENV_IS_IN_FLASH)
|
||||
# ifndef CONFIG_ENV_ADDR
|
||||
# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
|
||||
# endif
|
||||
# ifndef CONFIG_ENV_SIZE
|
||||
# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
|
||||
# endif
|
||||
# ifndef CONFIG_ENV_SECT_SIZE
|
||||
# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/*---------------------------------------------------------------------*/
|
||||
#undef DEBUG_FLASH
|
||||
|
||||
#ifdef DEBUG_FLASH
|
||||
#define DEBUGF(fmt,args...) printf(fmt ,##args)
|
||||
#else
|
||||
#define DEBUGF(fmt,args...)
|
||||
#endif
|
||||
/*---------------------------------------------------------------------*/
|
||||
|
||||
|
||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
|
||||
static int write_data (flash_info_t *info, ulong dest, ulong data);
|
||||
static void flash_get_offsets (ulong base, flash_info_t *info);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*
|
||||
* The PCU E uses an address map where flash banks are aligned top
|
||||
* down, so that the "first" flash bank ends at top of memory, and
|
||||
* the monitor entry point is at address (0xFFF00100). The second
|
||||
* flash bank is mapped immediately below bank 0.
|
||||
*
|
||||
* This is NOT in conformance to the "official" memory map!
|
||||
*
|
||||
*/
|
||||
|
||||
#define PCU_MONITOR_BASE ( (flash_info[0].start[0] + flash_info[0].size - 1) \
|
||||
- (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE) )
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||
unsigned long base, size_b0, size_b1;
|
||||
int i;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
}
|
||||
|
||||
/* Static FLASH Bank configuration here - FIXME XXX */
|
||||
|
||||
/*
|
||||
* Warning:
|
||||
*
|
||||
* Since the PCU E memory map assigns flash banks top down,
|
||||
* we swap the numbering later if both banks are equipped,
|
||||
* so they look like a contiguous area of memory.
|
||||
*/
|
||||
DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
|
||||
|
||||
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
|
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
|
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
|
||||
size_b0, size_b0<<20);
|
||||
}
|
||||
|
||||
DEBUGF("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE6_PRELIM);
|
||||
size_b1 = flash_get_size((vu_long *)FLASH_BASE6_PRELIM, &flash_info[1]);
|
||||
|
||||
DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n", size_b0, size_b1);
|
||||
|
||||
if (size_b1 > size_b0) {
|
||||
printf ("## ERROR: "
|
||||
"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
|
||||
size_b1, size_b1<<20,
|
||||
size_b0, size_b0<<20
|
||||
);
|
||||
flash_info[0].flash_id = FLASH_UNKNOWN;
|
||||
flash_info[1].flash_id = FLASH_UNKNOWN;
|
||||
flash_info[0].sector_count = -1;
|
||||
flash_info[1].sector_count = -1;
|
||||
flash_info[0].size = 0;
|
||||
flash_info[1].size = 0;
|
||||
return (0);
|
||||
}
|
||||
|
||||
DEBUGF ("## Before remap: "
|
||||
"BR0: 0x%08x OR0: 0x%08x "
|
||||
"BR6: 0x%08x OR6: 0x%08x\n",
|
||||
memctl->memc_br0, memctl->memc_or0,
|
||||
memctl->memc_br6, memctl->memc_or6);
|
||||
|
||||
/* Remap FLASH according to real size */
|
||||
base = 0 - size_b0;
|
||||
memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
|
||||
memctl->memc_br0 = (base & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
|
||||
|
||||
DEBUGF("## BR0: 0x%08x OR0: 0x%08x\n",
|
||||
memctl->memc_br0, memctl->memc_or0);
|
||||
|
||||
/* Re-do sizing to get full correct info */
|
||||
size_b0 = flash_get_size((vu_long *)base, &flash_info[0]);
|
||||
base = 0 - size_b0;
|
||||
|
||||
flash_info[0].size = size_b0;
|
||||
|
||||
flash_get_offsets (base, &flash_info[0]);
|
||||
|
||||
/* monitor protection ON by default */
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
PCU_MONITOR_BASE,
|
||||
PCU_MONITOR_BASE+monitor_flash_len-1,
|
||||
&flash_info[0]);
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_FLASH
|
||||
/* ENV protection ON by default */
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
CONFIG_ENV_ADDR,
|
||||
CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
|
||||
&flash_info[0]);
|
||||
#endif
|
||||
|
||||
if (size_b1) {
|
||||
flash_info_t tmp_info;
|
||||
|
||||
memctl->memc_or6 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
|
||||
memctl->memc_br6 = ((base - size_b1) & BR_BA_MSK) |
|
||||
BR_PS_16 | BR_MS_GPCM | BR_V;
|
||||
|
||||
DEBUGF("## New BR6: 0x%08x OR6: 0x%08x\n",
|
||||
memctl->memc_br6, memctl->memc_or6);
|
||||
|
||||
/* Re-do sizing to get full correct info */
|
||||
size_b1 = flash_get_size((vu_long *)(base - size_b1),
|
||||
&flash_info[1]);
|
||||
base -= size_b1;
|
||||
|
||||
flash_get_offsets (base, &flash_info[1]);
|
||||
|
||||
flash_info[1].size = size_b1;
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_FLASH
|
||||
/* ENV protection ON by default */
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
CONFIG_ENV_ADDR,
|
||||
CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
|
||||
&flash_info[1]);
|
||||
#endif
|
||||
/*
|
||||
* Swap bank numbers so that addresses are in ascending order
|
||||
*/
|
||||
tmp_info = flash_info[0];
|
||||
flash_info[0] = flash_info[1];
|
||||
flash_info[1] = tmp_info;
|
||||
} else {
|
||||
memctl->memc_br1 = 0; /* invalidate bank */
|
||||
|
||||
flash_info[1].flash_id = FLASH_UNKNOWN;
|
||||
flash_info[1].sector_count = -1;
|
||||
}
|
||||
|
||||
|
||||
DEBUGF("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
|
||||
|
||||
return (size_b0 + size_b1);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static void flash_get_offsets (ulong base, flash_info_t *info)
|
||||
{
|
||||
int i;
|
||||
short n;
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
return;
|
||||
}
|
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD) {
|
||||
return;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_AMDL322T:
|
||||
case FLASH_AMDL323T:
|
||||
case FLASH_AMDL324T:
|
||||
/* set sector offsets for top boot block type */
|
||||
|
||||
base += info->size;
|
||||
i = info->sector_count;
|
||||
for (n=0; n<8; ++n) { /* 8 x 8k boot sectors */
|
||||
base -= 8 << 10;
|
||||
--i;
|
||||
info->start[i] = base;
|
||||
}
|
||||
while (i > 0) { /* 64k regular sectors */
|
||||
base -= 64 << 10;
|
||||
--i;
|
||||
info->start[i] = base;
|
||||
}
|
||||
return;
|
||||
case FLASH_AMDL322B:
|
||||
case FLASH_AMDL323B:
|
||||
case FLASH_AMDL324B:
|
||||
/* set sector offsets for bottom boot block type */
|
||||
for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
|
||||
info->start[i] = base;
|
||||
base += 8 << 10;
|
||||
}
|
||||
while (base < info->size) { /* 64k regular sectors */
|
||||
info->start[i] = base;
|
||||
base += 64 << 10;
|
||||
++i;
|
||||
}
|
||||
return;
|
||||
case FLASH_AMDL640:
|
||||
/* set sector offsets for dual boot block type */
|
||||
for (i=0; i<8; ++i) { /* 8 x 8k boot sectors */
|
||||
info->start[i] = base;
|
||||
base += 8 << 10;
|
||||
}
|
||||
n = info->sector_count - 8;
|
||||
while (i < n) { /* 64k regular sectors */
|
||||
info->start[i] = base;
|
||||
base += 64 << 10;
|
||||
++i;
|
||||
}
|
||||
while (i < info->sector_count) { /* 8 x 8k boot sectors */
|
||||
info->start[i] = base;
|
||||
base += 8 << 10;
|
||||
++i;
|
||||
}
|
||||
return;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
/* NOTREACHED */
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
void flash_print_info (flash_info_t *info)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("missing or unknown FLASH type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case FLASH_MAN_AMD: printf ("AMD "); break;
|
||||
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
|
||||
default: printf ("Unknown Vendor "); break;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case FLASH_AMDL322B: printf ("AM29DL322B (32 Mbit, bottom boot sect)\n");
|
||||
break;
|
||||
case FLASH_AMDL322T: printf ("AM29DL322T (32 Mbit, top boot sector)\n");
|
||||
break;
|
||||
case FLASH_AMDL323B: printf ("AM29DL323B (32 Mbit, bottom boot sect)\n");
|
||||
break;
|
||||
case FLASH_AMDL323T: printf ("AM29DL323T (32 Mbit, top boot sector)\n");
|
||||
break;
|
||||
case FLASH_AMDL324B: printf ("AM29DL324B (32 Mbit, bottom boot sect)\n");
|
||||
break;
|
||||
case FLASH_AMDL324T: printf ("AM29DL324T (32 Mbit, top boot sector)\n");
|
||||
break;
|
||||
case FLASH_AMDL640: printf ("AM29DL640D (64 Mbit, dual boot sector)\n");
|
||||
break;
|
||||
default: printf ("Unknown Chip Type 0x%lX\n",
|
||||
info->flash_id);
|
||||
break;
|
||||
}
|
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n",
|
||||
info->size >> 20, info->sector_count);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i=0; i<info->sector_count; ++i) {
|
||||
if ((i % 5) == 0)
|
||||
printf ("\n ");
|
||||
printf (" %08lX%s",
|
||||
info->start[i],
|
||||
info->protect[i] ? " (RO)" : " "
|
||||
);
|
||||
}
|
||||
printf ("\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH!
|
||||
*/
|
||||
|
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
|
||||
{
|
||||
short i;
|
||||
ushort value;
|
||||
vu_short *saddr = (vu_short *)addr;
|
||||
|
||||
/* Write auto select command: read Manufacturer ID */
|
||||
saddr[0x0555] = 0x00AA;
|
||||
saddr[0x02AA] = 0x0055;
|
||||
saddr[0x0555] = 0x0090;
|
||||
|
||||
value = saddr[0];
|
||||
|
||||
DEBUGF("Manuf. ID @ 0x%08lx: 0x%04x\n", (ulong)addr, value);
|
||||
|
||||
switch (value) {
|
||||
case (AMD_MANUFACT & 0xFFFF):
|
||||
info->flash_id = FLASH_MAN_AMD;
|
||||
break;
|
||||
case (FUJ_MANUFACT & 0xFFFF):
|
||||
info->flash_id = FLASH_MAN_FUJ;
|
||||
break;
|
||||
default:
|
||||
DEBUGF("Unknown Manufacturer ID\n");
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
return (0); /* no or unknown flash */
|
||||
}
|
||||
|
||||
value = saddr[1]; /* device ID */
|
||||
|
||||
DEBUGF("Device ID @ 0x%08lx: 0x%04x\n", (ulong)(&addr[1]), value);
|
||||
|
||||
switch (value) {
|
||||
|
||||
case (AMD_ID_DL322T & 0xFFFF):
|
||||
info->flash_id += FLASH_AMDL322T;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00400000;
|
||||
break; /* => 8 MB */
|
||||
|
||||
case (AMD_ID_DL322B & 0xFFFF):
|
||||
info->flash_id += FLASH_AMDL322B;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00400000;
|
||||
break; /* => 8 MB */
|
||||
|
||||
case (AMD_ID_DL323T & 0xFFFF):
|
||||
info->flash_id += FLASH_AMDL323T;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00400000;
|
||||
break; /* => 8 MB */
|
||||
|
||||
case (AMD_ID_DL323B & 0xFFFF):
|
||||
info->flash_id += FLASH_AMDL323B;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00400000;
|
||||
break; /* => 8 MB */
|
||||
|
||||
case (AMD_ID_DL324T & 0xFFFF):
|
||||
info->flash_id += FLASH_AMDL324T;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00400000;
|
||||
break; /* => 8 MB */
|
||||
|
||||
case (AMD_ID_DL324B & 0xFFFF):
|
||||
info->flash_id += FLASH_AMDL324B;
|
||||
info->sector_count = 71;
|
||||
info->size = 0x00400000;
|
||||
break; /* => 8 MB */
|
||||
case (AMD_ID_DL640 & 0xFFFF):
|
||||
info->flash_id += FLASH_AMDL640;
|
||||
info->sector_count = 142;
|
||||
info->size = 0x00800000;
|
||||
break;
|
||||
default:
|
||||
DEBUGF("Unknown Device ID\n");
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
return (0); /* => no or unknown flash */
|
||||
|
||||
}
|
||||
|
||||
flash_get_offsets ((ulong)addr, info);
|
||||
|
||||
/* check for protected sectors */
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
#if 0
|
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
|
||||
/* D0 = 1 if protected */
|
||||
saddr = (vu_short *)(info->start[i]);
|
||||
info->protect[i] = saddr[2] & 1;
|
||||
#else
|
||||
info->protect[i] =0;
|
||||
#endif
|
||||
}
|
||||
|
||||
if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
|
||||
printf ("** ERROR: sector count %d > max (%d) **\n",
|
||||
info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
|
||||
info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
|
||||
}
|
||||
|
||||
saddr = (vu_short *)info->start[0];
|
||||
*saddr = 0x00F0; /* restore read mode */
|
||||
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last)
|
||||
{
|
||||
vu_short *addr = (vu_short*)(info->start[0]);
|
||||
int flag, prot, sect, l_sect;
|
||||
ulong start, now, last;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("- missing\n");
|
||||
} else {
|
||||
printf ("- no sectors to erase\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
if ((info->flash_id == FLASH_UNKNOWN) ||
|
||||
(info->flash_id > FLASH_AMD_COMP)) {
|
||||
printf ("Can't erase unknown flash type %08lx - aborted\n",
|
||||
info->flash_id);
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect=s_first; sect<=s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
l_sect = -1;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
addr[0x0555] = 0x00AA;
|
||||
addr[0x02AA] = 0x0055;
|
||||
addr[0x0555] = 0x0080;
|
||||
addr[0x0555] = 0x00AA;
|
||||
addr[0x02AA] = 0x0055;
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect<=s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
addr = (vu_short*)(info->start[sect]);
|
||||
addr[0] = 0x0030;
|
||||
l_sect = sect;
|
||||
}
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* wait at least 80us - let's wait 1 ms */
|
||||
udelay (1000);
|
||||
|
||||
/*
|
||||
* We wait for the last triggered sector
|
||||
*/
|
||||
if (l_sect < 0)
|
||||
goto DONE;
|
||||
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
addr = (vu_short*)(info->start[l_sect]);
|
||||
while ((addr[0] & 0x0080) != 0x0080) {
|
||||
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
return 1;
|
||||
}
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
putc ('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
|
||||
DONE:
|
||||
/* reset to read mode */
|
||||
addr = (vu_short *)info->start[0];
|
||||
addr[0] = 0x00F0; /* reset bank */
|
||||
|
||||
printf (" done\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
|
||||
#define FLASH_WIDTH 2 /* flash bus width in bytes */
|
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong cp, wp, data;
|
||||
int i, l, rc;
|
||||
|
||||
wp = (addr & ~(FLASH_WIDTH-1)); /* get lower FLASH_WIDTH aligned address */
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - wp) != 0) {
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<l; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
for (; i<FLASH_WIDTH && cnt>0; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
++cp;
|
||||
}
|
||||
for (; cnt==0 && i<FLASH_WIDTH; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
if ((rc = write_data(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += FLASH_WIDTH;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle FLASH_WIDTH aligned part
|
||||
*/
|
||||
while (cnt >= FLASH_WIDTH) {
|
||||
data = 0;
|
||||
for (i=0; i<FLASH_WIDTH; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
}
|
||||
if ((rc = write_data(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += FLASH_WIDTH;
|
||||
cnt -= FLASH_WIDTH;
|
||||
}
|
||||
|
||||
if (cnt == 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<FLASH_WIDTH && cnt>0; ++i, ++cp) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
}
|
||||
for (; i<FLASH_WIDTH; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
return (write_data(info, wp, data));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_data (flash_info_t *info, ulong dest, ulong data)
|
||||
{
|
||||
vu_short *addr = (vu_short*)(info->start[0]);
|
||||
vu_short *sdest = (vu_short *)dest;
|
||||
ushort sdata = (ushort)data;
|
||||
ushort sval;
|
||||
ulong start, passed;
|
||||
int flag, rc;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*sdest & sdata) != sdata) {
|
||||
return (2);
|
||||
}
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
addr[0x0555] = 0x00AA;
|
||||
addr[0x02AA] = 0x0055;
|
||||
addr[0x0555] = 0x00A0;
|
||||
|
||||
#ifdef WORKAROUND_FOR_BROKEN_HARDWARE
|
||||
/* work around the timeout bugs */
|
||||
udelay(20);
|
||||
#endif
|
||||
|
||||
*sdest = sdata;
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
rc = 0;
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
|
||||
for (passed=0; passed < CONFIG_SYS_FLASH_WRITE_TOUT; passed=get_timer(start)) {
|
||||
|
||||
sval = *sdest;
|
||||
|
||||
if ((sval & 0x0080) == (sdata & 0x0080))
|
||||
break;
|
||||
|
||||
if ((sval & 0x0020) == 0) /* DQ5: Timeout? */
|
||||
continue;
|
||||
|
||||
sval = *sdest;
|
||||
|
||||
if ((sval & 0x0080) != (sdata & 0x0080))
|
||||
rc = 1;
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
if (rc) {
|
||||
DEBUGF ("Program cycle failed @ addr 0x%08lX: val %04X data %04X\n",
|
||||
dest, sval, sdata);
|
||||
}
|
||||
|
||||
if (passed >= CONFIG_SYS_FLASH_WRITE_TOUT) {
|
||||
DEBUGF ("Timeout @ addr 0x%08lX: val %04X data %04X\n",
|
||||
dest, sval, sdata);
|
||||
rc = 1;
|
||||
}
|
||||
|
||||
/* reset to read mode */
|
||||
addr = (vu_short *)info->start[0];
|
||||
addr[0] = 0x00F0; /* reset bank */
|
||||
|
||||
return (rc);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
|
@ -1,562 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc8xx.h>
|
||||
#include <commproc.h>
|
||||
#include <i2c.h>
|
||||
#include <command.h>
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
static long int dram_size (long int, long int *, long int);
|
||||
static void puma_status (void);
|
||||
static void puma_set_mode (int mode);
|
||||
static int puma_init_done (void);
|
||||
static void puma_load (ulong addr, ulong len);
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#define _NOT_USED_ 0xFFFFFFFF
|
||||
|
||||
/*
|
||||
* 50 MHz SDRAM access using UPM A
|
||||
*/
|
||||
const uint sdram_table[] = {
|
||||
/*
|
||||
* Single Read. (Offset 0 in UPM RAM)
|
||||
*/
|
||||
0x1f0dfc04, 0xeeafbc04, 0x11af7c04, 0xefbeec00,
|
||||
0x1ffddc47, /* last */
|
||||
/*
|
||||
* SDRAM Initialization (offset 5 in UPM RAM)
|
||||
*
|
||||
* This is no UPM entry point. The following definition uses
|
||||
* the remaining space to establish an initialization
|
||||
* sequence, which is executed by a RUN command.
|
||||
*
|
||||
*/
|
||||
0x1ffddc35, 0xefceac34, 0x1f3d5c35, /* last */
|
||||
/*
|
||||
* Burst Read. (Offset 8 in UPM RAM)
|
||||
*/
|
||||
0x1f0dfc04, 0xeeafbc04, 0x10af7c04, 0xf0affc00,
|
||||
0xf0affc00, 0xf1affc00, 0xefbeec00, 0x1ffddc47, /* last */
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
|
||||
/*
|
||||
* Single Write. (Offset 18 in UPM RAM)
|
||||
*/
|
||||
0x1f0dfc04, 0xeeafac00, 0x01be4c04, 0x1ffddc47, /* last */
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
/*
|
||||
* Burst Write. (Offset 20 in UPM RAM)
|
||||
*/
|
||||
0x1f0dfc04, 0xeeafac00, 0x10af5c00, 0xf0affc00,
|
||||
0xf0affc00, 0xe1beec04, 0x1ffddc47, /* last */
|
||||
_NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
/*
|
||||
* Refresh (Offset 30 in UPM RAM)
|
||||
*/
|
||||
0x1ffd7c84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
|
||||
0xfffffc84, 0xfffffc07, /* last */
|
||||
_NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
/*
|
||||
* Exception. (Offset 3c in UPM RAM)
|
||||
*/
|
||||
0x7ffffc07, /* last */
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
};
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* PUMA access using UPM B
|
||||
*/
|
||||
const uint puma_table[] = {
|
||||
/*
|
||||
* Single Read. (Offset 0 in UPM RAM)
|
||||
*/
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_,
|
||||
/*
|
||||
* Precharge and MRS
|
||||
*/
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
/*
|
||||
* Burst Read. (Offset 8 in UPM RAM)
|
||||
*/
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
/*
|
||||
* Single Write. (Offset 18 in UPM RAM)
|
||||
*/
|
||||
0x0ffff804, 0x0ffff400, 0x3ffffc47, /* last */
|
||||
_NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
/*
|
||||
* Burst Write. (Offset 20 in UPM RAM)
|
||||
*/
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
/*
|
||||
* Refresh (Offset 30 in UPM RAM)
|
||||
*/
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
/*
|
||||
* Exception. (Offset 3c in UPM RAM)
|
||||
*/
|
||||
0x7ffffc07, /* last */
|
||||
_NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||
};
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*
|
||||
*/
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
puts ("Board: Siemens PCU E\n");
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
phys_size_t initdram (int board_type)
|
||||
{
|
||||
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
|
||||
volatile memctl8xx_t *memctl = &immr->im_memctl;
|
||||
long int size_b0, reg;
|
||||
int i;
|
||||
|
||||
/*
|
||||
* Configure UPMA for SDRAM
|
||||
*/
|
||||
upmconfig (UPMA, (uint *) sdram_table,
|
||||
sizeof (sdram_table) / sizeof (uint));
|
||||
|
||||
memctl->memc_mptpr = CONFIG_SYS_MPTPR;
|
||||
|
||||
/* burst length=4, burst type=sequential, CAS latency=2 */
|
||||
memctl->memc_mar = 0x00000088;
|
||||
|
||||
/*
|
||||
* Map controller bank 2 to the SDRAM bank at preliminary address.
|
||||
*/
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||||
memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
|
||||
memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
|
||||
#else /* XXX */
|
||||
memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
|
||||
memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
|
||||
#endif /* XXX */
|
||||
|
||||
/* initialize memory address register */
|
||||
memctl->memc_mamr = CONFIG_SYS_MAMR; /* refresh not enabled yet */
|
||||
|
||||
/* mode initialization (offset 5) */
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||||
udelay (200); /* 0x8000A105 */
|
||||
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x05);
|
||||
#else /* XXX */
|
||||
udelay (200); /* 0x80004105 */
|
||||
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x05);
|
||||
#endif /* XXX */
|
||||
|
||||
/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||||
udelay (1); /* 0x8000A830 */
|
||||
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (8) | MCR_MAD (0x30);
|
||||
#else /* XXX */
|
||||
udelay (1); /* 0x80004830 */
|
||||
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (8) | MCR_MAD (0x30);
|
||||
#endif /* XXX */
|
||||
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||||
udelay (1); /* 0x8000A106 */
|
||||
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF (1) | MCR_MAD (0x06);
|
||||
#else /* XXX */
|
||||
udelay (1); /* 0x80004106 */
|
||||
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF (1) | MCR_MAD (0x06);
|
||||
#endif /* XXX */
|
||||
|
||||
reg = memctl->memc_mamr;
|
||||
reg &= ~MAMR_TLFA_MSK; /* switch timer loop ... */
|
||||
reg |= MAMR_TLFA_4X; /* ... to 4x */
|
||||
reg |= MAMR_PTAE; /* enable refresh */
|
||||
memctl->memc_mamr = reg;
|
||||
|
||||
udelay (200);
|
||||
|
||||
/* Need at least 10 DRAM accesses to stabilize */
|
||||
for (i = 0; i < 10; ++i) {
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||||
volatile unsigned long *addr =
|
||||
(volatile unsigned long *) SDRAM_BASE5_PRELIM;
|
||||
#else /* XXX */
|
||||
volatile unsigned long *addr =
|
||||
(volatile unsigned long *) SDRAM_BASE2_PRELIM;
|
||||
#endif /* XXX */
|
||||
unsigned long val;
|
||||
|
||||
val = *(addr + i);
|
||||
*(addr + i) = val;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check Bank 0 Memory Size for re-configuration
|
||||
*/
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||||
size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
|
||||
#else /* XXX */
|
||||
size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
|
||||
#endif /* XXX */
|
||||
|
||||
memctl->memc_mamr = CONFIG_SYS_MAMR | MAMR_PTAE;
|
||||
|
||||
/*
|
||||
* Final mapping:
|
||||
*/
|
||||
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||||
memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
|
||||
memctl->memc_br5 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
|
||||
#else /* XXX */
|
||||
memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
|
||||
memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
|
||||
#endif /* XXX */
|
||||
udelay (1000);
|
||||
|
||||
/*
|
||||
* Configure UPMB for PUMA
|
||||
*/
|
||||
upmconfig (UPMB, (uint *) puma_table,
|
||||
sizeof (puma_table) / sizeof (uint));
|
||||
|
||||
return (size_b0);
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* Check memory range for valid RAM. A simple memory test determines
|
||||
* the actually available RAM size between addresses `base' and
|
||||
* `base + maxsize'. Some (not all) hardware errors are detected:
|
||||
* - short between address lines
|
||||
* - short between data lines
|
||||
*/
|
||||
|
||||
static long int dram_size (long int mamr_value, long int *base,
|
||||
long int maxsize)
|
||||
{
|
||||
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
|
||||
volatile memctl8xx_t *memctl = &immr->im_memctl;
|
||||
|
||||
memctl->memc_mamr = mamr_value;
|
||||
|
||||
return (get_ram_size (base, maxsize));
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||||
#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_CFG1 | CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 )
|
||||
#else /* XXX */
|
||||
#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_MDDIS | CONFIG_SYS_PB_ETH_CFG1 | \
|
||||
CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 )
|
||||
#endif /* XXX */
|
||||
|
||||
#define ETH_ALL_BITS (ETH_CFG_BITS | CONFIG_SYS_PB_ETH_POWERDOWN | CONFIG_SYS_PB_ETH_RESET)
|
||||
|
||||
void reset_phy (void)
|
||||
{
|
||||
immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
|
||||
ulong value;
|
||||
|
||||
/* Configure all needed port pins for GPIO */
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||||
# ifdef CONFIG_SYS_ETH_MDDIS_VALUE
|
||||
immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_MDDIS;
|
||||
# else
|
||||
immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* Set low */
|
||||
# endif
|
||||
immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* GPIO */
|
||||
immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_ETH_MDDIS); /* active output */
|
||||
immr->im_ioport.iop_padir |= CONFIG_SYS_PA_ETH_MDDIS; /* output */
|
||||
#endif /* XXX */
|
||||
immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */
|
||||
immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */
|
||||
|
||||
value = immr->im_cpm.cp_pbdat;
|
||||
|
||||
/* Assert Powerdown and Reset signals */
|
||||
value |= CONFIG_SYS_PB_ETH_POWERDOWN;
|
||||
value &= ~(CONFIG_SYS_PB_ETH_RESET);
|
||||
|
||||
/* PHY configuration includes MDDIS and CFG1 ... CFG3 */
|
||||
#if !PCU_E_WITH_SWAPPED_CS
|
||||
# ifdef CONFIG_SYS_ETH_MDDIS_VALUE
|
||||
value |= CONFIG_SYS_PB_ETH_MDDIS;
|
||||
# else
|
||||
value &= ~(CONFIG_SYS_PB_ETH_MDDIS);
|
||||
# endif
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_ETH_CFG1_VALUE
|
||||
value |= CONFIG_SYS_PB_ETH_CFG1;
|
||||
#else
|
||||
value &= ~(CONFIG_SYS_PB_ETH_CFG1);
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_ETH_CFG2_VALUE
|
||||
value |= CONFIG_SYS_PB_ETH_CFG2;
|
||||
#else
|
||||
value &= ~(CONFIG_SYS_PB_ETH_CFG2);
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_ETH_CFG3_VALUE
|
||||
value |= CONFIG_SYS_PB_ETH_CFG3;
|
||||
#else
|
||||
value &= ~(CONFIG_SYS_PB_ETH_CFG3);
|
||||
#endif
|
||||
|
||||
/* Drive output signals to initial state */
|
||||
immr->im_cpm.cp_pbdat = value;
|
||||
immr->im_cpm.cp_pbdir |= ETH_ALL_BITS;
|
||||
udelay (10000);
|
||||
|
||||
/* De-assert Ethernet Powerdown */
|
||||
immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */
|
||||
udelay (10000);
|
||||
|
||||
/* de-assert RESET signal of PHY */
|
||||
immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_ETH_RESET;
|
||||
udelay (1000);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Board Special Commands: access functions for "PUMA" FPGA
|
||||
*/
|
||||
#if defined(CONFIG_CMD_BSP)
|
||||
|
||||
#define PUMA_READ_MODE 0
|
||||
#define PUMA_LOAD_MODE 1
|
||||
|
||||
int do_puma (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
ulong addr, len;
|
||||
|
||||
switch (argc) {
|
||||
case 2: /* PUMA reset */
|
||||
if (strncmp (argv[1], "stat", 4) == 0) { /* Reset */
|
||||
puma_status ();
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
case 4: /* PUMA load addr len */
|
||||
if (strcmp (argv[1], "load") != 0)
|
||||
break;
|
||||
|
||||
addr = simple_strtoul (argv[2], NULL, 16);
|
||||
len = simple_strtoul (argv[3], NULL, 16);
|
||||
|
||||
printf ("PUMA load: addr %08lX len %ld (0x%lX): ",
|
||||
addr, len, len);
|
||||
puma_load (addr, len);
|
||||
|
||||
return 0;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return cmd_usage(cmdtp);
|
||||
}
|
||||
|
||||
U_BOOT_CMD (puma, 4, 1, do_puma,
|
||||
"access PUMA FPGA",
|
||||
"status - print PUMA status\n"
|
||||
"puma load addr len - load PUMA configuration data"
|
||||
);
|
||||
#endif
|
||||
|
||||
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
|
||||
|
||||
static void puma_set_mode (int mode)
|
||||
{
|
||||
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
|
||||
volatile memctl8xx_t *memctl = &immr->im_memctl;
|
||||
|
||||
/* disable PUMA in memory controller */
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||||
memctl->memc_br3 = 0;
|
||||
#else /* XXX */
|
||||
memctl->memc_br4 = 0;
|
||||
#endif /* XXX */
|
||||
|
||||
switch (mode) {
|
||||
case PUMA_READ_MODE:
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||||
memctl->memc_or3 = PUMA_CONF_OR_READ;
|
||||
memctl->memc_br3 = PUMA_CONF_BR_READ;
|
||||
#else /* XXX */
|
||||
memctl->memc_or4 = PUMA_CONF_OR_READ;
|
||||
memctl->memc_br4 = PUMA_CONF_BR_READ;
|
||||
#endif /* XXX */
|
||||
break;
|
||||
case PUMA_LOAD_MODE:
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||||
memctl->memc_or3 = PUMA_CONF_OR_LOAD;
|
||||
memctl->memc_br3 = PUMA_CONF_BR_LOAD;
|
||||
#else /* XXX */
|
||||
memctl->memc_or4 = PUMA_CONF_OR_READ;
|
||||
memctl->memc_br4 = PUMA_CONF_BR_READ;
|
||||
#endif /* XXX */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
|
||||
|
||||
#define PUMA_INIT_TIMEOUT 1000 /* max. 1000 ms = 1 second */
|
||||
|
||||
static void puma_load (ulong addr, ulong len)
|
||||
{
|
||||
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
|
||||
volatile uchar *fpga_addr = (volatile uchar *) PUMA_CONF_BASE; /* XXX ??? */
|
||||
uchar *data = (uchar *) addr;
|
||||
int i;
|
||||
|
||||
/* align length */
|
||||
if (len & 1)
|
||||
++len;
|
||||
|
||||
/* Reset FPGA */
|
||||
immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_INIT); /* make input */
|
||||
immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_PUMA_INIT);
|
||||
immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_INIT);
|
||||
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||||
immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_PUMA_PROG); /* GPIO */
|
||||
immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_PUMA_PROG); /* active output */
|
||||
immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_PUMA_PROG); /* Set low */
|
||||
immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_PUMA_PROG; /* output */
|
||||
#else
|
||||
immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_PUMA_PROG); /* GPIO */
|
||||
immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_PUMA_PROG); /* Set low */
|
||||
immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_PUMA_PROG); /* active output */
|
||||
immr->im_ioport.iop_padir |= CONFIG_SYS_PA_PUMA_PROG; /* output */
|
||||
#endif /* XXX */
|
||||
udelay (100);
|
||||
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||||
immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_PUMA_PROG; /* release reset */
|
||||
#else
|
||||
immr->im_ioport.iop_padat |= CONFIG_SYS_PA_PUMA_PROG; /* release reset */
|
||||
#endif /* XXX */
|
||||
|
||||
/* wait until INIT indicates completion of reset */
|
||||
for (i = 0; i < PUMA_INIT_TIMEOUT; ++i) {
|
||||
udelay (1000);
|
||||
if (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_INIT)
|
||||
break;
|
||||
}
|
||||
if (i == PUMA_INIT_TIMEOUT) {
|
||||
printf ("*** PUMA init timeout ***\n");
|
||||
return;
|
||||
}
|
||||
|
||||
puma_set_mode (PUMA_LOAD_MODE);
|
||||
|
||||
while (len--)
|
||||
*fpga_addr = *data++;
|
||||
|
||||
puma_set_mode (PUMA_READ_MODE);
|
||||
|
||||
puma_status ();
|
||||
}
|
||||
|
||||
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
|
||||
|
||||
static void puma_status (void)
|
||||
{
|
||||
/* Check state */
|
||||
printf ("PUMA initialization is %scomplete\n",
|
||||
puma_init_done ()? "" : "NOT ");
|
||||
}
|
||||
|
||||
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
|
||||
|
||||
static int puma_init_done (void)
|
||||
{
|
||||
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
|
||||
|
||||
/* make sure pin is GPIO input */
|
||||
immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_DONE);
|
||||
immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_PUMA_DONE);
|
||||
immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_DONE);
|
||||
|
||||
return (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_DONE) ? 1 : 0;
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
int misc_init_r (void)
|
||||
{
|
||||
ulong addr = 0;
|
||||
ulong len = 0;
|
||||
char *s;
|
||||
|
||||
printf ("PUMA: ");
|
||||
if (puma_init_done ()) {
|
||||
printf ("initialized\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
if ((s = getenv ("puma_addr")) != NULL)
|
||||
addr = simple_strtoul (s, NULL, 16);
|
||||
|
||||
if ((s = getenv ("puma_len")) != NULL)
|
||||
len = simple_strtoul (s, NULL, 16);
|
||||
|
||||
if ((!addr) || (!len)) {
|
||||
printf ("net list undefined\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
printf ("loading... ");
|
||||
|
||||
puma_load (addr, len);
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
|
@ -1,127 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
arch/powerpc/cpu/mpc8xx/start.o (.text)
|
||||
common/env_embedded.o(.text)
|
||||
*(.text)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.eh_frame)
|
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x0FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -1,136 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
arch/powerpc/cpu/mpc8xx/start.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib/vsprintf.o (.text)
|
||||
lib/crc32.o (.text)
|
||||
arch/powerpc/lib/extable.o (.text)
|
||||
|
||||
. = env_offset;
|
||||
common/env_embedded.o(.text)
|
||||
|
||||
*(.text)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
*(.eh_frame)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x0FFF) & 0xFFFFF000;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(4096);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(4096);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
@ -163,7 +163,6 @@ KUP4X powerpc mpc8xx kup4x kup
|
|||
ELPT860 powerpc mpc8xx elpt860 LEOX
|
||||
CCM powerpc mpc8xx - siemens
|
||||
IAD210 powerpc mpc8xx - siemens
|
||||
pcu_e powerpc mpc8xx - siemens
|
||||
QS823 powerpc mpc8xx qs850 snmc
|
||||
QS850 powerpc mpc8xx qs850 snmc
|
||||
QS860T powerpc mpc8xx qs860t snmc
|
||||
|
|
|
|||
|
|
@ -580,11 +580,11 @@ typedef struct scc_enet {
|
|||
/*********************************************************************/
|
||||
|
||||
|
||||
/*** CCM and PCU E ***********************************************/
|
||||
/*** CCM ***********************************************************/
|
||||
|
||||
/* The PCU E and CCM use the FEC on a MPC860T for Ethernet */
|
||||
/* The CCM uses the FEC on a MPC860T for Ethernet */
|
||||
|
||||
#if defined (CONFIG_PCU_E) || defined(CONFIG_CCM)
|
||||
#if defined(CONFIG_CCM)
|
||||
|
||||
#define FEC_ENET /* use FEC for EThernet */
|
||||
#undef SCC_ENET
|
||||
|
|
@ -605,7 +605,7 @@ typedef struct scc_enet {
|
|||
|
||||
#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
|
||||
|
||||
#endif /* CONFIG_PCU_E, CONFIG_CCM */
|
||||
#endif /* CONFIG_CCM */
|
||||
|
||||
/*** ELPT860 *********************************************************/
|
||||
|
||||
|
|
|
|||
|
|
@ -1,550 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2001-2005
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* Workaround for layout bug on prototype board
|
||||
*/
|
||||
#define PCU_E_WITH_SWAPPED_CS 1
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC860 1 /* This is a MPC860T CPU */
|
||||
#define CONFIG_MPC860T 1
|
||||
#define CONFIG_PCU_E 1 /* ...on a PCU E board */
|
||||
|
||||
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */
|
||||
#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
|
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
|
||||
|
||||
#define CONFIG_BAUDRATE 9600
|
||||
#if 0
|
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
|
||||
#else
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
#endif
|
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"bootp;" \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
|
||||
"bootm"
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
|
||||
|
||||
#define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */
|
||||
|
||||
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
|
||||
|
||||
#define CONFIG_SPI /* enable SPI driver */
|
||||
#define CONFIG_SPI_X /* 16 bit EEPROM addressing */
|
||||
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------
|
||||
* Offset to initial SPI buffers in DPRAM (used if the environment
|
||||
* is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to
|
||||
* use at an early stage. It is used between the two initialization
|
||||
* calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it
|
||||
* far enough from the start of the data area (as well as from the
|
||||
* stack pointer).
|
||||
* ---------------------------------------------------------------- */
|
||||
#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
#define CONFIG_CMD_BSP
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_NFS
|
||||
#define CONFIG_CMD_SNTP
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
|
||||
|
||||
#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
|
||||
|
||||
/* Ethernet hardware configuration done using port pins */
|
||||
#define CONFIG_SYS_PB_ETH_RESET 0x00000020 /* PB 26 */
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||||
#define CONFIG_SYS_PA_ETH_MDDIS 0x4000 /* PA 1 */
|
||||
#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */
|
||||
#define CONFIG_SYS_PB_ETH_CFG1 0x00000400 /* PB 21 */
|
||||
#define CONFIG_SYS_PB_ETH_CFG2 0x00000200 /* PB 22 */
|
||||
#define CONFIG_SYS_PB_ETH_CFG3 0x00000100 /* PB 23 */
|
||||
#else /* XXX */
|
||||
#define CONFIG_SYS_PB_ETH_MDDIS 0x00000010 /* PB 27 */
|
||||
#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00000100 /* PB 23 */
|
||||
#define CONFIG_SYS_PB_ETH_CFG1 0x00000200 /* PB 22 */
|
||||
#define CONFIG_SYS_PB_ETH_CFG2 0x00000400 /* PB 21 */
|
||||
#define CONFIG_SYS_PB_ETH_CFG3 0x00000800 /* PB 20 */
|
||||
#endif /* XXX */
|
||||
|
||||
/* Ethernet settings:
|
||||
* MDIO enabled, autonegotiation, 10/100Mbps, half/full duplex
|
||||
*/
|
||||
#define CONFIG_SYS_ETH_MDDIS_VALUE 0
|
||||
#define CONFIG_SYS_ETH_CFG1_VALUE 1
|
||||
#define CONFIG_SYS_ETH_CFG2_VALUE 1
|
||||
#define CONFIG_SYS_ETH_CFG3_VALUE 1
|
||||
|
||||
/* PUMA configuration */
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||||
#define CONFIG_SYS_PB_PUMA_PROG 0x00000010 /* PB 27 */
|
||||
#else /* XXX */
|
||||
#define CONFIG_SYS_PA_PUMA_PROG 0x4000 /* PA 1 */
|
||||
#endif /* XXX */
|
||||
#define CONFIG_SYS_PC_PUMA_DONE 0x0008 /* PC 12 */
|
||||
#define CONFIG_SYS_PC_PUMA_INIT 0x0004 /* PC 13 */
|
||||
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register
|
||||
*/
|
||||
#define CONFIG_SYS_IMMR 0xFE000000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
|
||||
#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Address accessed to reset the board - must not be mapped/assigned
|
||||
*/
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xFEFFFFFF
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
/* this is an ugly hack needed because of the silly non-constant address map */
|
||||
#define CONFIG_SYS_FLASH_BASE (0-flash_info[0].size-flash_info[1].size)
|
||||
|
||||
#if defined(DEBUG)
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#else
|
||||
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
|
||||
#endif
|
||||
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 160 /* max number of sectors on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#if 0
|
||||
/* Start port with environment in flash; switch to SPI EEPROM later */
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment */
|
||||
#define CONFIG_ENV_ADDR 0xFFFFE000 /* Address of Environment Sector */
|
||||
#define CONFIG_ENV_SECT_SIZE 0x2000 /* use the top-most 8k boot sector */
|
||||
#else
|
||||
/* Final version: environment in EEPROM */
|
||||
#define CONFIG_ENV_IS_IN_EEPROM 1
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CONFIG_ENV_OFFSET 1024
|
||||
#define CONFIG_ENV_SIZE 1024
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
|
||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
|
||||
#define CONFIG_SYS_DELAYED_ICACHE 1 /* enable ICache not before
|
||||
* running in RAM.
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
|
||||
*/
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
|
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
|
||||
#else
|
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6
|
||||
*-----------------------------------------------------------------------
|
||||
* External Arbitration max. priority (7),
|
||||
* Debug pins configuration '11',
|
||||
* Asynchronous external master enable.
|
||||
*/
|
||||
/* => 0x70600200 */
|
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_EARP7 | SIUMCR_DBGC11 | SIUMCR_AEME)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Reference Interrupt Status, Timebase freezing enabled
|
||||
*/
|
||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
|
||||
*/
|
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit, set PLL multiplication factor !
|
||||
*/
|
||||
/* 0x00004080 */
|
||||
#define CONFIG_SYS_PLPRCR_MF 0 /* (0+1) * 50 = 50 MHz Clock */
|
||||
#define CONFIG_SYS_PLPRCR \
|
||||
( (CONFIG_SYS_PLPRCR_MF << PLPRCR_MF_SHIFT) | \
|
||||
PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
|
||||
/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
|
||||
PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \
|
||||
)
|
||||
|
||||
#define CONFIG_8xx_GCLK_FREQ ((CONFIG_SYS_PLPRCR_MF+1)*50000000)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
*-----------------------------------------------------------------------
|
||||
* Set clock output, timebase and RTC source and divider,
|
||||
* power management and some other internal clocks
|
||||
*
|
||||
* Note: PITRTCLK is 50MHz / 512 = 97'656.25 Hz
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
/* 0x01800000 */
|
||||
#define CONFIG_SYS_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
|
||||
SCCR_RTDIV | SCCR_RTSEL | \
|
||||
/*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
|
||||
SCCR_EBDF00 | SCCR_DFSYNC00 | \
|
||||
SCCR_DFBRG00 | SCCR_DFNL000 | \
|
||||
SCCR_DFNH000 | SCCR_DFLCD100 | \
|
||||
SCCR_DFALCD01)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
* Note: RTC counts at PITRTCLK / 8'192 = 11.920928 Hz !!!
|
||||
*
|
||||
* Don't expect the "date" command to work without a 32kHz clock input!
|
||||
*/
|
||||
/* 0x00C3 => 0x0003 */
|
||||
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration Register 19-4
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_RCCR 0x0000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMDS - RISC Microcode Development Support Control Register
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_RMDS 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*
|
||||
* Interrupt Levels
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#define CONFIG_SYS_DER 0
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0/1 and OR0/1 (FLASH) - second Flash bank optional
|
||||
*/
|
||||
|
||||
#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||||
#define FLASH_BASE6_PRELIM 0xFF000000 /* FLASH bank #1 */
|
||||
#else /* XXX */
|
||||
#define FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank #1 */
|
||||
#endif /* XXX */
|
||||
|
||||
/*
|
||||
* used to re-map FLASH: restrict access enough but not too much to
|
||||
* meddle with FLASH accesses
|
||||
*/
|
||||
#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */
|
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
|
||||
|
||||
/* FLASH timing: CSNT = 0, ACS = 00, SCY = 8, EHTR = 1 */
|
||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_EHTR)
|
||||
|
||||
#define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM | OR_ACS_DIV1 | OR_BI | \
|
||||
CONFIG_SYS_OR_TIMING_FLASH)
|
||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
|
||||
CONFIG_SYS_OR_TIMING_FLASH)
|
||||
/* 16 bit, bank valid */
|
||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
|
||||
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||||
#define CONFIG_SYS_OR6_REMAP CONFIG_SYS_OR0_REMAP
|
||||
#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR0_PRELIM
|
||||
#define CONFIG_SYS_BR6_PRELIM ((FLASH_BASE6_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
|
||||
#else /* XXX */
|
||||
#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
|
||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
|
||||
#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
|
||||
#endif /* XXX */
|
||||
|
||||
/*
|
||||
* BR2/OR2: SDRAM
|
||||
*
|
||||
* Multiplexed addresses, GPL5 output to GPL5_A (don't care)
|
||||
*/
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||||
#define SDRAM_BASE5_PRELIM 0x00000000 /* SDRAM bank */
|
||||
#else /* XXX */
|
||||
#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank */
|
||||
#endif /* XXX */
|
||||
#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map 128 MB (>SDRAM_MAX_SIZE!) */
|
||||
#define SDRAM_TIMING OR_CSNT_SAM /* SDRAM-Timing */
|
||||
|
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
|
||||
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||||
#define CONFIG_SYS_OR5_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
|
||||
#define CONFIG_SYS_BR5_PRELIM ((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
|
||||
#else /* XXX */
|
||||
#define CONFIG_SYS_OR2_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
|
||||
#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
|
||||
#endif /* XXX */
|
||||
|
||||
/*
|
||||
* BR3/OR3: CAN Controller
|
||||
* BR3: 0x10000401 OR3: 0xffff818a
|
||||
*/
|
||||
#define CAN_CTRLR_BASE 0x10000000 /* CAN Controller */
|
||||
#define CAN_CTRLR_OR_AM 0xFFFF8000 /* 32 kB */
|
||||
#define CAN_CTRLR_TIMING (OR_BI | OR_SCY_8_CLK | OR_SETA | OR_EHTR)
|
||||
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||||
#define CONFIG_SYS_BR4_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
|
||||
#define CONFIG_SYS_OR4_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
|
||||
#else /* XXX */
|
||||
#define CONFIG_SYS_BR3_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
|
||||
#define CONFIG_SYS_OR3_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
|
||||
#endif /* XXX */
|
||||
|
||||
/*
|
||||
* BR4/OR4: PUMA Config
|
||||
*
|
||||
* Memory controller will be used in 2 modes:
|
||||
*
|
||||
* - "read" mode:
|
||||
* BR4: 0x10100801 OR4: 0xffff8530
|
||||
* - "load" mode (chip select on UPM B):
|
||||
* BR4: 0x101008c1 OR4: 0xffff8630
|
||||
*
|
||||
* Default initialization is in "read" mode
|
||||
*/
|
||||
#define PUMA_CONF_BASE 0x10100000 /* PUMA Config */
|
||||
#define PUMA_CONF_OR_AM 0xFFFF8000 /* 32 kB */
|
||||
#define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2 | OR_SCY_3_CLK)
|
||||
#define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_3_CLK)
|
||||
|
||||
#define PUMA_CONF_BR_LOAD ((PUMA_CONF_BASE & BR_BA_MSK) | \
|
||||
BR_PS_16 | BR_MS_UPMB | BR_V)
|
||||
#define PUMA_CONF_OR_LOAD (PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING)
|
||||
|
||||
#define PUMA_CONF_BR_READ ((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
|
||||
#define PUMA_CONF_OR_READ (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING)
|
||||
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||||
#define CONFIG_SYS_BR3_PRELIM PUMA_CONF_BR_READ
|
||||
#define CONFIG_SYS_OR3_PRELIM PUMA_CONF_OR_READ
|
||||
#else /* XXX */
|
||||
#define CONFIG_SYS_BR4_PRELIM PUMA_CONF_BR_READ
|
||||
#define CONFIG_SYS_OR4_PRELIM PUMA_CONF_OR_READ
|
||||
#endif /* XXX */
|
||||
|
||||
/*
|
||||
* BR5/OR5: PUMA: SMA Bus 8 Bit
|
||||
* BR5: 0x10200401 OR5: 0xffe0010a
|
||||
*/
|
||||
#define PUMA_SMA8_BASE 0x10200000 /* PUMA SMA Bus 8 Bit */
|
||||
#define PUMA_SMA8_OR_AM 0xFFE00000 /* 2 MB */
|
||||
#define PUMA_SMA8_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
|
||||
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||||
#define CONFIG_SYS_BR2_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
|
||||
#define CONFIG_SYS_OR2_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
|
||||
#else /* XXX */
|
||||
#define CONFIG_SYS_BR5_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
|
||||
#define CONFIG_SYS_OR5_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
|
||||
#endif /* XXX */
|
||||
|
||||
/*
|
||||
* BR6/OR6: PUMA: SMA Bus 16 Bit
|
||||
* BR6: 0x10600801 OR6: 0xffe0010a
|
||||
*/
|
||||
#define PUMA_SMA16_BASE 0x10600000 /* PUMA SMA Bus 16 Bit */
|
||||
#define PUMA_SMA16_OR_AM 0xFFE00000 /* 2 MB */
|
||||
#define PUMA_SMA16_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
|
||||
|
||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||||
#define CONFIG_SYS_BR1_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
|
||||
#define CONFIG_SYS_OR1_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
|
||||
#else /* XXX */
|
||||
#define CONFIG_SYS_BR6_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
|
||||
#define CONFIG_SYS_OR6_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
|
||||
#endif /* XXX */
|
||||
|
||||
/*
|
||||
* BR7/OR7: PUMA: external Flash
|
||||
* BR7: 0x10a00801 OR7: 0xfe00010a
|
||||
*/
|
||||
#define PUMA_FLASH_BASE 0x10A00000 /* PUMA external Flash */
|
||||
#define PUMA_FLASH_OR_AM 0xFE000000 /* 32 MB */
|
||||
#define PUMA_FLASH_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
|
||||
|
||||
#define CONFIG_SYS_BR7_PRELIM ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
|
||||
#define CONFIG_SYS_OR7_PRELIM (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA)
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler
|
||||
*/
|
||||
|
||||
/* periodic timer for refresh */
|
||||
#define CONFIG_SYS_MPTPR 0x0200
|
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM
|
||||
* 0x30104118 = Timer A period 0x30, MAMR_AMB_TYPE_1, MAMR_G0CLB_A10,
|
||||
* MAMR_RLFB_1X, MAMR_WLFB_1X, MAMR_TLFB_8X
|
||||
* 0x30904114 = - " - | Periodic Timer A Enable, MAMR_TLFB_4X
|
||||
*/
|
||||
/* periodic timer for refresh */
|
||||
#define CONFIG_SYS_MAMR_PTA 0x30 /* = 48 */
|
||||
|
||||
#define CONFIG_SYS_MAMR ( (CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | \
|
||||
MAMR_AMA_TYPE_1 | \
|
||||
MAMR_G0CLA_A10 | \
|
||||
MAMR_RLFA_1X | \
|
||||
MAMR_WLFA_1X | \
|
||||
MAMR_TLFA_8X )
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -190,8 +190,8 @@ void status_led_set (int led, int state);
|
|||
|
||||
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
|
||||
|
||||
/***** PCU E and CCM ************************************************/
|
||||
#elif (defined(CONFIG_PCU_E) || defined(CONFIG_CCM))
|
||||
/***** CCM ************************************************************/
|
||||
#elif defined(CONFIG_CCM)
|
||||
|
||||
# define STATUS_LED_PAR im_cpm.cp_pbpar
|
||||
# define STATUS_LED_DIR im_cpm.cp_pbdir
|
||||
|
|
|
|||
Loading…
Reference in a new issue