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imx: imx8mq: add dtsi file
Add dtsi file for i.MX8MQ. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Peng Fan
Stefano Babic
parent
f24e482ae0
commit
52df705c96
4 changed files with 1765 additions and 0 deletions
92
arch/arm/dts/fsl-imx8-ca53.dtsi
Normal file
92
arch/arm/dts/fsl-imx8-ca53.dtsi
Normal file
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@ -0,0 +1,92 @@
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/*
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* Copyright 2017 NXP
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/{
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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idle-states {
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entry-method = "psci";
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CPU_SLEEP: cpu-sleep {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x0000000>;
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entry-latency-us = <700>;
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exit-latency-us = <250>;
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min-residency-us = <1000>;
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};
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CLUSTER_SLEEP: cluster-sleep {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x1000000>;
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entry-latency-us = <1000>;
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exit-latency-us = <700>;
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min-residency-us = <2700>;
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wakeup-latency-us = <1500>;
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};
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};
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/* We have 1 clusters having 4 Cortex-A53 cores */
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A53_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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cpu-idle-states = <&CPU_SLEEP>;
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};
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A53_1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x1>;
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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cpu-idle-states = <&CPU_SLEEP>;
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};
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A53_2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x2>;
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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cpu-idle-states = <&CPU_SLEEP>;
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};
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A53_3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x3>;
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enable-method = "psci";
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next-level-cache = <&A53_L2>;
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cpu-idle-states = <&CPU_SLEEP>;
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};
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A53_L2: l2-cache0 {
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compatible = "cache";
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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cpu_suspend = <0xc4000001>;
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cpu_off = <0xc4000002>;
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cpu_on = <0xc4000003>;
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};
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};
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429
arch/arm/dts/fsl-imx8mq.dtsi
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429
arch/arm/dts/fsl-imx8mq.dtsi
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@ -0,0 +1,429 @@
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "fsl-imx8-ca53.dtsi"
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#include <dt-bindings/clock/imx8mq-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/pins-imx8mq.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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compatible = "fsl,imx8mq";
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interrupt-parent = <&gpc>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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ethernet0 = &fec1;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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gpio4 = &gpio5;
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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i2c3 = &i2c4;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x00000000 0x40000000 0 0xc0000000>;
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};
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gic: interrupt-controller@38800000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
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<0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) |
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IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) |
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IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) |
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IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) |
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IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
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clock-frequency = <8333333>;
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interrupt-parent = <&gic>;
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};
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power: power-controller {
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compatible = "fsl,imx8mq-pm-domain";
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num-domains = <11>;
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#power-domain-cells = <1>;
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};
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pwm2: pwm@30670000 {
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compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
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reg = <0x0 0x30670000 0x0 0x10000>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
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<&clk IMX8MQ_CLK_PWM2_ROOT>;
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clock-names = "ipg", "per";
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#pwm-cells = <2>;
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status = "disabled";
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};
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gpio1: gpio@30200000 {
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compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
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reg = <0x0 0x30200000 0x0 0x10000>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@30210000 {
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compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
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reg = <0x0 0x30210000 0x0 0x10000>;
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@30220000 {
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compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
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reg = <0x0 0x30220000 0x0 0x10000>;
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio4: gpio@30230000 {
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compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
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reg = <0x0 0x30230000 0x0 0x10000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio5: gpio@30240000 {
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compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
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reg = <0x0 0x30240000 0x0 0x10000>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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tmu: tmu@30260000 {
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compatible = "fsl,imx8mq-tmu";
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reg = <0x0 0x30260000 0x0 0x10000>;
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interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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little-endian;
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u-boot,dm-pre-reloc;
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fsl,tmu-range = <0xa0000 0x90026 0x8004a 0x1006a>;
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fsl,tmu-calibration = <0x00000000 0x00000020
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0x00000001 0x00000028
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0x00000002 0x00000030
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0x00000003 0x00000038
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0x00000004 0x00000040
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0x00000005 0x00000048
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0x00000006 0x00000050
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0x00000007 0x00000058
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0x00000008 0x00000060
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0x00000009 0x00000068
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0x0000000a 0x00000070
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0x0000000b 0x00000077
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0x00010000 0x00000057
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0x00010001 0x0000005b
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0x00010002 0x0000005f
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0x00010003 0x00000063
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0x00010004 0x00000067
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0x00010005 0x0000006b
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0x00010006 0x0000006f
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0x00010007 0x00000073
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0x00010008 0x00000077
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0x00010009 0x0000007b
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0x0001000a 0x0000007f
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0x00020000 0x00000002
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0x00020001 0x0000000e
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0x00020002 0x0000001a
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0x00020003 0x00000026
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0x00020004 0x00000032
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0x00020005 0x0000003e
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0x00020006 0x0000004a
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0x00020007 0x00000056
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0x00020008 0x00000062
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0x00030000 0x00000000
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0x00030001 0x00000008
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0x00030002 0x00000010
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0x00030003 0x00000018
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0x00030004 0x00000020
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0x00030005 0x00000028
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0x00030006 0x00000030
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0x00030007 0x00000038>;
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#thermal-sensor-cells = <0>;
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};
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thermal-zones {
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/* cpu thermal */
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cpu-thermal {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&tmu>;
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trips {
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cpu_alert0: trip0 {
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temperature = <85000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit0: trip1 {
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temperature = <125000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_alert0>;
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cooling-device =
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<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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lcdif: lcdif@30320000 {
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compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
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reg = <0x0 0x30320000 0x0 0x10000>;
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clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_DIV>,
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<&clk IMX8MQ_CLK_DUMMY>,
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<&clk IMX8MQ_CLK_DUMMY>;
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clock-names = "pix", "axi", "disp_axi";
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assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>;
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assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
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assigned-clock-rate = <594000000>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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iomuxc: iomuxc@30330000 {
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compatible = "fsl,imx8mq-iomuxc";
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reg = <0x0 0x30330000 0x0 0x10000>;
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};
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gpr: iomuxc-gpr@30340000 {
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compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx7d-iomuxc-gpr", "syscon";
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reg = <0x0 0x30340000 0x0 0x10000>;
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};
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ocotp: ocotp-ctrl@30350000 {
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compatible = "fsl,imx8mq-ocotp", "fsl,imx7d-ocotp", "syscon";
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reg = <0x0 0x30350000 0x0 0x10000>;
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};
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anatop: anatop@30360000 {
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compatible = "fsl,imx8mq-anatop", "fsl,imx6q-anatop",
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"syscon", "simple-bus";
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reg = <0x0 0x30360000 0x0 0x10000>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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};
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clk: ccm@30380000 {
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compatible = "fsl,imx8mq-ccm";
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reg = <0x0 0x30380000 0x0 0x10000>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
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#clock-cells = <1>;
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};
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gpc: gpc@303a0000 {
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compatible = "fsl,imx8mq-gpc", "fsl,imx7d-gpc", "syscon";
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reg = <0x0 0x303a0000 0x0 0x10000>;
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interrupt-controller;
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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};
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usdhc1: usdhc@30b40000 {
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compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
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reg = <0x0 0x30b40000 0x0 0x10000>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MQ_CLK_DUMMY>,
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<&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
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<&clk IMX8MQ_CLK_USDHC1_ROOT>;
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clock-names = "ipg", "ahb", "per";
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assigned-clocks = <&clk IMX8MQ_CLK_USDHC1_DIV>;
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assigned-clock-rates = <400000000>;
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fsl,tuning-start-tap = <20>;
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fsl,tuning-step= <2>;
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bus-width = <4>;
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status = "disabled";
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};
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usdhc2: usdhc@30b50000 {
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compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
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reg = <0x0 0x30b50000 0x0 0x10000>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MQ_CLK_DUMMY>,
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<&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
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<&clk IMX8MQ_CLK_USDHC2_ROOT>;
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clock-names = "ipg", "ahb", "per";
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fsl,tuning-start-tap = <20>;
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fsl,tuning-step= <2>;
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bus-width = <4>;
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status = "disabled";
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};
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fec1: ethernet@30be0000 {
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compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
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reg = <0x0 0x30be0000 0x0 0x10000>;
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interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
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<&clk IMX8MQ_CLK_ENET1_ROOT>,
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<&clk IMX8MQ_CLK_ENET_TIMER_DIV>,
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<&clk IMX8MQ_CLK_ENET_REF_DIV>,
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<&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>;
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clock-names = "ipg", "ahb", "ptp",
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"enet_clk_ref", "enet_out";
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assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI_SRC>,
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<&clk IMX8MQ_CLK_ENET_TIMER_SRC>,
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<&clk IMX8MQ_CLK_ENET_REF_SRC>,
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<&clk IMX8MQ_CLK_ENET_TIMER_DIV>;
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assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
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<&clk IMX8MQ_SYS2_PLL_100M>,
|
||||
<&clk IMX8MQ_SYS2_PLL_125M>;
|
||||
assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
|
||||
stop-mode = <&gpr 0x10 3>;
|
||||
fsl,num-tx-queues=<3>;
|
||||
fsl,num-rx-queues=<3>;
|
||||
fsl,wakeup_irq = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
imx_ion {
|
||||
compatible = "fsl,mxc-ion";
|
||||
fsl,heap-id = <0>;
|
||||
};
|
||||
|
||||
i2c1: i2c@30a20000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx21-i2c";
|
||||
reg = <0x0 0x30a20000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@30a30000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx21-i2c";
|
||||
reg = <0x0 0x30a30000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@30a40000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx21-i2c";
|
||||
reg = <0x0 0x30a40000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@30a50000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx21-i2c";
|
||||
reg = <0x0 0x30a50000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog1: wdog@30280000 {
|
||||
compatible = "fsl,imx21-wdt";
|
||||
reg = <0 0x30280000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog2: wdog@30290000 {
|
||||
compatible = "fsl,imx21-wdt";
|
||||
reg = <0 0x30290000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog3: wdog@302a0000 {
|
||||
compatible = "fsl,imx21-wdt";
|
||||
reg = <0 0x302a0000 0 0x10000>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dma_cap: dma_cap {
|
||||
compatible = "dma-capability";
|
||||
only-dma-mask32 = <1>;
|
||||
};
|
||||
|
||||
qspi: qspi@30bb0000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx7d-qspi";
|
||||
reg = <0 0x30bb0000 0 0x10000>, <0 0x08000000 0 0x10000000>;
|
||||
reg-names = "QuadSPI", "QuadSPI-memory";
|
||||
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
|
||||
<&clk IMX8MQ_CLK_QSPI_ROOT>;
|
||||
clock-names = "qspi_en", "qspi";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&A53_0 {
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
612
include/dt-bindings/clock/imx8mq-clock.h
Normal file
612
include/dt-bindings/clock/imx8mq-clock.h
Normal file
|
|
@ -0,0 +1,612 @@
|
|||
/*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H
|
||||
#define __DT_BINDINGS_CLOCK_IMX8MQ_H
|
||||
|
||||
#define IMX8MQ_CLK_DUMMY 0
|
||||
#define IMX8MQ_CLK_32K 1
|
||||
#define IMX8MQ_CLK_25M 2
|
||||
#define IMX8MQ_CLK_27M 3
|
||||
#define IMX8MQ_CLK_EXT1 4
|
||||
#define IMX8MQ_CLK_EXT2 5
|
||||
#define IMX8MQ_CLK_EXT3 6
|
||||
#define IMX8MQ_CLK_EXT4 7
|
||||
|
||||
/* ANAMIX PLL clocks */
|
||||
/* FRAC PLLs */
|
||||
/* ARM PLL */
|
||||
#define IMX8MQ_ARM_PLL_REF_SEL 8
|
||||
#define IMX8MQ_ARM_PLL_REF_DIV 9
|
||||
#define IMX8MQ_ARM_PLL 10
|
||||
#define IMX8MQ_ARM_PLL_BYPASS 11
|
||||
#define IMX8MQ_ARM_PLL_OUT 12
|
||||
|
||||
/* GPU PLL */
|
||||
#define IMX8MQ_GPU_PLL_REF_SEL 13
|
||||
#define IMX8MQ_GPU_PLL_REF_DIV 14
|
||||
#define IMX8MQ_GPU_PLL 15
|
||||
#define IMX8MQ_GPU_PLL_BYPASS 16
|
||||
#define IMX8MQ_GPU_PLL_OUT 17
|
||||
|
||||
/* VPU PLL */
|
||||
#define IMX8MQ_VPU_PLL_REF_SEL 18
|
||||
#define IMX8MQ_VPU_PLL_REF_DIV 19
|
||||
#define IMX8MQ_VPU_PLL 20
|
||||
#define IMX8MQ_VPU_PLL_BYPASS 21
|
||||
#define IMX8MQ_VPU_PLL_OUT 22
|
||||
|
||||
/* AUDIO PLL1 */
|
||||
#define IMX8MQ_AUDIO_PLL1_REF_SEL 23
|
||||
#define IMX8MQ_AUDIO_PLL1_REF_DIV 24
|
||||
#define IMX8MQ_AUDIO_PLL1 25
|
||||
#define IMX8MQ_AUDIO_PLL1_BYPASS 26
|
||||
#define IMX8MQ_AUDIO_PLL1_OUT 27
|
||||
|
||||
/* AUDIO PLL2 */
|
||||
#define IMX8MQ_AUDIO_PLL2_REF_SEL 28
|
||||
#define IMX8MQ_AUDIO_PLL2_REF_DIV 29
|
||||
#define IMX8MQ_AUDIO_PLL2 30
|
||||
#define IMX8MQ_AUDIO_PLL2_BYPASS 31
|
||||
#define IMX8MQ_AUDIO_PLL2_OUT 32
|
||||
|
||||
/* VIDEO PLL1 */
|
||||
#define IMX8MQ_VIDEO_PLL1_REF_SEL 33
|
||||
#define IMX8MQ_VIDEO_PLL1_REF_DIV 34
|
||||
#define IMX8MQ_VIDEO_PLL1 35
|
||||
#define IMX8MQ_VIDEO_PLL1_BYPASS 36
|
||||
#define IMX8MQ_VIDEO_PLL1_OUT 37
|
||||
|
||||
/* SYS1 PLL */
|
||||
#define IMX8MQ_SYS1_PLL1_REF_SEL 38
|
||||
#define IMX8MQ_SYS1_PLL1_REF_DIV 39
|
||||
#define IMX8MQ_SYS1_PLL1 40
|
||||
#define IMX8MQ_SYS1_PLL1_OUT 41
|
||||
#define IMX8MQ_SYS1_PLL1_OUT_DIV 42
|
||||
#define IMX8MQ_SYS1_PLL2 43
|
||||
#define IMX8MQ_SYS1_PLL2_DIV 44
|
||||
#define IMX8MQ_SYS1_PLL2_OUT 45
|
||||
|
||||
/* SYS2 PLL */
|
||||
#define IMX8MQ_SYS2_PLL1_REF_SEL 46
|
||||
#define IMX8MQ_SYS2_PLL1_REF_DIV 47
|
||||
#define IMX8MQ_SYS2_PLL1 48
|
||||
#define IMX8MQ_SYS2_PLL1_OUT 49
|
||||
#define IMX8MQ_SYS2_PLL1_OUT_DIV 50
|
||||
#define IMX8MQ_SYS2_PLL2 51
|
||||
#define IMX8MQ_SYS2_PLL2_DIV 52
|
||||
#define IMX8MQ_SYS2_PLL2_OUT 53
|
||||
|
||||
/* SYS3 PLL */
|
||||
#define IMX8MQ_SYS3_PLL1_REF_SEL 54
|
||||
#define IMX8MQ_SYS3_PLL1_REF_DIV 55
|
||||
#define IMX8MQ_SYS3_PLL1 56
|
||||
#define IMX8MQ_SYS3_PLL1_OUT 57
|
||||
#define IMX8MQ_SYS3_PLL1_OUT_DIV 58
|
||||
#define IMX8MQ_SYS3_PLL2 59
|
||||
#define IMX8MQ_SYS3_PLL2_DIV 60
|
||||
#define IMX8MQ_SYS3_PLL2_OUT 61
|
||||
|
||||
/* DRAM PLL */
|
||||
#define IMX8MQ_DRAM_PLL1_REF_SEL 62
|
||||
#define IMX8MQ_DRAM_PLL1_REF_DIV 63
|
||||
#define IMX8MQ_DRAM_PLL1 64
|
||||
#define IMX8MQ_DRAM_PLL1_OUT 65
|
||||
#define IMX8MQ_DRAM_PLL1_OUT_DIV 66
|
||||
#define IMX8MQ_DRAM_PLL2 67
|
||||
#define IMX8MQ_DRAM_PLL2_DIV 68
|
||||
#define IMX8MQ_DRAM_PLL2_OUT 69
|
||||
|
||||
/* SYS PLL DIV */
|
||||
#define IMX8MQ_SYS1_PLL_40M 70
|
||||
#define IMX8MQ_SYS1_PLL_80M 71
|
||||
#define IMX8MQ_SYS1_PLL_100M 72
|
||||
#define IMX8MQ_SYS1_PLL_133M 73
|
||||
#define IMX8MQ_SYS1_PLL_160M 74
|
||||
#define IMX8MQ_SYS1_PLL_200M 75
|
||||
#define IMX8MQ_SYS1_PLL_266M 76
|
||||
#define IMX8MQ_SYS1_PLL_400M 77
|
||||
#define IMX8MQ_SYS1_PLL_800M 78
|
||||
|
||||
#define IMX8MQ_SYS2_PLL_50M 79
|
||||
#define IMX8MQ_SYS2_PLL_100M 80
|
||||
#define IMX8MQ_SYS2_PLL_125M 81
|
||||
#define IMX8MQ_SYS2_PLL_166M 82
|
||||
#define IMX8MQ_SYS2_PLL_200M 83
|
||||
#define IMX8MQ_SYS2_PLL_250M 84
|
||||
#define IMX8MQ_SYS2_PLL_333M 85
|
||||
#define IMX8MQ_SYS2_PLL_500M 86
|
||||
#define IMX8MQ_SYS2_PLL_1000M 87
|
||||
|
||||
/* CCM ROOT clocks */
|
||||
/* A53 */
|
||||
#define IMX8MQ_CLK_A53_SRC 88
|
||||
#define IMX8MQ_CLK_A53_CG 89
|
||||
#define IMX8MQ_CLK_A53_DIV 90
|
||||
/* M4 */
|
||||
#define IMX8MQ_CLK_M4_SRC 91
|
||||
#define IMX8MQ_CLK_M4_CG 92
|
||||
#define IMX8MQ_CLK_M4_DIV 93
|
||||
/* VPU */
|
||||
#define IMX8MQ_CLK_VPU_SRC 94
|
||||
#define IMX8MQ_CLK_VPU_CG 95
|
||||
#define IMX8MQ_CLK_VPU_DIV 96
|
||||
/* GPU CORE */
|
||||
#define IMX8MQ_CLK_GPU_CORE_SRC 97
|
||||
#define IMX8MQ_CLK_GPU_CORE_CG 98
|
||||
#define IMX8MQ_CLK_GPU_CORE_DIV 99
|
||||
/* GPU SHADER */
|
||||
#define IMX8MQ_CLK_GPU_SHADER_SRC 100
|
||||
#define IMX8MQ_CLK_GPU_SHADER_CG 101
|
||||
#define IMX8MQ_CLK_GPU_SHADER_DIV 102
|
||||
|
||||
/* BUS TYPE */
|
||||
/* MAIN AXI */
|
||||
#define IMX8MQ_CLK_MAIN_AXI_SRC 103
|
||||
#define IMX8MQ_CLK_MAIN_AXI_CG 104
|
||||
#define IMX8MQ_CLK_MAIN_AXI_PRE_DIV 105
|
||||
#define IMX8MQ_CLK_MAIN_AXI_DIV 106
|
||||
/* ENET AXI */
|
||||
#define IMX8MQ_CLK_ENET_AXI_SRC 107
|
||||
#define IMX8MQ_CLK_ENET_AXI_CG 108
|
||||
#define IMX8MQ_CLK_ENET_AXI_PRE_DIV 109
|
||||
#define IMX8MQ_CLK_ENET_AXI_DIV 110
|
||||
/* NAND_USDHC_BUS */
|
||||
#define IMX8MQ_CLK_NAND_USDHC_BUS_SRC 111
|
||||
#define IMX8MQ_CLK_NAND_USDHC_BUS_CG 112
|
||||
#define IMX8MQ_CLK_NAND_USDHC_BUS_PRE_DIV 113
|
||||
#define IMX8MQ_CLK_NAND_USDHC_BUS_DIV 114
|
||||
/* VPU BUS */
|
||||
#define IMX8MQ_CLK_VPU_BUS_SRC 115
|
||||
#define IMX8MQ_CLK_VPU_BUS_CG 116
|
||||
#define IMX8MQ_CLK_VPU_BUS_PRE_DIV 117
|
||||
#define IMX8MQ_CLK_VPU_BUS_DIV 118
|
||||
/* DISP_AXI */
|
||||
#define IMX8MQ_CLK_DISP_AXI_SRC 119
|
||||
#define IMX8MQ_CLK_DISP_AXI_CG 120
|
||||
#define IMX8MQ_CLK_DISP_AXI_PRE_DIV 121
|
||||
#define IMX8MQ_CLK_DISP_AXI_DIV 122
|
||||
/* DISP APB */
|
||||
#define IMX8MQ_CLK_DISP_APB_SRC 123
|
||||
#define IMX8MQ_CLK_DISP_APB_CG 124
|
||||
#define IMX8MQ_CLK_DISP_APB_PRE_DIV 125
|
||||
#define IMX8MQ_CLK_DISP_APB_DIV 126
|
||||
/* DISP RTRM */
|
||||
#define IMX8MQ_CLK_DISP_RTRM_SRC 127
|
||||
#define IMX8MQ_CLK_DISP_RTRM_CG 128
|
||||
#define IMX8MQ_CLK_DISP_RTRM_PRE_DIV 129
|
||||
#define IMX8MQ_CLK_DISP_RTRM_DIV 130
|
||||
/* USB_BUS */
|
||||
#define IMX8MQ_CLK_USB_BUS_SRC 131
|
||||
#define IMX8MQ_CLK_USB_BUS_CG 132
|
||||
#define IMX8MQ_CLK_USB_BUS_PRE_DIV 133
|
||||
#define IMX8MQ_CLK_USB_BUS_DIV 134
|
||||
/* GPU_AXI */
|
||||
#define IMX8MQ_CLK_GPU_AXI_SRC 135
|
||||
#define IMX8MQ_CLK_GPU_AXI_CG 136
|
||||
#define IMX8MQ_CLK_GPU_AXI_PRE_DIV 137
|
||||
#define IMX8MQ_CLK_GPU_AXI_DIV 138
|
||||
/* GPU_AHB */
|
||||
#define IMX8MQ_CLK_GPU_AHB_SRC 139
|
||||
#define IMX8MQ_CLK_GPU_AHB_CG 140
|
||||
#define IMX8MQ_CLK_GPU_AHB_PRE_DIV 141
|
||||
#define IMX8MQ_CLK_GPU_AHB_DIV 142
|
||||
/* NOC */
|
||||
#define IMX8MQ_CLK_NOC_SRC 143
|
||||
#define IMX8MQ_CLK_NOC_CG 144
|
||||
#define IMX8MQ_CLK_NOC_PRE_DIV 145
|
||||
#define IMX8MQ_CLK_NOC_DIV 146
|
||||
/* NOC_APB */
|
||||
#define IMX8MQ_CLK_NOC_APB_SRC 147
|
||||
#define IMX8MQ_CLK_NOC_APB_CG 148
|
||||
#define IMX8MQ_CLK_NOC_APB_PRE_DIV 149
|
||||
#define IMX8MQ_CLK_NOC_APB_DIV 150
|
||||
|
||||
/* AHB */
|
||||
#define IMX8MQ_CLK_AHB_SRC 151
|
||||
#define IMX8MQ_CLK_AHB_CG 152
|
||||
#define IMX8MQ_CLK_AHB_PRE_DIV 153
|
||||
#define IMX8MQ_CLK_AHB_DIV 154
|
||||
/* AUDIO AHB */
|
||||
#define IMX8MQ_CLK_AUDIO_AHB_SRC 155
|
||||
#define IMX8MQ_CLK_AUDIO_AHB_CG 156
|
||||
#define IMX8MQ_CLK_AUDIO_AHB_PRE_DIV 157
|
||||
#define IMX8MQ_CLK_AUDIO_AHB_DIV 158
|
||||
|
||||
/* DRAM_ALT */
|
||||
#define IMX8MQ_CLK_DRAM_ALT_SRC 159
|
||||
#define IMX8MQ_CLK_DRAM_ALT_CG 160
|
||||
#define IMX8MQ_CLK_DRAM_ALT_PRE_DIV 161
|
||||
#define IMX8MQ_CLK_DRAM_ALT_DIV 162
|
||||
/* DRAM APB */
|
||||
#define IMX8MQ_CLK_DRAM_APB_SRC 163
|
||||
#define IMX8MQ_CLK_DRAM_APB_CG 164
|
||||
#define IMX8MQ_CLK_DRAM_APB_PRE_DIV 165
|
||||
#define IMX8MQ_CLK_DRAM_APB_DIV 166
|
||||
/* VPU_G1 */
|
||||
#define IMX8MQ_CLK_VPU_G1_SRC 167
|
||||
#define IMX8MQ_CLK_VPU_G1_CG 168
|
||||
#define IMX8MQ_CLK_VPU_G1_PRE_DIV 169
|
||||
#define IMX8MQ_CLK_VPU_G1_DIV 170
|
||||
/* VPU_G2 */
|
||||
#define IMX8MQ_CLK_VPU_G2_SRC 171
|
||||
#define IMX8MQ_CLK_VPU_G2_CG 172
|
||||
#define IMX8MQ_CLK_VPU_G2_PRE_DIV 173
|
||||
#define IMX8MQ_CLK_VPU_G2_DIV 174
|
||||
/* DISP_DTRC */
|
||||
#define IMX8MQ_CLK_DISP_DTRC_SRC 175
|
||||
#define IMX8MQ_CLK_DISP_DTRC_CG 176
|
||||
#define IMX8MQ_CLK_DISP_DTRC_PRE_DIV 177
|
||||
#define IMX8MQ_CLK_DISP_DTRC_DIV 178
|
||||
/* DISP_DC8000 */
|
||||
#define IMX8MQ_CLK_DISP_DC8000_SRC 179
|
||||
#define IMX8MQ_CLK_DISP_DC8000_CG 180
|
||||
#define IMX8MQ_CLK_DISP_DC8000_PRE_DIV 181
|
||||
#define IMX8MQ_CLK_DISP_DC8000_DIV 182
|
||||
/* PCIE_CTRL */
|
||||
#define IMX8MQ_CLK_PCIE1_CTRL_SRC 183
|
||||
#define IMX8MQ_CLK_PCIE1_CTRL_CG 184
|
||||
#define IMX8MQ_CLK_PCIE1_CTRL_PRE_DIV 185
|
||||
#define IMX8MQ_CLK_PCIE1_CTRL_DIV 186
|
||||
/* PCIE_PHY */
|
||||
#define IMX8MQ_CLK_PCIE1_PHY_SRC 187
|
||||
#define IMX8MQ_CLK_PCIE1_PHY_CG 188
|
||||
#define IMX8MQ_CLK_PCIE1_PHY_PRE_DIV 189
|
||||
#define IMX8MQ_CLK_PCIE1_PHY_DIV 190
|
||||
/* PCIE_AUX */
|
||||
#define IMX8MQ_CLK_PCIE1_AUX_SRC 191
|
||||
#define IMX8MQ_CLK_PCIE1_AUX_CG 192
|
||||
#define IMX8MQ_CLK_PCIE1_AUX_PRE_DIV 193
|
||||
#define IMX8MQ_CLK_PCIE1_AUX_DIV 194
|
||||
/* DC_PIXEL */
|
||||
#define IMX8MQ_CLK_DC_PIXEL_SRC 195
|
||||
#define IMX8MQ_CLK_DC_PIXEL_CG 196
|
||||
#define IMX8MQ_CLK_DC_PIXEL_PRE_DIV 197
|
||||
#define IMX8MQ_CLK_DC_PIXEL_DIV 198
|
||||
/* LCDIF_PIXEL */
|
||||
#define IMX8MQ_CLK_LCDIF_PIXEL_SRC 199
|
||||
#define IMX8MQ_CLK_LCDIF_PIXEL_CG 200
|
||||
#define IMX8MQ_CLK_LCDIF_PIXEL_PRE_DIV 201
|
||||
#define IMX8MQ_CLK_LCDIF_PIXEL_DIV 202
|
||||
/* SAI1~6 */
|
||||
#define IMX8MQ_CLK_SAI1_SRC 203
|
||||
#define IMX8MQ_CLK_SAI1_CG 204
|
||||
#define IMX8MQ_CLK_SAI1_PRE_DIV 205
|
||||
#define IMX8MQ_CLK_SAI1_DIV 206
|
||||
|
||||
#define IMX8MQ_CLK_SAI2_SRC 207
|
||||
#define IMX8MQ_CLK_SAI2_CG 208
|
||||
#define IMX8MQ_CLK_SAI2_PRE_DIV 209
|
||||
#define IMX8MQ_CLK_SAI2_DIV 210
|
||||
|
||||
#define IMX8MQ_CLK_SAI3_SRC 211
|
||||
#define IMX8MQ_CLK_SAI3_CG 212
|
||||
#define IMX8MQ_CLK_SAI3_PRE_DIV 213
|
||||
#define IMX8MQ_CLK_SAI3_DIV 214
|
||||
|
||||
#define IMX8MQ_CLK_SAI4_SRC 215
|
||||
#define IMX8MQ_CLK_SAI4_CG 216
|
||||
#define IMX8MQ_CLK_SAI4_PRE_DIV 217
|
||||
#define IMX8MQ_CLK_SAI4_DIV 218
|
||||
|
||||
#define IMX8MQ_CLK_SAI5_SRC 219
|
||||
#define IMX8MQ_CLK_SAI5_CG 220
|
||||
#define IMX8MQ_CLK_SAI5_PRE_DIV 221
|
||||
#define IMX8MQ_CLK_SAI5_DIV 222
|
||||
|
||||
#define IMX8MQ_CLK_SAI6_SRC 223
|
||||
#define IMX8MQ_CLK_SAI6_CG 224
|
||||
#define IMX8MQ_CLK_SAI6_PRE_DIV 225
|
||||
#define IMX8MQ_CLK_SAI6_DIV 226
|
||||
/* SPDIF1 */
|
||||
#define IMX8MQ_CLK_SPDIF1_SRC 227
|
||||
#define IMX8MQ_CLK_SPDIF1_CG 228
|
||||
#define IMX8MQ_CLK_SPDIF1_PRE_DIV 229
|
||||
#define IMX8MQ_CLK_SPDIF1_DIV 230
|
||||
/* SPDIF2 */
|
||||
#define IMX8MQ_CLK_SPDIF2_SRC 231
|
||||
#define IMX8MQ_CLK_SPDIF2_CG 232
|
||||
#define IMX8MQ_CLK_SPDIF2_PRE_DIV 233
|
||||
#define IMX8MQ_CLK_SPDIF2_DIV 234
|
||||
/* ENET_REF */
|
||||
#define IMX8MQ_CLK_ENET_REF_SRC 235
|
||||
#define IMX8MQ_CLK_ENET_REF_CG 236
|
||||
#define IMX8MQ_CLK_ENET_REF_PRE_DIV 237
|
||||
#define IMX8MQ_CLK_ENET_REF_DIV 238
|
||||
/* ENET_TIMER */
|
||||
#define IMX8MQ_CLK_ENET_TIMER_SRC 239
|
||||
#define IMX8MQ_CLK_ENET_TIMER_CG 240
|
||||
#define IMX8MQ_CLK_ENET_TIMER_PRE_DIV 241
|
||||
#define IMX8MQ_CLK_ENET_TIMER_DIV 242
|
||||
/* ENET_PHY */
|
||||
#define IMX8MQ_CLK_ENET_PHY_REF_SRC 243
|
||||
#define IMX8MQ_CLK_ENET_PHY_REF_CG 244
|
||||
#define IMX8MQ_CLK_ENET_PHY_REF_PRE_DIV 245
|
||||
#define IMX8MQ_CLK_ENET_PHY_REF_DIV 246
|
||||
/* NAND */
|
||||
#define IMX8MQ_CLK_NAND_SRC 247
|
||||
#define IMX8MQ_CLK_NAND_CG 248
|
||||
#define IMX8MQ_CLK_NAND_PRE_DIV 249
|
||||
#define IMX8MQ_CLK_NAND_DIV 250
|
||||
/* QSPI */
|
||||
#define IMX8MQ_CLK_QSPI_SRC 251
|
||||
#define IMX8MQ_CLK_QSPI_CG 252
|
||||
#define IMX8MQ_CLK_QSPI_PRE_DIV 253
|
||||
#define IMX8MQ_CLK_QSPI_DIV 254
|
||||
/* USDHC1 */
|
||||
#define IMX8MQ_CLK_USDHC1_SRC 255
|
||||
#define IMX8MQ_CLK_USDHC1_CG 256
|
||||
#define IMX8MQ_CLK_USDHC1_PRE_DIV 257
|
||||
#define IMX8MQ_CLK_USDHC1_DIV 258
|
||||
/* USDHC2 */
|
||||
#define IMX8MQ_CLK_USDHC2_SRC 259
|
||||
#define IMX8MQ_CLK_USDHC2_CG 260
|
||||
#define IMX8MQ_CLK_USDHC2_PRE_DIV 261
|
||||
#define IMX8MQ_CLK_USDHC2_DIV 262
|
||||
/* I2C1 */
|
||||
#define IMX8MQ_CLK_I2C1_SRC 263
|
||||
#define IMX8MQ_CLK_I2C1_CG 264
|
||||
#define IMX8MQ_CLK_I2C1_PRE_DIV 265
|
||||
#define IMX8MQ_CLK_I2C1_DIV 266
|
||||
/* I2C2 */
|
||||
#define IMX8MQ_CLK_I2C2_SRC 267
|
||||
#define IMX8MQ_CLK_I2C2_CG 268
|
||||
#define IMX8MQ_CLK_I2C2_PRE_DIV 269
|
||||
#define IMX8MQ_CLK_I2C2_DIV 270
|
||||
/* I2C3 */
|
||||
#define IMX8MQ_CLK_I2C3_SRC 271
|
||||
#define IMX8MQ_CLK_I2C3_CG 272
|
||||
#define IMX8MQ_CLK_I2C3_PRE_DIV 273
|
||||
#define IMX8MQ_CLK_I2C3_DIV 274
|
||||
/* I2C4 */
|
||||
#define IMX8MQ_CLK_I2C4_SRC 275
|
||||
#define IMX8MQ_CLK_I2C4_CG 276
|
||||
#define IMX8MQ_CLK_I2C4_PRE_DIV 277
|
||||
#define IMX8MQ_CLK_I2C4_DIV 278
|
||||
/* UART1 */
|
||||
#define IMX8MQ_CLK_UART1_SRC 279
|
||||
#define IMX8MQ_CLK_UART1_CG 280
|
||||
#define IMX8MQ_CLK_UART1_PRE_DIV 281
|
||||
#define IMX8MQ_CLK_UART1_DIV 282
|
||||
/* UART2 */
|
||||
#define IMX8MQ_CLK_UART2_SRC 283
|
||||
#define IMX8MQ_CLK_UART2_CG 284
|
||||
#define IMX8MQ_CLK_UART2_PRE_DIV 285
|
||||
#define IMX8MQ_CLK_UART2_DIV 286
|
||||
/* UART3 */
|
||||
#define IMX8MQ_CLK_UART3_SRC 287
|
||||
#define IMX8MQ_CLK_UART3_CG 288
|
||||
#define IMX8MQ_CLK_UART3_PRE_DIV 289
|
||||
#define IMX8MQ_CLK_UART3_DIV 290
|
||||
/* UART4 */
|
||||
#define IMX8MQ_CLK_UART4_SRC 291
|
||||
#define IMX8MQ_CLK_UART4_CG 292
|
||||
#define IMX8MQ_CLK_UART4_PRE_DIV 293
|
||||
#define IMX8MQ_CLK_UART4_DIV 294
|
||||
/* USB_CORE_REF */
|
||||
#define IMX8MQ_CLK_USB_CORE_REF_SRC 295
|
||||
#define IMX8MQ_CLK_USB_CORE_REF_CG 296
|
||||
#define IMX8MQ_CLK_USB_CORE_REF_PRE_DIV 297
|
||||
#define IMX8MQ_CLK_USB_CORE_REF_DIV 298
|
||||
/* USB_PHY_REF */
|
||||
#define IMX8MQ_CLK_USB_PHY_REF_SRC 299
|
||||
#define IMX8MQ_CLK_USB_PHY_REF_CG 300
|
||||
#define IMX8MQ_CLK_USB_PHY_REF_PRE_DIV 301
|
||||
#define IMX8MQ_CLK_USB_PHY_REF_DIV 302
|
||||
/* ECSPI1 */
|
||||
#define IMX8MQ_CLK_ECSPI1_SRC 303
|
||||
#define IMX8MQ_CLK_ECSPI1_CG 304
|
||||
#define IMX8MQ_CLK_ECSPI1_PRE_DIV 305
|
||||
#define IMX8MQ_CLK_ECSPI1_DIV 306
|
||||
/* ECSPI2 */
|
||||
#define IMX8MQ_CLK_ECSPI2_SRC 307
|
||||
#define IMX8MQ_CLK_ECSPI2_CG 308
|
||||
#define IMX8MQ_CLK_ECSPI2_PRE_DIV 309
|
||||
#define IMX8MQ_CLK_ECSPI2_DIV 310
|
||||
/* PWM1 */
|
||||
#define IMX8MQ_CLK_PWM1_SRC 311
|
||||
#define IMX8MQ_CLK_PWM1_CG 312
|
||||
#define IMX8MQ_CLK_PWM1_PRE_DIV 313
|
||||
#define IMX8MQ_CLK_PWM1_DIV 314
|
||||
/* PWM2 */
|
||||
#define IMX8MQ_CLK_PWM2_SRC 315
|
||||
#define IMX8MQ_CLK_PWM2_CG 316
|
||||
#define IMX8MQ_CLK_PWM2_PRE_DIV 317
|
||||
#define IMX8MQ_CLK_PWM2_DIV 318
|
||||
/* PWM3 */
|
||||
#define IMX8MQ_CLK_PWM3_SRC 319
|
||||
#define IMX8MQ_CLK_PWM3_CG 320
|
||||
#define IMX8MQ_CLK_PWM3_PRE_DIV 321
|
||||
#define IMX8MQ_CLK_PWM3_DIV 322
|
||||
/* PWM4 */
|
||||
#define IMX8MQ_CLK_PWM4_SRC 323
|
||||
#define IMX8MQ_CLK_PWM4_CG 324
|
||||
#define IMX8MQ_CLK_PWM4_PRE_DIV 325
|
||||
#define IMX8MQ_CLK_PWM4_DIV 326
|
||||
/* GPT1 */
|
||||
#define IMX8MQ_CLK_GPT1_SRC 327
|
||||
#define IMX8MQ_CLK_GPT1_CG 328
|
||||
#define IMX8MQ_CLK_GPT1_PRE_DIV 329
|
||||
#define IMX8MQ_CLK_GPT1_DIV 330
|
||||
/* WDOG */
|
||||
#define IMX8MQ_CLK_WDOG_SRC 331
|
||||
#define IMX8MQ_CLK_WDOG_CG 332
|
||||
#define IMX8MQ_CLK_WDOG_PRE_DIV 333
|
||||
#define IMX8MQ_CLK_WDOG_DIV 334
|
||||
/* WRCLK */
|
||||
#define IMX8MQ_CLK_WRCLK_SRC 335
|
||||
#define IMX8MQ_CLK_WRCLK_CG 336
|
||||
#define IMX8MQ_CLK_WRCLK_PRE_DIV 337
|
||||
#define IMX8MQ_CLK_WRCLK_DIV 338
|
||||
/* DSI_CORE */
|
||||
#define IMX8MQ_CLK_DSI_CORE_SRC 339
|
||||
#define IMX8MQ_CLK_DSI_CORE_CG 340
|
||||
#define IMX8MQ_CLK_DSI_CORE_PRE_DIV 341
|
||||
#define IMX8MQ_CLK_DSI_CORE_DIV 342
|
||||
/* DSI_PHY */
|
||||
#define IMX8MQ_CLK_DSI_PHY_REF_SRC 343
|
||||
#define IMX8MQ_CLK_DSI_PHY_REF_CG 344
|
||||
#define IMX8MQ_CLK_DSI_PHY_REF_PRE_DIV 345
|
||||
#define IMX8MQ_CLK_DSI_PHY_REF_DIV 346
|
||||
/* DSI_DBI */
|
||||
#define IMX8MQ_CLK_DSI_DBI_SRC 347
|
||||
#define IMX8MQ_CLK_DSI_DBI_CG 348
|
||||
#define IMX8MQ_CLK_DSI_DBI_PRE_DIV 349
|
||||
#define IMX8MQ_CLK_DSI_DBI_DIV 350
|
||||
/*DSI_ESC */
|
||||
#define IMX8MQ_CLK_DSI_ESC_SRC 351
|
||||
#define IMX8MQ_CLK_DSI_ESC_CG 352
|
||||
#define IMX8MQ_CLK_DSI_ESC_PRE_DIV 353
|
||||
#define IMX8MQ_CLK_DSI_ESC_DIV 354
|
||||
/* CSI1_CORE */
|
||||
#define IMX8MQ_CLK_CSI1_CORE_SRC 355
|
||||
#define IMX8MQ_CLK_CSI1_CORE_CG 356
|
||||
#define IMX8MQ_CLK_CSI1_CORE_PRE_DIV 357
|
||||
#define IMX8MQ_CLK_CSI1_CORE_DIV 358
|
||||
/* CSI1_PHY */
|
||||
#define IMX8MQ_CLK_CSI1_PHY_REF_SRC 359
|
||||
#define IMX8MQ_CLK_CSI1_PHY_REF_CG 360
|
||||
#define IMX8MQ_CLK_CSI1_PHY_REF_PRE_DIV 361
|
||||
#define IMX8MQ_CLK_CSI1_PHY_REF_DIV 362
|
||||
/* CSI_ESC */
|
||||
#define IMX8MQ_CLK_CSI1_ESC_SRC 363
|
||||
#define IMX8MQ_CLK_CSI1_ESC_CG 364
|
||||
#define IMX8MQ_CLK_CSI1_ESC_PRE_DIV 365
|
||||
#define IMX8MQ_CLK_CSI1_ESC_DIV 366
|
||||
/* CSI2_CORE */
|
||||
#define IMX8MQ_CLK_CSI2_CORE_SRC 367
|
||||
#define IMX8MQ_CLK_CSI2_CORE_CG 368
|
||||
#define IMX8MQ_CLK_CSI2_CORE_PRE_DIV 369
|
||||
#define IMX8MQ_CLK_CSI2_CORE_DIV 370
|
||||
/* CSI2_PHY */
|
||||
#define IMX8MQ_CLK_CSI2_PHY_REF_SRC 371
|
||||
#define IMX8MQ_CLK_CSI2_PHY_REF_CG 372
|
||||
#define IMX8MQ_CLK_CSI2_PHY_REF_PRE_DIV 373
|
||||
#define IMX8MQ_CLK_CSI2_PHY_REF_DIV 374
|
||||
/* CSI2_ESC */
|
||||
#define IMX8MQ_CLK_CSI2_ESC_SRC 375
|
||||
#define IMX8MQ_CLK_CSI2_ESC_CG 376
|
||||
#define IMX8MQ_CLK_CSI2_ESC_PRE_DIV 377
|
||||
#define IMX8MQ_CLK_CSI2_ESC_DIV 378
|
||||
/* PCIE2_CTRL */
|
||||
#define IMX8MQ_CLK_PCIE2_CTRL_SRC 379
|
||||
#define IMX8MQ_CLK_PCIE2_CTRL_CG 380
|
||||
#define IMX8MQ_CLK_PCIE2_CTRL_PRE_DIV 381
|
||||
#define IMX8MQ_CLK_PCIE2_CTRL_DIV 382
|
||||
/* PCIE2_PHY */
|
||||
#define IMX8MQ_CLK_PCIE2_PHY_SRC 383
|
||||
#define IMX8MQ_CLK_PCIE2_PHY_CG 384
|
||||
#define IMX8MQ_CLK_PCIE2_PHY_PRE_DIV 385
|
||||
#define IMX8MQ_CLK_PCIE2_PHY_DIV 386
|
||||
/* PCIE2_AUX */
|
||||
#define IMX8MQ_CLK_PCIE2_AUX_SRC 387
|
||||
#define IMX8MQ_CLK_PCIE2_AUX_CG 388
|
||||
#define IMX8MQ_CLK_PCIE2_AUX_PRE_DIV 389
|
||||
#define IMX8MQ_CLK_PCIE2_AUX_DIV 390
|
||||
/* ECSPI3 */
|
||||
#define IMX8MQ_CLK_ECSPI3_SRC 391
|
||||
#define IMX8MQ_CLK_ECSPI3_CG 392
|
||||
#define IMX8MQ_CLK_ECSPI3_PRE_DIV 393
|
||||
#define IMX8MQ_CLK_ECSPI3_DIV 394
|
||||
|
||||
/* CCGR clocks */
|
||||
#define IMX8MQ_CLK_A53_ROOT 395
|
||||
#define IMX8MQ_CLK_DRAM_ROOT 396
|
||||
#define IMX8MQ_CLK_ECSPI1_ROOT 397
|
||||
#define IMX8MQ_CLK_ECSPI2_ROOT 398
|
||||
#define IMX8MQ_CLK_ECSPI3_ROOT 399
|
||||
#define IMX8MQ_CLK_ENET1_ROOT 400
|
||||
#define IMX8MQ_CLK_GPT1_ROOT 401
|
||||
#define IMX8MQ_CLK_I2C1_ROOT 402
|
||||
#define IMX8MQ_CLK_I2C2_ROOT 403
|
||||
#define IMX8MQ_CLK_I2C3_ROOT 404
|
||||
#define IMX8MQ_CLK_I2C4_ROOT 405
|
||||
#define IMX8MQ_CLK_M4_ROOT 406
|
||||
#define IMX8MQ_CLK_PCIE1_ROOT 407
|
||||
#define IMX8MQ_CLK_PCIE2_ROOT 408
|
||||
#define IMX8MQ_CLK_PWM1_ROOT 409
|
||||
#define IMX8MQ_CLK_PWM2_ROOT 410
|
||||
#define IMX8MQ_CLK_PWM3_ROOT 411
|
||||
#define IMX8MQ_CLK_PWM4_ROOT 412
|
||||
#define IMX8MQ_CLK_QSPI_ROOT 413
|
||||
#define IMX8MQ_CLK_SAI1_ROOT 414
|
||||
#define IMX8MQ_CLK_SAI2_ROOT 415
|
||||
#define IMX8MQ_CLK_SAI3_ROOT 416
|
||||
#define IMX8MQ_CLK_SAI4_ROOT 417
|
||||
#define IMX8MQ_CLK_SAI5_ROOT 418
|
||||
#define IMX8MQ_CLK_SAI6_ROOT 419
|
||||
#define IMX8MQ_CLK_UART1_ROOT 420
|
||||
#define IMX8MQ_CLK_UART2_ROOT 421
|
||||
#define IMX8MQ_CLK_UART3_ROOT 422
|
||||
#define IMX8MQ_CLK_UART4_ROOT 423
|
||||
#define IMX8MQ_CLK_USB1_CTRL_ROOT 424
|
||||
#define IMX8MQ_CLK_USB2_CTRL_ROOT 425
|
||||
#define IMX8MQ_CLK_USB1_PHY_ROOT 426
|
||||
#define IMX8MQ_CLK_USB2_PHY_ROOT 427
|
||||
#define IMX8MQ_CLK_USDHC1_ROOT 428
|
||||
#define IMX8MQ_CLK_USDHC2_ROOT 429
|
||||
#define IMX8MQ_CLK_WDOG1_ROOT 430
|
||||
#define IMX8MQ_CLK_WDOG2_ROOT 431
|
||||
#define IMX8MQ_CLK_WDOG3_ROOT 432
|
||||
#define IMX8MQ_CLK_GPU_ROOT 433
|
||||
#define IMX8MQ_CLK_HEVC_ROOT 434
|
||||
#define IMX8MQ_CLK_AVC_ROOT 435
|
||||
#define IMX8MQ_CLK_VP9_ROOT 436
|
||||
#define IMX8MQ_CLK_HEVC_INTER_ROOT 437
|
||||
#define IMX8MQ_CLK_DISP_ROOT 438
|
||||
#define IMX8MQ_CLK_HDMI_ROOT 439
|
||||
#define IMX8MQ_CLK_HDMI_PHY_ROOT 440
|
||||
#define IMX8MQ_CLK_VPU_DEC_ROOT 441
|
||||
#define IMX8MQ_CLK_CSI1_ROOT 442
|
||||
#define IMX8MQ_CLK_CSI2_ROOT 443
|
||||
#define IMX8MQ_CLK_RAWNAND_ROOT 444
|
||||
#define IMX8MQ_CLK_SDMA1_ROOT 445
|
||||
#define IMX8MQ_CLK_SDMA2_ROOT 446
|
||||
#define IMX8MQ_CLK_VPU_G1_ROOT 447
|
||||
#define IMX8MQ_CLK_VPU_G2_ROOT 448
|
||||
|
||||
/* SCCG PLL GATE */
|
||||
#define IMX8MQ_SYS1_PLL_OUT 449
|
||||
#define IMX8MQ_SYS2_PLL_OUT 450
|
||||
#define IMX8MQ_SYS3_PLL_OUT 451
|
||||
#define IMX8MQ_DRAM_PLL_OUT 452
|
||||
|
||||
#define IMX8MQ_GPT_3M_CLK 453
|
||||
|
||||
#define IMX8MQ_CLK_IPG_ROOT 454
|
||||
#define IMX8MQ_CLK_IPG_AUDIO_ROOT 455
|
||||
#define IMX8MQ_CLK_SAI1_IPG 456
|
||||
#define IMX8MQ_CLK_SAI2_IPG 457
|
||||
#define IMX8MQ_CLK_SAI3_IPG 458
|
||||
#define IMX8MQ_CLK_SAI4_IPG 459
|
||||
#define IMX8MQ_CLK_SAI5_IPG 460
|
||||
#define IMX8MQ_CLK_SAI6_IPG 461
|
||||
|
||||
/* DSI AHB/IPG clocks */
|
||||
/* rxesc clock */
|
||||
#define IMX8MQ_CLK_DSI_AHB_SRC 462
|
||||
#define IMX8MQ_CLK_DSI_AHB_CG 463
|
||||
#define IMX8MQ_CLK_DSI_AHB_PRE_DIV 464
|
||||
#define IMX8MQ_CLK_DSI_AHB_DIV 465
|
||||
/* txesc clock */
|
||||
#define IMX8MQ_CLK_DSI_IPG_DIV 466
|
||||
|
||||
/* VIDEO2 PLL */
|
||||
#define IMX8MQ_VIDEO2_PLL1_REF_SEL 467
|
||||
#define IMX8MQ_VIDEO2_PLL1_REF_DIV 468
|
||||
#define IMX8MQ_VIDEO2_PLL1 469
|
||||
#define IMX8MQ_VIDEO2_PLL1_OUT 470
|
||||
#define IMX8MQ_VIDEO2_PLL1_OUT_DIV 471
|
||||
#define IMX8MQ_VIDEO2_PLL2 472
|
||||
#define IMX8MQ_VIDEO2_PLL2_DIV 473
|
||||
#define IMX8MQ_VIDEO2_PLL2_OUT 474
|
||||
#define IMX8MQ_CLK_TMU_ROOT 475
|
||||
|
||||
#define IMX8MQ_CLK_END 476
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
|
||||
632
include/dt-bindings/pinctrl/pins-imx8mq.h
Normal file
632
include/dt-bindings/pinctrl/pins-imx8mq.h
Normal file
|
|
@ -0,0 +1,632 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __DTS_IMX8MQ_PINFUNC_H
|
||||
#define __DTS_IMX8MQ_PINFUNC_H
|
||||
|
||||
/*
|
||||
* The pin function ID is a tuple of
|
||||
* <mux_reg conf_reg input_reg mux_mode input_val>
|
||||
*/
|
||||
|
||||
#define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B 0x030 0x298 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE 0x034 0x29C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG 0x038 0x2A0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG 0x03C 0x2A4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG 0x040 0x2A8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG 0x044 0x2AC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG 0x048 0x2B0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG 0x04C 0x2B4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x050 0x2B8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID 0x054 0x2BC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS 0x054 0x2BC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0 0x058 0x2C0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1 0x05C 0x2C4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x060 0x2C8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2 0x060 0x2C8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x064 0x2CC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB 0x064 0x2CC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1
|
||||
#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0 0x0D4 0x33C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1 0x0D8 0x340 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2 0x0DC 0x344 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3 0x0E0 0x348 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4 0x0E4 0x34C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK 0x0F0 0x358 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0 0x0F4 0x35C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1 0x0F8 0x360 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2 0x0FC 0x364 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3 0x100 0x368 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0 0x104 0x36C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1 0x108 0x370 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2 0x10C 0x374 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3 0x110 0x378 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4 0x114 0x37C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5 0x118 0x380 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6 0x11C 0x384 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7 0x120 0x388 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8 0x124 0x38C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10 0x12C 0x394 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13 0x138 0x3A0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14 0x13C 0x3A4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0 0x140 0x3A8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1 0x144 0x3AC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2 0x148 0x3B0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3 0x14C 0x3B4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC 0x14C 0x3B4 0x4CC 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC 0x154 0x3BC 0x4CC 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x52C 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK 0x158 0x3C0 0x4C8 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK 0x158 0x3C0 0x000 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK 0x158 0x3C0 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC 0x15C 0x3C4 0x4C4 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC 0x15C 0x3C4 0x4E4 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK 0x15C 0x3C4 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x15C 0x3C4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15 0x15C 0x3C4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK 0x160 0x3C8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK 0x160 0x3C8 0x4D0 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL 0x160 0x3C8 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x160 0x3C8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16 0x160 0x3C8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0x164 0x3CC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0 0x164 0x3CC 0x4D4 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0 0x164 0x3CC 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x164 0x3CC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0 0x164 0x3CC 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17 0x164 0x3CC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0x168 0x3D0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1 0x168 0x3D0 0x4D8 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1 0x168 0x3D0 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x168 0x3D0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1 0x168 0x3D0 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18 0x168 0x3D0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0x16C 0x3D4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2 0x16C 0x3D4 0x4DC 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2 0x16C 0x3D4 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x16C 0x3D4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2 0x16C 0x3D4 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19 0x16C 0x3D4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0x170 0x3D8 0x4E0 0x0 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3 0x170 0x3D8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3 0x170 0x3D8 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x170 0x3D8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3 0x170 0x3D8 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20 0x170 0x3D8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4 0x174 0x3DC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x174 0x3DC 0x51C 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK 0x174 0x3DC 0x510 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4 0x174 0x3DC 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x174 0x3DC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4 0x174 0x3DC 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21 0x174 0x3DC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5 0x178 0x3E0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x178 0x3E0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0x178 0x3E0 0x514 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC 0x178 0x3E0 0x4C4 0x3 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5 0x178 0x3E0 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x178 0x3E0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5 0x178 0x3E0 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22 0x178 0x3E0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6 0x17C 0x3E4 0x520 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x17C 0x3E4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0x17C 0x3E4 0x518 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6 0x17C 0x3E4 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x17C 0x3E4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6 0x17C 0x3E4 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23 0x17C 0x3E4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7 0x180 0x3E8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK 0x180 0x3E8 0x530 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0x180 0x3E8 0x4CC 0x2 0x4
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0x180 0x3E8 0x000 0x3 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7 0x180 0x3E8 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x180 0x3E8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7 0x180 0x3E8 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24 0x180 0x3E8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x184 0x3EC 0x4CC 0x0 0x3
|
||||
#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC 0x184 0x3EC 0x4EC 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO 0x184 0x3EC 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x184 0x3EC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25 0x184 0x3EC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x188 0x3F0 0x4C8 0x0 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK 0x188 0x3F0 0x4E8 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI 0x188 0x3F0 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11 0x188 0x3F0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26 0x188 0x3F0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0x18C 0x3F4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0 0x18C 0x3F4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8 0x18C 0x3F4 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x18C 0x3F4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8 0x18C 0x3F4 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27 0x18C 0x3F4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0x190 0x3F8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1 0x190 0x3F8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9 0x190 0x3F8 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x190 0x3F8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9 0x190 0x3F8 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28 0x190 0x3F8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x194 0x3FC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2 0x194 0x3FC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10 0x194 0x3FC 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x194 0x3FC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10 0x194 0x3FC 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29 0x194 0x3FC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0x198 0x400 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3 0x198 0x400 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11 0x198 0x400 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x198 0x400 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11 0x198 0x400 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30 0x198 0x400 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0x19C 0x404 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0x19C 0x404 0x510 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK 0x19C 0x404 0x51C 0x2 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12 0x19C 0x404 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19C 0x404 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12 0x19C 0x404 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31 0x19C 0x404 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0x1A0 0x408 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x1A0 0x408 0x514 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0x1A0 0x408 0x000 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13 0x1A0 0x408 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x1A0 0x408 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13 0x1A0 0x408 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0 0x1A0 0x408 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0x1A4 0x40C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC 0x1A4 0x40C 0x518 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC 0x1A4 0x40C 0x520 0x2 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14 0x1A4 0x40C 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1A4 0x40C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14 0x1A4 0x40C 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1 0x1A4 0x40C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0x1A8 0x410 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK 0x1A8 0x410 0x530 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15 0x1A8 0x410 0x000 0x4 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1A8 0x410 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15 0x1A8 0x410 0x000 0x6 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2 0x1A8 0x410 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x1AC 0x414 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK 0x1AC 0x414 0x52C 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0x1AC 0x414 0x4C8 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1AC 0x414 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2
|
||||
#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2
|
||||
#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT 0x1C0 0x428 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK 0x1C4 0x42C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x52C 0x1 0x2
|
||||
#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR 0x1C8 0x430 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x2
|
||||
#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3 0x1E0 0x448 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x52C 0x2 0x3
|
||||
#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4 0x1E4 0x44C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5 0x1E8 0x450 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6 0x1EC 0x454 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7 0x1F0 0x458 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8 0x1F4 0x45C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9 0x1F8 0x460 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10 0x1FC 0x464 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11 0x200 0x468 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12 0x204 0x46C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13 0x208 0x470 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14 0x20C 0x474 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15 0x210 0x478 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16 0x214 0x47C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2
|
||||
#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17 0x218 0x480 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18 0x21C 0x484 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19 0x220 0x488 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20 0x224 0x48C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21 0x228 0x490 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x22C 0x494 0x524 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22 0x22C 0x494 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x230 0x498 0x528 0x2 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23 0x230 0x498 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24 0x234 0x49C 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25 0x238 0x4A0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26 0x23C 0x4A4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1
|
||||
#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27 0x240 0x4A8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2
|
||||
#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28 0x244 0x4AC 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3
|
||||
#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29 0x248 0x4B0 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x24C 0x4B4 0x524 0x2 0x1
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30 0x24C 0x4B4 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x250 0x4B8 0x528 0x2 0x1
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0
|
||||
#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31 0x250 0x4B8 0x000 0x7 0x0
|
||||
#define MX8MQ_IOMUXC_TEST_MODE 0x000 0x254 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_BOOT_MODE0 0x000 0x258 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_BOOT_MODE1 0x000 0x25C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_JTAG_MOD 0x000 0x260 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_JTAG_TRST_B 0x000 0x264 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_JTAG_TDI 0x000 0x268 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_JTAG_TMS 0x000 0x26C 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_JTAG_TCK 0x000 0x270 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_JTAG_TDO 0x000 0x274 0x000 0x0 0x0
|
||||
#define MX8MQ_IOMUXC_RTC 0x000 0x278 0x000 0x0 0x0
|
||||
|
||||
#endif /* __DTS_IMX8MQ_PINFUNC_H */
|
||||
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Reference in a new issue