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https://github.com/AsahiLinux/u-boot
synced 2024-11-29 08:01:08 +00:00
imx: HAB: Update hab codes to support ARM64 and i.MX8M
There are some changes to support ARM64 i.MX8M platform in this patches: 1. The hab_rvt base and function vectors are different as i.MX6/7 2. Need to bypass an workaround for i.MX6 to fix problem in MMU. 3. The x18 register needed save & restore before calling any HAB API. According to ARM procedure call spec, the x18 is caller saved when it is used as temporary register. So calling HAB API may scratch this register, and cause crash once accessing the gd pointer. On ARMv7, the r9 is callee saved when it is used as variable register. So no need to save & restore it. 4. Add SEC_CONFIG fuse for iMX8M When current EL is not EL3, the direct calling to HAB will fail because CAAM/SNVS can't initialize at non-secure mode. In this case, we use SIP call to run the HAB in ATF. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan
Stefano Babic
parent
c428ca80c2
commit
507da978fa
2 changed files with 218 additions and 25 deletions
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@ -165,6 +165,18 @@ typedef void hapi_clock_init_t(void);
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#define HAB_ENG_RTL 0x77 /* RTL simulation engine */
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#define HAB_ENG_SW 0xff /* Software engine */
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#ifdef CONFIG_ARM64
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#define HAB_RVT_BASE 0x00000880
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#define HAB_RVT_ENTRY (*(ulong *)(HAB_RVT_BASE + 0x08))
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#define HAB_RVT_EXIT (*(ulong *)(HAB_RVT_BASE + 0x10))
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#define HAB_RVT_CHECK_TARGET (*(ulong *)(HAB_RVT_BASE + 0x18))
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#define HAB_RVT_AUTHENTICATE_IMAGE (*(ulong *)(HAB_RVT_BASE + 0x20))
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#define HAB_RVT_REPORT_EVENT (*(ulong *)(HAB_RVT_BASE + 0x40))
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#define HAB_RVT_REPORT_STATUS (*(ulong *)(HAB_RVT_BASE + 0x48))
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#define HAB_RVT_FAILSAFE (*(ulong *)(HAB_RVT_BASE + 0x50))
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#else
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#ifdef CONFIG_ROM_UNIFIED_SECTIONS
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#define HAB_RVT_BASE 0x00000100
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#else
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@ -186,6 +198,8 @@ typedef void hapi_clock_init_t(void);
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#define HAB_RVT_REPORT_STATUS (*(uint32_t *)(HAB_RVT_BASE + 0x24))
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#define HAB_RVT_FAILSAFE (*(uint32_t *)(HAB_RVT_BASE + 0x28))
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#endif /*CONFIG_ARM64*/
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#define HAB_CID_ROM 0 /**< ROM Caller ID */
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#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/
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@ -10,10 +10,14 @@
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#include <mapmem.h>
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#include <image.h>
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#include <asm/io.h>
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#include <asm/global_data.h>
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#include <asm/system.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/hab.h>
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#include <linux/arm-smccc.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define ALIGN_SIZE 0x1000
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#define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8
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@ -21,7 +25,7 @@
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#define MX6SL_PU_IROM_MMU_EN_VAR 0x00901c60
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#define IS_HAB_ENABLED_BIT \
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(is_soc_type(MXC_SOC_MX7ULP) ? 0x80000000 : \
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(is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2))
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((is_soc_type(MXC_SOC_MX7) || is_soc_type(MXC_SOC_IMX8M)) ? 0x2000000 : 0x2))
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static int ivt_header_error(const char *err_str, struct ivt_header *ivt_hdr)
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{
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@ -48,6 +52,194 @@ static int verify_ivt_header(struct ivt_header *ivt_hdr)
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return result;
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}
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#ifdef CONFIG_ARM64
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#define FSL_SIP_HAB 0xC2000007
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#define FSL_SIP_HAB_AUTHENTICATE 0x00
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#define FSL_SIP_HAB_ENTRY 0x01
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#define FSL_SIP_HAB_EXIT 0x02
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#define FSL_SIP_HAB_REPORT_EVENT 0x03
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#define FSL_SIP_HAB_REPORT_STATUS 0x04
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#define FSL_SIP_HAB_FAILSAFE 0x05
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#define FSL_SIP_HAB_CHECK_TARGET 0x06
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static volatile gd_t *gd_save;
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#endif
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static inline void save_gd(void)
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{
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#ifdef CONFIG_ARM64
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gd_save = gd;
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#endif
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}
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static inline void restore_gd(void)
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{
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#ifdef CONFIG_ARM64
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/*
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* Make will already error that reserving x18 is not supported at the
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* time of writing, clang: error: unknown argument: '-ffixed-x18'
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*/
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__asm__ volatile("mov x18, %0\n" : : "r" (gd_save));
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#endif
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}
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enum hab_status hab_rvt_report_event(enum hab_status status, u32 index,
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u8 *event, size_t *bytes)
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{
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enum hab_status ret;
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hab_rvt_report_event_t *hab_rvt_report_event_func;
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struct arm_smccc_res res __maybe_unused;
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hab_rvt_report_event_func = (hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT;
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#if defined(CONFIG_ARM64)
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if (current_el() != 3) {
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/* call sip */
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arm_smccc_smc(FSL_SIP_HAB, FSL_SIP_HAB_REPORT_EVENT, (unsigned long)index,
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(unsigned long)event, (unsigned long)bytes, 0, 0, 0, &res);
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return (enum hab_status)res.a0;
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}
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#endif
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save_gd();
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ret = hab_rvt_report_event_func(status, index, event, bytes);
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restore_gd();
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return ret;
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}
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enum hab_status hab_rvt_report_status(enum hab_config *config, enum hab_state *state)
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{
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enum hab_status ret;
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hab_rvt_report_status_t *hab_rvt_report_status_func;
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struct arm_smccc_res res __maybe_unused;
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hab_rvt_report_status_func = (hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS;
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#if defined(CONFIG_ARM64)
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if (current_el() != 3) {
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/* call sip */
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arm_smccc_smc(FSL_SIP_HAB, FSL_SIP_HAB_REPORT_STATUS, (unsigned long)config,
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(unsigned long)state, 0, 0, 0, 0, &res);
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return (enum hab_status)res.a0;
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}
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#endif
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save_gd();
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ret = hab_rvt_report_status_func(config, state);
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restore_gd();
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return ret;
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}
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enum hab_status hab_rvt_entry(void)
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{
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enum hab_status ret;
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hab_rvt_entry_t *hab_rvt_entry_func;
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struct arm_smccc_res res __maybe_unused;
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hab_rvt_entry_func = (hab_rvt_entry_t *)HAB_RVT_ENTRY;
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#if defined(CONFIG_ARM64)
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if (current_el() != 3) {
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/* call sip */
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arm_smccc_smc(FSL_SIP_HAB, FSL_SIP_HAB_ENTRY, 0, 0, 0, 0, 0, 0, &res);
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return (enum hab_status)res.a0;
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}
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#endif
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save_gd();
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ret = hab_rvt_entry_func();
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restore_gd();
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return ret;
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}
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enum hab_status hab_rvt_exit(void)
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{
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enum hab_status ret;
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hab_rvt_exit_t *hab_rvt_exit_func;
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struct arm_smccc_res res __maybe_unused;
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hab_rvt_exit_func = (hab_rvt_exit_t *)HAB_RVT_EXIT;
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#if defined(CONFIG_ARM64)
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if (current_el() != 3) {
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/* call sip */
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arm_smccc_smc(FSL_SIP_HAB, FSL_SIP_HAB_EXIT, 0, 0, 0, 0, 0, 0, &res);
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return (enum hab_status)res.a0;
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}
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#endif
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save_gd();
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ret = hab_rvt_exit_func();
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restore_gd();
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return ret;
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}
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void hab_rvt_failsafe(void)
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{
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hab_rvt_failsafe_t *hab_rvt_failsafe_func;
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hab_rvt_failsafe_func = (hab_rvt_failsafe_t *)HAB_RVT_FAILSAFE;
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#if defined(CONFIG_ARM64)
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if (current_el() != 3) {
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/* call sip */
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arm_smccc_smc(FSL_SIP_HAB, FSL_SIP_HAB_FAILSAFE, 0, 0, 0, 0, 0, 0, NULL);
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return;
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}
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#endif
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save_gd();
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hab_rvt_failsafe_func();
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restore_gd();
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}
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enum hab_status hab_rvt_check_target(enum hab_target type, const void *start,
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size_t bytes)
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{
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enum hab_status ret;
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hab_rvt_check_target_t *hab_rvt_check_target_func;
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struct arm_smccc_res res __maybe_unused;
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hab_rvt_check_target_func = (hab_rvt_check_target_t *)HAB_RVT_CHECK_TARGET;
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#if defined(CONFIG_ARM64)
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if (current_el() != 3) {
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/* call sip */
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arm_smccc_smc(FSL_SIP_HAB, FSL_SIP_HAB_CHECK_TARGET, (unsigned long)type,
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(unsigned long)start, (unsigned long)bytes, 0, 0, 0, &res);
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return (enum hab_status)res.a0;
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}
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#endif
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save_gd();
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ret = hab_rvt_check_target_func(type, start, bytes);
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restore_gd();
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return ret;
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}
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void *hab_rvt_authenticate_image(uint8_t cid, ptrdiff_t ivt_offset,
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void **start, size_t *bytes, hab_loader_callback_f_t loader)
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{
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void *ret;
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hab_rvt_authenticate_image_t *hab_rvt_authenticate_image_func;
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struct arm_smccc_res res __maybe_unused;
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hab_rvt_authenticate_image_func = (hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE;
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#if defined(CONFIG_ARM64)
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if (current_el() != 3) {
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/* call sip */
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arm_smccc_smc(FSL_SIP_HAB, FSL_SIP_HAB_AUTHENTICATE, (unsigned long)ivt_offset,
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(unsigned long)start, (unsigned long)bytes, 0, 0, 0, &res);
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return (void *)res.a0;
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}
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#endif
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save_gd();
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ret = hab_rvt_authenticate_image_func(cid, ivt_offset, start, bytes, loader);
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restore_gd();
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return ret;
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}
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#if !defined(CONFIG_SPL_BUILD)
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#define MAX_RECORD_BYTES (8*1024) /* 4 kbytes */
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@ -253,12 +445,6 @@ static int get_hab_status(void)
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size_t bytes = sizeof(event_data); /* Event size in bytes */
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enum hab_config config = 0;
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enum hab_state state = 0;
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hab_rvt_report_event_t *hab_rvt_report_event;
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hab_rvt_report_status_t *hab_rvt_report_status;
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hab_rvt_report_event = (hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT;
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hab_rvt_report_status =
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(hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS;
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if (imx_hab_is_enabled())
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puts("\nSecure boot enabled\n");
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@ -493,7 +679,7 @@ static bool csf_is_valid(struct ivt *ivt, ulong start_addr, size_t bytes)
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return false;
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}
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csf_hdr = (u8 *)ivt->csf;
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csf_hdr = (u8 *)(ulong)ivt->csf;
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/* Verify if CSF Header exist */
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if (*csf_hdr != HAB_CMD_HDR) {
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@ -561,25 +747,15 @@ bool imx_hab_is_enabled(void)
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int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,
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uint32_t ivt_offset)
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{
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uint32_t load_addr = 0;
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ulong load_addr = 0;
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size_t bytes;
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uint32_t ivt_addr = 0;
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ulong ivt_addr = 0;
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int result = 1;
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ulong start;
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hab_rvt_authenticate_image_t *hab_rvt_authenticate_image;
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hab_rvt_entry_t *hab_rvt_entry;
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hab_rvt_exit_t *hab_rvt_exit;
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hab_rvt_check_target_t *hab_rvt_check_target;
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struct ivt *ivt;
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struct ivt_header *ivt_hdr;
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enum hab_status status;
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hab_rvt_authenticate_image =
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(hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE;
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hab_rvt_entry = (hab_rvt_entry_t *)HAB_RVT_ENTRY;
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hab_rvt_exit = (hab_rvt_exit_t *)HAB_RVT_EXIT;
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hab_rvt_check_target = (hab_rvt_check_target_t *)HAB_RVT_CHECK_TARGET;
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if (!imx_hab_is_enabled()) {
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puts("hab fuse not enabled\n");
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return 0;
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@ -591,7 +767,7 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,
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hab_caam_clock_enable(1);
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/* Calculate IVT address header */
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ivt_addr = ddr_start + ivt_offset;
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ivt_addr = (ulong) (ddr_start + ivt_offset);
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ivt = (struct ivt *)ivt_addr;
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ivt_hdr = &ivt->hdr;
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@ -601,7 +777,7 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,
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/* Verify IVT body */
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if (ivt->self != ivt_addr) {
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printf("ivt->self 0x%08x pointer is 0x%08x\n",
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printf("ivt->self 0x%08x pointer is 0x%08lx\n",
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ivt->self, ivt_addr);
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goto hab_authentication_exit;
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}
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@ -624,9 +800,9 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,
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goto hab_exit_failure_print_status;
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}
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status = hab_rvt_check_target(HAB_TGT_MEMORY, (void *)ddr_start, bytes);
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status = hab_rvt_check_target(HAB_TGT_MEMORY, (void *)(ulong)ddr_start, bytes);
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if (status != HAB_SUCCESS) {
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printf("HAB check target 0x%08x-0x%08x fail\n",
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printf("HAB check target 0x%08x-0x%08lx fail\n",
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ddr_start, ddr_start + bytes);
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goto hab_exit_failure_print_status;
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}
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@ -649,6 +825,8 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,
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printf("\tstart = 0x%08lx\n", start);
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printf("\tbytes = 0x%x\n", bytes);
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#endif
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#ifndef CONFIG_ARM64
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/*
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* If the MMU is enabled, we have to notify the ROM
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* code, or it won't flush the caches when needed.
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@ -676,8 +854,9 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size,
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writel(1, MX6SL_PU_IROM_MMU_EN_VAR);
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}
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}
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#endif
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load_addr = (uint32_t)hab_rvt_authenticate_image(
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load_addr = (ulong)hab_rvt_authenticate_image(
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HAB_CID_UBOOT,
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ivt_offset, (void **)&start,
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(size_t *)&bytes, NULL);
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