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powerpc: C29X: Move CONFIG_PPC_C29X to Kconfig option

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Replace CONFIG_PPC_C29X with ARCH_C29X in Kconfig and clean up existing
macros.

Signed-off-by: York Sun <york.sun@nxp.com>
This commit is contained in:
York Sun 2016-11-15 18:44:22 -08:00
parent a202b9f802
commit 4fd64746b0
9 changed files with 15 additions and 16 deletions
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4
arch/powerpc/cpu/mpc85xx/Kconfig
View file

@ -33,6 +33,7 @@ config TARGET_BSC9132QDS
config TARGET_C29XPCIE config TARGET_C29XPCIE
bool "Support C29XPCIE" bool "Support C29XPCIE"
select ARCH_C29X
select SUPPORT_SPL select SUPPORT_SPL
select SUPPORT_TPL select SUPPORT_TPL
select PHYS_64BIT select PHYS_64BIT
@ -185,6 +186,9 @@ config ARCH_BSC9131
config ARCH_BSC9132 config ARCH_BSC9132
bool bool
config ARCH_C29X
bool
config ARCH_MPC8544 config ARCH_MPC8544
bool bool

2
arch/powerpc/cpu/mpc85xx/Makefile
View file

@ -65,7 +65,7 @@ obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o
obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o obj-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
# SoC specific SERDES support # SoC specific SERDES support
obj-$(CONFIG_PPC_C29X) += c29x_serdes.o obj-$(CONFIG_ARCH_C29X) += c29x_serdes.o
obj-$(CONFIG_MPC8536) += mpc8536_serdes.o obj-$(CONFIG_MPC8536) += mpc8536_serdes.o
obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o obj-$(CONFIG_ARCH_MPC8544) += mpc8544_serdes.o
obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o obj-$(CONFIG_ARCH_MPC8548) += mpc8548_serdes.o

2
arch/powerpc/cpu/mpc85xx/cpu_init.c
View file

@ -959,7 +959,7 @@ int cpu_init_r(void)
#ifdef CONFIG_FSL_CAAM #ifdef CONFIG_FSL_CAAM
sec_init(); sec_init();
#if defined(CONFIG_PPC_C29X) #if defined(CONFIG_ARCH_C29X)
if ((SVR_SOC_VER(svr) == SVR_C292) || if ((SVR_SOC_VER(svr) == SVR_C292) ||
(SVR_SOC_VER(svr) == SVR_C293)) (SVR_SOC_VER(svr) == SVR_C293))
sec_init_idx(1); sec_init_idx(1);

4
arch/powerpc/include/asm/config_mpc85xx.h
View file

@ -914,7 +914,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_SFP_VER_3_0
#elif defined(CONFIG_PPC_C29X) #elif defined(CONFIG_ARCH_C29X)
#define CONFIG_MAX_CPUS 1 #define CONFIG_MAX_CPUS 1
#define CONFIG_FSL_SDHC_V2_3 #define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_NUM_LAWS 12
@ -955,7 +955,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_DDRC_GEN3 #define CONFIG_SYS_FSL_DDRC_GEN3
#endif #endif
#if !defined(CONFIG_PPC_C29X) #if !defined(CONFIG_ARCH_C29X)
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#endif #endif

10
arch/powerpc/include/asm/immap_85xx.h
View file

@ -2123,7 +2123,7 @@ typedef struct ccsr_gur {
#ifdef CONFIG_MPC8536 #ifdef CONFIG_MPC8536
#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
#elif defined(CONFIG_PPC_C29X) #elif defined(CONFIG_ARCH_C29X)
#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \ #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \
& MPC85xx_PORDEVSR2_DDR_SPD_0) \ & MPC85xx_PORDEVSR2_DDR_SPD_0) \
@ -2175,7 +2175,7 @@ typedef struct ccsr_gur {
#elif defined(CONFIG_ARCH_BSC9132) #elif defined(CONFIG_ARCH_BSC9132)
#define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000 #define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17
#elif defined(CONFIG_PPC_C29X) #elif defined(CONFIG_ARCH_C29X)
#define MPC85xx_PORDEVSR_IO_SEL 0x00e00000 #define MPC85xx_PORDEVSR_IO_SEL 0x00e00000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
#else #else
@ -2193,7 +2193,7 @@ typedef struct ccsr_gur {
#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
u32 pordbgmsr; /* POR debug mode status */ u32 pordbgmsr; /* POR debug mode status */
u32 pordevsr2; /* POR I/O device status 2 */ u32 pordevsr2; /* POR I/O device status 2 */
#if defined(CONFIG_PPC_C29X) #if defined(CONFIG_ARCH_C29X)
#define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008 #define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008
#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3 #define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3
#endif #endif
@ -2344,7 +2344,7 @@ typedef struct ccsr_gur {
#define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000 #define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000
#define MPC85xx_PMUXCR0_SIM_SEL 0x00014000 #define MPC85xx_PMUXCR0_SIM_SEL 0x00014000
#endif #endif
#if defined(CONFIG_PPC_C29X) #if defined(CONFIG_ARCH_C29X)
#define MPC85xx_PMUXCR_SPI_MASK 0x00000300 #define MPC85xx_PMUXCR_SPI_MASK 0x00000300
#define MPC85xx_PMUXCR_SPI 0x00000000 #define MPC85xx_PMUXCR_SPI 0x00000000
#define MPC85xx_PMUXCR_SPI_GPIO 0x00000100 #define MPC85xx_PMUXCR_SPI_GPIO 0x00000100
@ -2964,7 +2964,7 @@ struct ccsr_pman {
#endif #endif
#define CONFIG_SYS_MDIO1_OFFSET 0x24000 #define CONFIG_SYS_MDIO1_OFFSET 0x24000
#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
#if defined(CONFIG_PPC_C29X) #if defined(CONFIG_ARCH_C29X)
#define CONFIG_SYS_FSL_SEC_OFFSET 0x80000 #define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
#define CONFIG_SYS_FSL_JR0_OFFSET 0x81000 #define CONFIG_SYS_FSL_JR0_OFFSET 0x81000
#else #else

2
drivers/crypto/fsl/jr.c
View file

@ -21,7 +21,7 @@
uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = { uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
0, 0,
#if defined(CONFIG_PPC_C29X) #if defined(CONFIG_ARCH_C29X)
CONFIG_SYS_FSL_SEC_IDX_OFFSET, CONFIG_SYS_FSL_SEC_IDX_OFFSET,
2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET 2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET
#endif #endif

4
include/configs/C29XPCIE.h
View file

@ -11,10 +11,6 @@
#ifndef __CONFIG_H #ifndef __CONFIG_H
#define __CONFIG_H #define __CONFIG_H
#ifdef CONFIG_C29XPCIE
#define CONFIG_PPC_C29X
#endif
#ifdef CONFIG_SPIFLASH #ifdef CONFIG_SPIFLASH
#define CONFIG_RAMBOOT_SPIFLASH #define CONFIG_RAMBOOT_SPIFLASH
#define CONFIG_SYS_TEXT_BASE 0x11000000 #define CONFIG_SYS_TEXT_BASE 0x11000000

2
include/fsl_sec.h
View file

@ -303,7 +303,7 @@ struct sg_entry {
*/ */
int blob_dek(const u8 *src, u8 *dst, u8 len); int blob_dek(const u8 *src, u8 *dst, u8 len);
#if defined(CONFIG_PPC_C29X) #if defined(CONFIG_ARCH_C29X)
int sec_init_idx(uint8_t); int sec_init_idx(uint8_t);
#endif #endif
int sec_init(void); int sec_init(void);

1
scripts/config_whitelist.txt
View file

@ -3682,7 +3682,6 @@ CONFIG_PPC4xx_EMAC
CONFIG_PPC64BRIDGE CONFIG_PPC64BRIDGE
CONFIG_PPC_B4420 CONFIG_PPC_B4420
CONFIG_PPC_B4860 CONFIG_PPC_B4860
CONFIG_PPC_C29X
CONFIG_PPC_CLUSTER_START CONFIG_PPC_CLUSTER_START
CONFIG_PPC_P2041 CONFIG_PPC_P2041
CONFIG_PPC_P3041 CONFIG_PPC_P3041