mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
This commit is contained in:
commit
4ddc981225
13 changed files with 45 additions and 2 deletions
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@ -30,7 +30,8 @@ struct socfpga_sdr_ctrl {
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u32 dram_timing4; /* 0x10 */
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u32 lowpwr_timing;
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u32 dram_odt;
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u32 __padding0[4];
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u32 extratime1;
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u32 __padding0[3];
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u32 dram_addrw; /* 0x2c */
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u32 dram_if_width; /* 0x30 */
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u32 dram_dev_width;
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@ -88,6 +89,7 @@ struct socfpga_sdram_config {
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u32 dram_timing4;
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u32 lowpwr_timing;
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u32 dram_odt;
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u32 extratime1;
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u32 dram_addrw;
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u32 dram_if_width;
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u32 dram_dev_width;
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@ -427,6 +429,10 @@ SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
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/* Field instance: sdr::ctrlgrp::dramsts */
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#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
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#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
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/* Register template: sdr::ctrlgrp::extratime1 */
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#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20
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#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24
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#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28
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/* SDRAM width macro for configuration with ECC */
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#define SDRAM_WIDTH_32BIT_WITH_ECC 40
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File diff suppressed because one or more lines are too long
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@ -81,6 +81,13 @@ static const struct socfpga_sdram_config sdram_config = {
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SDR_CTRLGRP_DRAMODT_READ_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
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SDR_CTRLGRP_DRAMODT_WRITE_LSB),
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.extratime1 =
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(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
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SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
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SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
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SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
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.dram_addrw =
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(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
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SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) |
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@ -49,6 +49,9 @@
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
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#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
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#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
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#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
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@ -49,6 +49,9 @@
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
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#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
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#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
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#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
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@ -49,6 +49,9 @@
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
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#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
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#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
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#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
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@ -49,6 +49,9 @@
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
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#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
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#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
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#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
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@ -49,6 +49,9 @@
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
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#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
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#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
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#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x777
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@ -49,6 +49,9 @@
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 6
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
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#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
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#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
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#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
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@ -49,6 +49,9 @@
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
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#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
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#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
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#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x330
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@ -42,6 +42,9 @@
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
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#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
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#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
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#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
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@ -49,6 +49,9 @@
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
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#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
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#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
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#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
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#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
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#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF
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@ -418,6 +418,9 @@ static void sdr_load_regs(const struct socfpga_sdram_config *cfg)
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debug("Configuring DRAMODT\n");
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writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
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debug("Configuring EXTRATIME1\n");
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writel(cfg->extratime1, &sdr_ctrl->extratime1);
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}
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/**
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