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Merge https://source.denx.de/u-boot/custodians/u-boot-marvell

Browse source 
- Convert GoFlex Home Ethernet and SATA to Driver Model (Tony)
- mvebu: Automatically detect CONFIG_SYS_TCLK (Pavel)
- mvebu: sata_mv: Fix HDD identication during cold start (Tony)
- a37xx: pci: Fix handling PIO config error responses (Pavel)
- Other minor misc changes and board maintainer updates
This commit is contained in:
Tom Rini 2021-08-11 08:31:25 -04:00
commit 4dc1a5c248
26 changed files with 125 additions and 76 deletions
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2
arch/arm/mach-kirkwood/include/mach/kw88f6281.h
View file

@ -15,8 +15,6 @@
#define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE
/* TCLK Core Clock definition */
#ifndef CONFIG_SYS_TCLK
#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
#endif
#endif /* _ASM_ARCH_KW88F6281_H */

15
arch/arm/mach-mvebu/include/mach/soc.h
View file

@ -33,11 +33,6 @@
#define MV_88F68XX_A0_ID 0x4
#define MV_88F68XX_B0_ID 0xa
/* TCLK Core Clock definition */
#ifndef CONFIG_SYS_TCLK
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
#endif
/* SOC specific definations */
#define INTREG_BASE 0xd0000000
#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
@ -150,6 +145,9 @@
#define BOOT_FROM_UART 0x30
#define BOOT_FROM_SPI 0x38
#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \
200000000 : 166000000)
#elif defined(CONFIG_ARMADA_38X)
/* SAR values for Armada 38x */
#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600))
@ -170,6 +168,9 @@
#define BOOT_FROM_SPI 0x32
#define BOOT_FROM_MMC 0x30
#define BOOT_FROM_MMC_ALT 0x31
#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(15)) ? \
200000000 : 250000000)
#elif defined(CONFIG_ARMADA_MSYS)
/* SAR values for MSYS */
#define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200)
@ -186,6 +187,8 @@
#define BOOT_FROM_NAND 0x1
#define BOOT_FROM_UART 0x2
#define BOOT_FROM_SPI 0x3
#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
#else
/* SAR values for Armada XP */
#define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230))
@ -205,6 +208,8 @@
#define BOOT_FROM_UART 0x2
#define BOOT_FROM_SPI 0x3
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
#endif
#endif /* _MVEBU_SOC_H */

6
arch/arm/mach-mvebu/spl.c
View file

@ -345,7 +345,11 @@ void board_init_f(ulong dummy)
serdes_phy_config();
/* Setup DDR */
ddr3_init();
ret = ddr3_init();
if (ret) {
debug("ddr3_init() failed: %d\n", ret);
hang();
}
#endif
/* Initialize Auto Voltage Scaling */

2
board/Seagate/dockstar/MAINTAINERS
View file

@ -1,5 +1,5 @@
DOCKSTAR BOARD
M: Eric Cooper <ecc@cmu.edu>
M: Tony Dinh <mibodhi@gmail.com>
S: Maintained
F: board/Seagate/dockstar/
F: include/configs/dockstar.h

2
board/Seagate/goflexhome/MAINTAINERS
View file

@ -1,5 +1,5 @@
GOFLEXHOME BOARD
M: Suriyan Ramasami <suriyan.r@gmail.com>
M: Tony Dinh <mibodhi@gmail.com>
S: Maintained
F: board/Seagate/goflexhome/
F: include/configs/goflexhome.h

57
board/Seagate/goflexhome/goflexhome.c
View file

@ -1,5 +1,9 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2021
* Tony Dinh <mibodhi@gmail.com>
* Suriyan Ramasami <suriyan.r@gmail.com>
*
* Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com>
*
* Based on dockstar.c originally written by
@ -107,36 +111,65 @@ int board_init(void)
return 0;
}
static int fdt_get_phy_addr(const char *path)
{
const void *fdt = gd->fdt_blob;
const u32 *reg;
const u32 *val;
int node, phandle, addr;
/* Find the node by its full path */
node = fdt_path_offset(fdt, path);
if (node >= 0) {
/* Look up phy-handle */
val = fdt_getprop(fdt, node, "phy-handle", NULL);
if (val) {
phandle = fdt32_to_cpu(*val);
if (!phandle)
return -1;
/* Follow it to its node */
node = fdt_node_offset_by_phandle(fdt, phandle);
if (node) {
/* Look up reg */
reg = fdt_getprop(fdt, node, "reg", NULL);
if (reg) {
addr = fdt32_to_cpu(*reg);
return addr;
}
}
}
}
return -1;
}
#ifdef CONFIG_RESET_PHY_R
/* Configure and enable MV88E1116 PHY */
void reset_phy(void)
{
u16 reg;
u16 devadr;
char *name = "egiga0";
int phyaddr;
char *name = "ethernet-controller@72000";
char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0";
if (miiphy_set_current_dev(name))
return;
/* command to read PHY dev address */
if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
printf("Err..%s could not read PHY dev address\n",
__func__);
phyaddr = fdt_get_phy_addr(eth0_path);
if (phyaddr < 0)
return;
}
/*
* Enable RGMII delay on Tx and Rx for CPU port
* Ref: sec 4.7.2 of chip datasheet
*/
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2);
miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg);
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg);
miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0);
/* reset the phy */
miiphy_reset(name, devadr);
miiphy_reset(name, phyaddr);
printf("88E1116 Initialized on %s\n", name);
}

5
configs/goflexhome_defconfig
View file

@ -16,7 +16,6 @@ CONFIG_CONSOLE_MUX=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_SYS_PROMPT="GoFlexHome> "
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_IDE=y
CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
@ -48,3 +47,7 @@ CONFIG_SYS_NS16550=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_SATA=y
CONFIG_SATA_MV=y
CONFIG_DM_ETH=y
CONFIG_NET_RANDOM_ETHADDR=y

29
drivers/ata/sata_mv.c
View file

@ -809,6 +809,7 @@ static int mv_ata_exec_ata_cmd_nondma(struct udevice *dev, int port,
static int mv_sata_identify(struct udevice *dev, int port, u16 *id)
{
struct sata_fis_h2d h2d;
int len;
memset(&h2d, 0, sizeof(struct sata_fis_h2d));
@ -818,8 +819,32 @@ static int mv_sata_identify(struct udevice *dev, int port, u16 *id)
/* Give device time to get operational */
mdelay(10);
return mv_ata_exec_ata_cmd_nondma(dev, port, &h2d, (u8 *)id,
ATA_ID_WORDS * 2, READ_CMD);
/* During cold start, with some HDDs, the first ATA ID command does
* not populate the ID words. In fact, the first ATA ID
* command will only power up the drive, and then the ATA ID command
* processing is lost in the process.
*/
len = mv_ata_exec_ata_cmd_nondma(dev, port, &h2d, (u8 *)id,
ATA_ID_WORDS * 2, READ_CMD);
/* If drive capacity has been filled in, then it was successfully
* identified (the drive has been powered up before, i.e.
* this function is invoked during a reboot)
*/
if (ata_id_n_sectors(id) != 0)
return len;
/* Issue the 2nd ATA ID command to make sure the ID words are
* populated properly.
*/
mdelay(10);
len = mv_ata_exec_ata_cmd_nondma(dev, port, &h2d, (u8 *)id,
ATA_ID_WORDS * 2, READ_CMD);
if (ata_id_n_sectors(id) != 0)
return len;
printf("Err: Failed to identify SATA device %d\n", port);
return -ENODEV;
}
static void mv_sata_xfer_mode(struct udevice *dev, int port, u16 *id)

52
drivers/pci/pci-aardvark.c
View file

@ -177,7 +177,6 @@
#define LINK_MAX_RETRIES 10
#define LINK_WAIT_TIMEOUT 100000
#define CFG_RD_UR_VAL 0xFFFFFFFF
#define CFG_RD_CRS_VAL 0xFFFF0001
/**
@ -263,12 +262,12 @@ static int pcie_advk_wait_pio(struct pcie_advk *pcie)
* pcie_advk_check_pio_status() - Validate PIO status and get the read result
*
* @pcie: Pointer to the PCI bus
* @read: Read from or write to configuration space - true(read) false(write)
* @read_val: Pointer to the read result, only valid when read is true
* @allow_crs: Only for read requests, if CRS response is allowed
* @read_val: Pointer to the read result
*
*/
static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
bool read,
bool allow_crs,
uint *read_val)
{
uint reg;
@ -286,22 +285,16 @@ static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
break;
}
/* Get the read result */
if (read)
if (read_val)
*read_val = advk_readl(pcie, PIO_RD_DATA);
/* No error */
strcomp_status = NULL;
break;
case PIO_COMPLETION_STATUS_UR:
if (read) {
/* For reading, UR is not an error status. */
*read_val = CFG_RD_UR_VAL;
strcomp_status = NULL;
} else {
strcomp_status = "UR";
}
strcomp_status = "UR";
break;
case PIO_COMPLETION_STATUS_CRS:
if (read) {
if (allow_crs && read_val) {
/* For reading, CRS is not an error status. */
*read_val = CFG_RD_CRS_VAL;
strcomp_status = NULL;
@ -352,6 +345,7 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
enum pci_size_t size)
{
struct pcie_advk *pcie = dev_get_priv(bus);
bool allow_crs;
uint reg;
int ret;
@ -364,13 +358,17 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
return 0;
}
allow_crs = (offset == PCI_VENDOR_ID) && (size == 4);
if (advk_readl(pcie, PIO_START)) {
dev_err(pcie->dev,
"Previous PIO read/write transfer is still running\n");
if (offset != PCI_VENDOR_ID)
return -EINVAL;
*valuep = CFG_RD_CRS_VAL;
return 0;
if (allow_crs) {
*valuep = CFG_RD_CRS_VAL;
return 0;
}
*valuep = pci_get_ff(size);
return -EINVAL;
}
/* Program the control register */
@ -392,16 +390,20 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf,
advk_writel(pcie, 1, PIO_START);
if (!pcie_advk_wait_pio(pcie)) {
if (offset != PCI_VENDOR_ID)
return -EINVAL;
*valuep = CFG_RD_CRS_VAL;
return 0;
if (allow_crs) {
*valuep = CFG_RD_CRS_VAL;
return 0;
}
*valuep = pci_get_ff(size);
return -EINVAL;
}
/* Check PIO status and get the read result */
ret = pcie_advk_check_pio_status(pcie, true, &reg);
if (ret)
ret = pcie_advk_check_pio_status(pcie, allow_crs, &reg);
if (ret) {
*valuep = pci_get_ff(size);
return ret;
}
dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08x)\n",
offset, size, reg);
@ -511,9 +513,7 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
}
/* Check PIO status */
pcie_advk_check_pio_status(pcie, false, &reg);
return 0;
return pcie_advk_check_pio_status(pcie, false, NULL);
}
/**

1
include/configs/clearfog.h
View file

@ -17,7 +17,6 @@
* for DDR ECC byte filling in the SPL before loading the main
* U-Boot into it.
*/
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI

2
include/configs/controlcenterdc.h
View file

@ -20,8 +20,6 @@
* U-Boot into it.
*/
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
#define CONFIG_LOADADDR 1000000
/*

1
include/configs/crs3xx-98dx3236.h
View file

@ -12,7 +12,6 @@
#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) /* 64 MB */
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI

1
include/configs/db-88f6720.h
View file

@ -15,7 +15,6 @@
* for DDR ECC byte filling in the SPL before loading the main
* U-Boot into it.
*/
#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
/* I2C */
#define CONFIG_SYS_I2C_LEGACY

2
include/configs/db-88f6820-amc.h
View file

@ -10,8 +10,6 @@
* High Level Configuration Options (easy to change)
*/
#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI

2
include/configs/db-88f6820-gp.h
View file

@ -10,8 +10,6 @@
* High Level Configuration Options (easy to change)
*/
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/* I2C */
#define CONFIG_SYS_I2C_LEGACY
#define CONFIG_SYS_I2C_MVTWSI

1
include/configs/db-mv784mp-gp.h
View file

@ -16,7 +16,6 @@
* for DDR ECC byte filling in the SPL before loading the main
* U-Boot into it.
*/
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/* I2C */
#define CONFIG_SYS_I2C_LEGACY

1
include/configs/db-xc3-24g4xg.h
View file

@ -11,7 +11,6 @@
*/
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI

1
include/configs/ds414.h
View file

@ -18,7 +18,6 @@
* for DDR ECC byte filling in the SPL before loading the main
* U-Boot into it.
*/
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/* I2C */
#define CONFIG_SYS_I2C_LEGACY

6
include/configs/goflexhome.h
View file

@ -72,4 +72,10 @@
#define CONFIG_PHY_BASE_ADR 0
#endif /* CONFIG_CMD_NET */
/* SATA driver configuration */
#ifdef CONFIG_SATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_LBA48
#endif /* CONFIG_SATA */
#endif /* _CONFIG_GOFLEXHOME_H */

1
include/configs/helios4.h
View file

@ -17,7 +17,6 @@
* for DDR ECC byte filling in the SPL before loading the main
* U-Boot into it.
*/
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI

5
include/configs/lacie_kw.h
View file

@ -39,11 +39,6 @@
#endif
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*
* Core clock definition
*/
#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
/*
* SDRAM configuration
*/

2
include/configs/lsxl.h
View file

@ -13,11 +13,9 @@
#if defined(CONFIG_LSCHLV2)
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lschl.cfg
#define CONFIG_MACH_TYPE 3006
#define CONFIG_SYS_TCLK 166666667 /* 166 MHz */
#elif defined(CONFIG_LSXHL)
#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg
#define CONFIG_MACH_TYPE 2663
/* CONFIG_SYS_TCLK is 200000000 by default */
#else
#error "unknown board"
#endif

1
include/configs/maxbcm.h
View file

@ -15,7 +15,6 @@
* for DDR ECC byte filling in the SPL before loading the main
* U-Boot into it.
*/
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/* I2C */
#define CONFIG_SYS_I2C_LEGACY

1
include/configs/theadorable.h
View file

@ -15,7 +15,6 @@
* for DDR ECC byte filling in the SPL before loading the main
* U-Boot into it.
*/
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/*
* The debugging version enables USB support via defconfig.

1
include/configs/turris_omnia.h
View file

@ -16,7 +16,6 @@
* for DDR ECC byte filling in the SPL before loading the main
* U-Boot into it.
*/
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI

2
include/configs/x530.h
View file

@ -12,8 +12,6 @@
#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/*
* NS16550 Configuration
*/